AN12969A

AN12969A PANASONIC

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• Manufacturer or author: Provided By digicamel.com
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Technical content

Datasheet sections

1Publication date: October 2008 SDE00027BEB DATA SHEET AN12969APart No.

I2C bus control compatible AGC built-in stereo BTL amplifier IC (For driving a piezoelectric speaker) „ Overview AN12969A has a built-in AGC function in a stereo BTL amplifier for driving a piezoelectric speaker to prevent noise at output clip, and has a built-in a charge-pump power supply for driving speaker output amplifiers. And I2C bus control method is applied in switching of each mode like some Standby function is turned ON/OFF. „ Features yThe piezoelectric speaker can be driven by applying the circuit of high withstand voltage power amplifier. yOn level in AGC can be selected by controlling I2C bus. yAttack and recovery times in AGC can be selected by controlling I2C bus. yResistance and capacitor, which were used for conventional analog AGC aren’t needed anymore. yI2C is controlled almost in the same way as those of AN12959A. yShut-down function is mounted. yAmplifier gain switching yThe input circuit constructs a bus boost circuit easily and improves the sound quality of the piezoelectric speaker. yThe supply for speaker output amplifier isn’t needed anymore. „ Applications yAudio amplifier for mobile, such as a cellular phone „ Package y31 pin Plastic Quad 6 Column BGA Package(0.5 mm Pitch) „ Type ySilicon Monolithic Bi-CMOS IC

„ Application Circuit Example Note) This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set. *2 : The threshold voltage at Pin B3 has the VCC_D dependency. *3 : This block diagram is for explaining functions. The part of the block diagram may be omitted, or it may be simplified. B3 pin Operate voltage Shut-down < 0.26 VShut-down < 0.18 V Operate > 2.34 VOperate > 1.62 V VCC_D = 2.6 VVCC_D = 1.8 V Note) N.C. pin is without a solder ball. Diagram of pin names on package bottom face 0.31 mm0.5 mm 0.23 mm 2.96 mm 2.96 mm D C A GND SPL GND F GND GND CP E B 21 6543 GND_SPR VREF_SP LOUT_NEG GND_SPL ROUT_POS LOUT_POS F6GND_CP 1 μF +14 dB +14 dB VCC_SP 22 Ω 1 μF Charge Pump 22 Ω 22 Ω VBAT = 3.0 V – 4.5 V 2.2 μF 2.2 μF CPOUT C1N C1P VBATE5 E4 VREG_PRED 0.1 μF GND GND I2C-BUS Control VCC_D = 1.7 V – 3.3 V 2.2 kΩ 2.2 kΩ SCL SDA 1 μF VCC_D VCC = 2.7 V – 4.5 V 1 μF VCC B3Shutdown Operate 0.1 μF S.D VREF B2 1 μF INPUT_L INPUT_R PREOUT_L FB_L FB_R AGC AGC C1 ROUT_NEG +14 dB +14 dB 22 Ω AGC DET PREOUT_R 10 kΩ 1 500 pF 10 kΩ0.1 μF 10 kΩ 1 500 pF 10 kΩ0.1 μF D3GND +6 dB / 0 dB Gain Select +6 dB / 0 dB Gain Select CP OUT CP OUT C1P C1N ROUT POS VREG PRED VBAT VBAT GND SPR GND PRE OUTR FBR FBL ROUT NEG VCC SP VREF SP GND PRE OUTL LOUT NEG VREF SD GND SDA LOUT POS VCC VCCD SCL 390 Ω

„ Pin Descriptions First amplifier negative feedback input R-channelInputFB_RD5 N.C.—N.C.D2 First amplifier negative feedback input L-channelInputFB_LD6 First amplifier output R-channelOutputPREOUT_RD4 GroundingGroundGNDD3 First amplifier output L-channelOutputPREOUT_LC5 VCC_SP for the circuit of speaker outputPower SupplyVCC_SPC2 Speaker output R-channel (–) OutputROUT_NEGC1 GroundingGroundGNDA6 Power supply VCCPower SupplyVCCA3 VCC_D for logic circuit Power SupplyVCC_DA4 Speaker output L-channel (+) OutputLOUT_POSA2 Grounding (For speaker L-channel) GroundGND_SPLA1 Grounding (For speaker R-channel) GroundGND_SPRD1 N.C.—N.C.C6 GroundingGroundGNDC4 Reference voltage pin for the circuit of speaker outputInputVREF_SPC3 N.C.—N.C.B6 SDAInput / OutputSDAB5 GroundingGroundGNDB4 Shut-down pinInputS.DB3 Reference voltage pinInputVREFB2 Speaker output L-channel (–) OutputLOUT_NEGB1 SCLInputSCLA5 DescriptionTypePin namePin No.

„ Pin Descriptions (continued) VREG capacitor pin for charge pump gate-driverOutputVREG_PREDE4 GroundingGroundGNDF1 VBAT for Charge-pumpPower SupplyVBATE6 VBAT for Charge-pumpPower SupplyVBATE5 N.C.—N.C.E3 N.C.—N.C.E2 Charge-pump outputOutputCPOUTF2 Charge pump flying capacitor pin (−)OutputC1NF5 Charge pump flying capacitor pin (+)OutputC1PF4 Charge-pump outputOutputCPOUTF3 Grounding (For charge-pump)GroundGND_CPF6 Speaker output R-channel (+)OutputROUT_POSE1 DescriptionTypePin namePin No.

„ Absolute Maximum Ratings „ Operating supply voltage range 3.6VCC_D —A—ICCSupply current2 NoteUnitRangeSymbolParameterA No. °C–55 to +150TstgStorage temperature5 °C–20 to +70ToprOperating ambient temperature4 *2mW136PDPower dissipation3 *1V 5.0VCC,VBAT Supply voltage1 Note) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 : The power dissipation shown is the value at Ta = 70°C for the independent (unmounted) IC package with a heat sink. When using this IC, refer to the yPD-Ta diagram in the „Technical Data and design the heat radiation with sufficient margin so that the allowable value might not be exceeded based on the conditions of power supply voltage, load, and ambient temperature. *3 : Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C. V *1, *21.7 to 3.3 NoteUnitRangeSymbolParameter 3.0to 4.5VBAT VCC_D *12.7 to 4.5VCC Supply voltage range Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The I 2C bus of this product is designed to correspond to Standard mode(100 Kbps) and Fast mode(400 Kbps) in Philips Corporation I2C

4628— —dBV13.612.611.6 VIN = –6.0 dBV, f = 1 kHz, RL = 100 Ω, VBAT = 4.3 V, AGC – SELECT = [000] VSPOA1L VSPOA1RSP AGC output level 14 —μA1.00.1—Non-signal, STB = ON, SP_SAVE = ON, AGC = ONIVCC3BCircuit current 3B at non-signal6 —mA1.00.5—Non-signal, STB = OFF, SP_SAVE = ON, AGC = ONIVCC1CCircuit current 1C at non-signal7 —μA100.1—Non-signal, STB = OFF, SP_SAVE = OFF, AGC = ONIVCC3ACircuit current 3A at non-signal3 —μA100.1—Non-signal, STB = OFF, SP_SAVE = ON, AGC = ONIVCC3CCircuit current 3C at non-signal9 —mA2319—Non-signal, STB = OFF, SP_SAVE = ON, AGC = ONIVCC2CCircuit current 2C at non-signal8 —μA1.00.1—Non-signal, STB = ON, SP_SAVE = ON, AGC = ON IVCC2BCircuit current 2B at non-signal5 —μA1.00.1—Non-signal, STB = ON, SP_SAVE = ON, AGC = ONIVCC1BCircuit current 1B at non-signal4 —mANon-signal, STB = OFF, SP_SAVE = OFF, AGC = ONIVCC2ACircuit current 2A at non-signal2 I/O Characteristics VIN = –26.0 dBV, f = 1 kHz, RL = 100 Ω, to THD5th —dBV1.00.0–1.0VIN = –26.0 dBV, f = 1 kHz, RL = 100 Ω VSPOL VSPORSP reference output level10 —%0.50.07—THSPOL THSPORSP reference output distortion11 —dBV–68–75—Non-Signal using A curve filterVNSPOL VNSPORSP reference output noise voltage 12 —dBV–90–114—VIN = –26.0 dBV, f = 1 kHz, RL = 100 Ω using A curve filter VSSPOL VSSPOROutput level at SP Save13 Circuit Current —mA1.00.5—Non-signal, STB = OFF, SP_SAVE = OFF, AGC = ON IVCC1ACircuit current 1A at non-signal1 Limits Typ Unit Max Note Min ConditionsSymbolParameterB No. „ Electrical Characteristics Note) Unless otherwise specified, T a = 25°C±2°C, VCC = 3.0 V,VCC_D = 1.8 V, VBAT =3.8 V

The threshold voltage at Pin B3 —kHz400—0—fSCL Max. frequency of SCL signal allowable to input19 —V0.1 × VCC_D ———VsdlthShut-down input Low level20 I2C interface —V——0.9 × VCC_D —VsdhthShut-down input High level21 —μA10—–10Input voltage 0.1 V to 1.7 VIiSCL, SDA signal input current18 —V0.2 × VCC_D —0Open corrector, sync current : 3mAVOLSDA signal output Low Level17 —VVCC_D + 0.5—0.7 × VCC_D —VIHSCL, SDA signal input High level16 —V0.3 × VCC_D —–0.5—VILSCL, SDA signal input Low level15 Limits Typ Unit Max Note Min ConditionsSymbolParameterB No. „ Electrical Characteristics (continued) Note) Unless otherwise specified, T a = 25°C±2°C, VCC = 3.0 V,VCC_D = 1.8 V, VBAT =3.8 V

—MHz—1.25——fCPOscillation frequency32 I2C interface —μs——0.6—tSU;STOSetup time of stop condition31 —μs0.9—0—tHD;DATData hold time30 —μs——0.1—tSU;DATData setup time29 —μs0.3———tFFalling time of SDA, SCL signal28 —μs——1.3—tBUF Bus free time between stop and start conditions22 —μs——0.6tSU;STASetup time of start condition23 —μs——0.6—tHD;STAHold time of start condition24 —μs——1.3tLowLow period of SCL clock 25 —μs——0.6—tHighHigh period of SCL clock26 —μs0.3——tRRising time of SDA, SCL signal27 Reference values Typ Unit Max Note Min ConditionsSymbolParameterB No. „ Electrical Characteristics (Reference values for design) Note) Unless otherwise specified, Ta = 25°C±2°C, VCC = 3.0 V,VCC_D = 1.8 V, VBAT =3.8 V The characteristics listed below are reference values for design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to user concerns.

tSU;DAT tHD;DAT tSU;STOtSU;STAtHD;STA tRtF tLow tHigh START CONDITION SDA SCL tR tF tHD;STA STOP CONDITION Repeated START CONDITION START CONDITION VIHmin VILmax (*2) (*3) Note) 1. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. 2. *1: All values are V IHmin (*2) and VILmax (*3) level standard. *2: V IHmin is the minimum limit of the signal input high level is indicated. *3: V ILmax is the maximum limit of the signal input low level is indicated. „ Electrical Characteristics (Reference values for design) (Continued) Note) Unless otherwise specified, Ta = 25°C±2°C, VCC = 3.0 V,VCC_D = 1.8 V, VBAT =3.8 V The characteristics listed below are reference values for design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to user concerns.

Two transmission messages (i.e. the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following description provides information on the structure of the frame. <Start Conditions> When the level of the SDA changes to low from high while the level of the SCL is high, the data reception of the receiver will be enabled. <Stop Conditions> When the level of the SDA changes to high from low while the level of the SCL is high, the data reception of the receiver will be aborted. <Slave Address> The slave address is a specified one unique to each device. When the address of another device is sent, the reception will be aborted. <Sub-Address> The sub-address is a specified one unique to each function. <Data> Data is information under control. <Acknowledge Bit> The acknowledge bit is used to enable the master to acknowledge the reception of data for each octet. The master acknowledges the data reception of the receiver by transmitting a high-level signal to the receiver and receiving a low-level signal returned from the receiver as shown by the dotted lines in the above Fig. The communication will be aborted if the low signal is not returned. The SDA will not change when the level of the SCL is high except start or stop conditions are enabled. SDA SCL START CONDITION SLAVE ADDRESS ACK SUB ADDRESS ACK DATA ACK STOP CONDITION 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 01 8 0 1 0 0 0 0 0 0 0 Example of transmission messages „ Technical Data 1. I2C-bus Mode 1) Write Mode

(b) Auto increment Auto increment mode (When the data is sent in sequence, the sub-address will change one by one and the data will be input.) Auto increment mode (c) Initial condition The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0(Note.1) will be absolutely "0", when the power is turned ON. (d) Sub-address Byte and Data Byte Format (*1,*2) AGC-ATT data bit1 AGC-ATT data bit2 AGC-REC data bit1 AGC-REC data bit2 AGC-REC data bit3 AGC-ON data bit1 AGC-ON data bit2 AGC-ON data bit3*1Hex (*1,*2) (*1,*2) All Standby 0 → ON 1 → OFF (*1) SP Save 0 → ON 1 → OFF (*1,*2) D1 D0 LSB (*1,*2) AGC 0 → OFF 1 → ON (*1,*2) (*1) (*1,*2) (*1) (*1) Data byte (*1,*2)*2Hex GAIN 0 → +20 dB 1 → +26 dB *0Hex MSBSub- address Note) *1: <00Hex Register> D0, D4, D5, D6 : Always set to "0" D1 : SP and charge-pump standby ON/OFF switch D2 : SP Save ON/OFF switch D3 : AGC ON/OFF switch D7 : GAIN +20 dB / +26 dB selection <01Hex Register> D0, D1: AGC-attack-time selection D2, D3, D4 : AGC-recovery-time selection D5, D6, D7 : AGC-on-level selection <02Hex Register> D0 to D7 : Always set to "0". (test & adjust mode). *2: Please use these bit only Data = "0", because they are used by our company’s final test and fine-tuning AGC-on level. Note that Data = "1" is not shut-down mode. PAData 1 A A Data n Data 2ASub-addressAWSlave addressS „ Technical Data (continued) 1. I2C-bus Mode (continued) 1) Write Mode (continued) (a) I2C-bus PROTOCOL x Slave address : 10110110 (B6Hex) x Format (Normal) Start condition Stop condition Acknowledge bitWrite Mode : 0 PAData byteASub-addressAWSlave addressS

„ Technical Data (continued) 1. I2C-bus Mode (continued) 1) Write Mode (continued) (e) AGC-attack-time selection (f) AGC-recovery-time selection 0.5 ms00 1m s10 Write 01Hex Register 4 ms11 2 ms01 Attack time D0D1 1.0 s000 4.0 s001 6.0 s101 2.0 s010 Write 01Hex Register 3.0 s10 Recovery time 1.5 s0 (g) AGC-on-level selection at VCC = 3.0 V, VCC_D = 1.8 V, VBAT = 3.8 V *1 12 V[p-p]12.6 dBV000 16.6 dBV 16.1 dBV 15.6 dBV 15.1 dBV 14.5 dBV 13.9 dBV 13.2 dBV AGC On Level

19 V[p-p]

18 V[p-p]

17 V[p-p]

16 V[p-p]

15 V[p-p]

14 V[p-p]

13 V[p-p]

(V[p-p]) 001 101 010 011 Write 01Hex Register (h) Amp. gain selection at VCC = 3.0 V, VCC_D = 1.8 V, VBAT = 3.8 V Note) *1: At the time of V BAT = 3.1 V, output is clipped, excessive clip in AGC OFF can be prevented. 26 dB1 20 dB0 Gain Write 00Hex Register

„ Technical Data (continued) 1. I2C-bus Mode (continued) 2) Read Mode (a) I2C-bus PROTOCOL Slave address 10110111(B7Hex) Format Read Mode : 1 (b) Sub-address Byte and Data Byte Format Sub-address *1Hex Latch data D0 Sub-address *1Hex Latch data D1 Sub-address *1Hex Latch data D2 Sub-address *1Hex Latch data D3 Sub-address *1Hex Latch data D4 Sub-address *1Hex Latch data D5 Sub-address *1Hex Latch data D6 Sub-address *1Hex Latch data D7 Data 1 Sub-address *0Hex Latch data D0 Sub-address *0Hex Latch data D1 Sub-address *0Hex Latch data D2 Sub-address *0Hex Latch data D3 Sub-address *0Hex Latch data D4 Sub-address *0Hex Latch data D5 Sub-address *0Hex Latch data D6 Sub-address *0Hex Latch data D7 Data 0 Data byte Data 2 Sub-address *2Hex Latch data D1 Sub-address *2Hex Latch data D0 LSB Sub-address *2Hex Latch data D2 Sub-address *2Hex Latch data D3 Sub-address *2Hex Latch data D4 Sub-address *2Hex Latch data D5 Sub-address *2Hex Latch data D6 D6D7 Sub-address *2Hex Latch data D7 MSB Note) At the slave address input, it is sequentially output from Data 0. There is no necessity for inputting the sub-address. PAData 1 A Data 2AData 0ARSlave addressS

„ Technical Data (continued) 2. Operating temperature guarantee of I2C-bus Control The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25°C) by inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control. But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to customer concerns. 3. Usage note of I2C-bus 1. The I 2C bus of this product is designed to correspond to Standard mode(100 Kbps) and Fast mode(400 Kbps) in Philips Corporation I2C specification version 2.1. However, not correspond to High Speed mode (< 3.4Mbps). 2. This product operate as a slave device in I 2C bus system. 3. This product is not confirmed to operate in multi-master bus system and mixing -speed bus system. And this product is not confirmed connectivity to CBUS receiver. If using this product in these mode, please confirm availability to our company. 4. Purchase of Panasonic I 2C components conveys a license to use these components in an I2C systems under the Philips I2C patent right on condition that using condition conform to I2C standard specification approved by Philips Corporation.

Ground pin.—— GND DC 0 V I 2C-BUS SCL pinInput impedance = Hi-Z SCL Hi-Z Power supply pin for I2C-BUS—— VCC_D 1.8 V(typ.) Power supply pin—— VCC 3.0 V(typ.) Ground pin for L-channel speaker output—— GND_SPL DC 0 V Output impedance = Equal to or less than 1 Ω Impedance L-channel positive speaker output pin LOUT_POS DC 2.7 V DescriptionInternal circuitWaveform and voltage Pin No. „ Technical Data (continued) 4. I/O block circuit diagram and pin function descriptions Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. 20k VCC_SP(6.1 V) GND_SPL VCC_D (1.8 V)

Please do not make it open, because the open S.D pin is not fixed. Input impedance = Hi-Z S.D Hi-ZB3 The reference voltage terminal for determining DC bias of the input stage of a speaker amplifier system. Please connect an external capacitor to remove a ripple. Input impedance = About 75 kΩ VREF DC 2.5 V Output impedance = Equal to or less than 1 Ω Impedance L-channel negative speaker output pin LOUT_NEG DC 2.7 V DescriptionInternal circuitWaveform and voltage Pin No. „ Technical Data (continued) 4. I/O block circuit diagram and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. 20k GND_SPL VCC_SP(6.1 V) B2 150k 150k VREG(5 V) VCC_D (1.8 V)

R-channel negative speaker output pin Output impedance = Equal to or less than 1 Ω ROUT_NEG DC 2.7 V Power supply pin for speaker output. Please connect to F2,F3 Pin (CPOUT), and connect an external capacitor to remove a rippule. VCC_SP 2×VBAT N.C.——N.C. I 2C-BUS SDA pinInput impedance = Hi-Z SDA Hi-Z Impedance DescriptionInternal circuitWaveform and voltage Pin No. „ Technical Data (continued) 4. I/O block circuit diagram and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. VCC_D (1.8 V) GND VCC_SP(6.1 V) 20k GND_SPR

Output terminal of R-channel input amplifier of speaker amplifier system. Please connect external resistance for the gain setting. Output impedance = Equal to or less than 10 Ω PREOUT_R DC 2.5 V GND pin for R-channel speaker output—— GND_SPR DC 0 V Output terminal of L-channel input amplifier of speaker amplifier system. Please connect external resistance for the gain setting. Output impedance = Equal to or less than 10 Ω PREOUT_L DC 2.5 V The reference voltage terminal for determining DC bias of the output stage of a speaker amplifier system. Please connect an external capacitor to remove a ripple. Input impedance = About 150 kΩ VREF_SP DC 2.7 V Impedance DescriptionInternal circuitWaveform and voltage Pin No. „ Technical Data (continued) 4. I/O block circuit diagram and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. VCC_SP(6.1 V) 10k 300k 300k VREG(5 V) VREG(5 V)

„ Technical Data (continued) 4. I/O block circuit diagram and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. R-channel positive speaker output pin Output impedance = Equal to or less than 1 Ω ROUT_POS DC 2.7 V VREG capacitor pin for charge pump gate-driver Output impedance = Equal to or less than 1 VREG_PRED DC CPOUT * 0.45 Input impedance = Hi-Z Input impedance = Hi-Z Impedance Feedback terminal of L-channel input amplifier of speaker amplifier system. The gain of the L-channel input amplifier can be set by connecting an external resistance between Pin C4 and Pin C5. FB_L DC 2.5 V Feedback terminal of R-channel input amplifier of speaker amplifier system. The gain of the R-channel input amplifier can be set by connecting an external resistance between Pin D4 and Pin D5. FB_R DC 2.5 V DescriptionInternal circuitWaveform and voltage Pin No. VREG(5 V) GND VREG(5 V) GND 20k VCC_SP(6.1 V) GND_SPR 75k 25k GND_CP

Power supply pin—— VBAT 3.8 V(typ.) Ground pin for charge-pump.—— GND_CP DC 0 V 1Ω ≤ 1Ω ≤ 1Ω ≤ Impedance Charge-pump flying capacitor connect pin. C1P 1.25MHz VBAT to CPOUT Charge-pump flying capacitor connect pin. C1N 1.25MHz GND to VBAT Charge-pump output pin Please connect an external capacitor to remove a ripple. CPOUT VBAT*2 DescriptionInternal circuitWaveform and voltage Pin No. „ Technical Data (continued) 4. I/O block circuit diagram and pin function descriptions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. VBAT (3.8 V) GND_CP VBAT (3.8 V) GND_CP VBAT (3.8 V) GND_CP

„ Technical Data (continued) 5. Power supply and logic sequence Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. 2) The sequence of V BAT and VCC and VCC_D This IC does not have a rising and falling order in VBAT and VCC and VCC_D. Rising and falling times of them are recommended 1 ms or more. Note) *1: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off. It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and resistance linked to an input terminal (IN_R and IN_L). It is a recommendation value in a constant given in the example of an application circuit (block diagram). Power supply Standby SP_Save 30 ms or more *1 VBAT,V CC, VCC_D, SD After at least 30 ms has passed after the standby off, please off SP_Save. Off On Off Off On On On On Off Off On Off The basic procedure at the power-on 0 ms or more Please get Standby On simultaneously with or after SP_Save On. The basic procedure at the power-off 1. The power OFF condition. Both the Standby and the SP_Save are in the ON condition. 2. Power ON 3. Standby OFF 4. SP_Save OFF 1. The power ON condition. Both the Standby and the SP_Save are in the OFF condition. 2. SP_Save ON (= Standby ON) 3. Standby ON 4. Power OFF Please turn on the power supply first, and then get Standby OFF. The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop performance caused in switching. 1) The sequence of the power supply and each logic VBAT VCC VCC_D Off On On Off 1 ms 以上 1 ms or more 1 ms 以上 1 ms or more

„ Technical Data (continued) 5. Power supply and logic sequence (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. 3) The sequence of the charge-pump. Power supply Standby CPOUT Off On Off On On Off About 2msec : CPOUT rise time About 3msec : CPOUT fall time Note) *1: Charge-pump output CPOUT almost outputs the voltage of VBAT at the time of Standby. Also, it has a built-in discharge circuit of CPOUT pin and operates discharge to CPOUT < (VBAT + 0.9 [V]) at the time of Standby. *2: Please take more than 5msec between Standby Off and next Standby On. On Off More than 5msec VBAT,V CC, VCC_D, SD

6.1 Power supply

1) Power supply for output amplifier The output amplifier operates with voltage applied to VCC_SP. VCC_SP is supplied from built-in charge-pump with output voltage of twice VBAT. 2) Power supply for control system The control system operates with power supply applied to VCC pin. (I2C logic, clock generation circuit, etc.) 3) Power supply for signal system The signal system operates with the internal regulator of 5 V. 5 V, reference voltage of the internal regulator is generated from VCC_SP using VCC power supply. By setting signal voltage at 5 V, the dynamic range of the signal can be secured sufficiently. When the gain of the input amplifier is 0 dB, clip occurs at the amplitude of 3 V[p-p] (typ.) in input signal. 4) Power supply for I 2C interface I2C interface operates with power supply applied to VCC_D pin. I2C circuit operates with VCC. 5) High voltage at shut-down pin Please use the power supply applied to VCC_D or apply voltage from the outside. Threshold voltage depends on the voltage to VCC_D. „ Technical Data (continued) 6. Explanation on mainly functions Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. AN12969A output maximum amplitude VBAT × 2 − 1.3 V (typ.)

1) The gain for a speaker amplifier can be adjusted, as the gain for a input amplifier can be set with an external resistance. Input impedance is also set with the external resistance. When the gain for the input amplifier is set at ±0 dB, the total gain for the speaker amplifier is +26 dB or +20 dB (It can be selected with I2C). When the external resistance for the input amplifier is assumed as R1, R2, Gain = 20 log(R2 / R1) Zin = R1 In case of R1 = 10 kΩ, R2 = 10 kΩ with the constants in the above fig, the gain for the input amplifier is ±0 dB and impedance is 10 kΩ. During operation, keep the voltage of R1 and R2 at more than 5 kΩ. 2) With an external capacity added to the input amplifier, LPF, which removes an unwanted high frequency element, can be constructed. When external resistance is assumed as R2, capacity as C2, In case of R2 = 10 kΩ, C2 = 1500 pF with the constants in the above fig, Cut-off frequency, fc is 10.6 kHz. „ Technical Data (continued) 6. Explanation on mainly used functions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

6.2 Speaker amplifier

LOUT_NEG LOUT_POSAGC +14 dB +14 dB AGC DET INPUT_L 10 kΩ 10 kΩ 1500 pF 0 dB BTL : +6 dB +6 dB / 0 dB I2C Logic 0.1 μF

6.2 Speaker amplifier (continued)

3) With the smaller capacity of the input AC coupling capacitor, HPF, which removes unwanted low frequency element, can be constructed. When input resistance is assumed as R1, and AC coupling capacitor as C1, In case of R1 = 10 kΩ, C1 = 0.1 μF, cut-off frequency, fc is 160 Hz. In case of R1 = 10 kΩ, C1 = 0.022 μF, cut-of frequency, fc is 720 Hz. 4) Bus Boost circuit can be constructed by adding capacity (RBB) and resistance (CBB) to the input amplifier. The frequency to increase 3 dB is assumed as fo

6.3 Protection circuit for speaker amplifier

1) Thermal protection circuit The thermal protection circuit operates at the Tj of approximately 150°C. The thermal protection circuit is reset automatically when the temperature drops. 2) Output pin short protection circuit Output pin-power supply line short protection Output-to-output pin short protection Output pin-GND line short protection If short-circuit is no longer detected, it will return automatically. Note) Operation is not guaranteed although the protection circuit is built in. Moreover, hundred percent inspection is not guaranteed. „ Technical Data (continued) 6. Explanation on mainly used functions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. 0.1 μF 20 log ((Rf + RBB) / Rin)Ao = 20 log ((Rf + RBB) / Rf)Bus Boost Gain 1 / (2 ×π × Rf × CBB)fo = CIN Rf Cf RBB CBB RIN

6.4 Cautions

1) Cautions about AGC Signal output in the input amplifier is detected and converted to forward current. Compared this forward current with reference voltage, if the forward current is larger, AGC turns ON. When the frequency band of the speaker is narrower than that of the amplifier. If maximum input is made in low frequency band, AGC operates to decrease volume. Namely, low sound part is not heard from a speaker, but AGC reacts to low sound part to turn down the volume. Please carefully design so that the frequency bands is synchronized between the speaker and amplifier. Note) Frequency characteristics should be set not only for the speaker, but in the built-in condition The below Graph shows when the values of resistance and capacity are changed. „ Technical Data (continued) 6. Explanation on mainly used functions (continued) Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. Frequency Characteristics ＡＮ１２９６９Ａ -15 -10 0.01 0.1 1 10 100 Input Frequency (kHz) Output level （ｄBV) VccSP=9V Vin=-22dBV AGC OFF Cin=0.039uF Cf=1500pF Rin=10K RF=5.6K CBB=0.015uF RBB=10K Cin=0.1uF Cf=1500pF Rin=10K RF=10K CBB=0 RBB=0 2) Cautions about shut-down with SD pin During normal operation, when a shut-down pin is turned Low directly, shock noise comes out. As SP_Save is set in mute, first turn ON SP_Save, and then turn ON Standby to stop operation. Finally, set shut-down pin to Low.

„ Technical Data (continued) 7. PD —T a diagram

„ Usage Notes 1. This IC is intended to be used for general electronic equipment [cellular phones]. Consult our sales staff in advance for information on the following applications: x Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body. x Any applications other than the standard applications intended. (1) Space appliance (such as artificial satellite, and rocket) (2) Traffic control equipment (such as for automobile, airplane, train, and ship) (3) Medical equipment for life support (4) Submarine transponder (5) Control equipment for power plant (6) Disaster prevention and security device (7) Weapon (8) Others : Applications of which reliability equivalent to (1) to (7) is required 2. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it migh t smoke or ignite. 3. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description for the pin configuration. 4. Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as a solder- bridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin- V CC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short) . And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 6. When using the LSI for new models, verify the safety including the long-term reliability for each product. 7. When the application system is designed by using this LSI, be sure to confirm notes in this book. Be sure to read the notes to descriptions and the usage notes in the book. 8. Please carry out the thermal design with sufficient margin such that the power dissipation will not be exceeded, based on the conditions of power supply, load and surrounding temperature. Although indicated also in the column of the maximum rating, the maximum rating becomes an instant and the marginal value which must not exceed. It sufficiently evaluates, and I use-wish-do so that it may not exceed certainly. Moreover, don't impress neither voltage nor current to PIN which is not indicated. It may destroy in both cases. 9. Please do not make it open, because the open SD pin (Pin B3) is not fixed.

Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: – Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod- ucts may directly jeopardize life or harm the human body. – Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or im- provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805