AN12959A

AN12959A PANASONIC

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• Manufacturer or author: Provided By digicamel.com
• PDF pages: 27

Technical content

Datasheet sections

1Publication date: October 2008 SDE00028BEB AN12959APart No.

I2C bus control compatible AGC built-in stereo BTL amplifier IC (For driving a piezoelectric speaker) „ Overview AN12959A has a built-in AGC function in a stereo BTL amplifier for driving a piezoelectric speaker to prevent noise at output clip. And I2C bus control method is applied in switching of each mode like some Standby function is turned ON/OFF. „ Features yThe piezoelectric speaker can be driven by applying the circuit of high withstand voltage power amplifier. yOn level in AGC can be selected by controlling I2C bus. yAttack and recovery times in AGC can be selected by controlling I2C bus. yResistance and capacitor, which were used for conventional analog AGC aren’t needed anymore. yI2C is controlled almost in the same way as those of AN12979A/AN12978A. yShut-down function is mounted. yAmplifier gain switching yThe input circuit constructs a bus boost circuit easily and improves the sound quality of the piezoelectric speaker. „ Applications yAudio amplifier for mobile, such as a cellular phone „ Package y21 pin plastic quad 5 column BGA package (0.5 mm pitch) „ Type ySilicon Monolithic Bi-CMOS IC

„ Application Circuit Example (Block Diagram) Note) 1. This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set. 2. *:The threshold voltage at Pin B3 has the VCC_D dependency. E2 E3 E4 A2 B2 B3 A3 B4 A4 ROUT_NEG +14 dB GND_SPR VREF_SP VCC_SP = 6.1 V 1 μF +14 dB LOUT_NEG GND_SPL ROUT_POS LOUT_POS Piezoelectric speaker 10 kΩ 1500 pF 10 kΩ 0.1 μF INPUT_L 10 kΩ 1500 pF 10 kΩ 0.1 μF INPUT_R PREOUT_L PREOUT_R FB_L FB_R GND GND I2C-BUS Control VCC_D = 1.8 V 2.2 kΩ 2.2 kΩ SCLSDA 1 μF Shutdown Operate 0.1 μF S.D VCC_D N.C. 1 μF VREF VCC = 3 V 1 μF AGC AGC DET +6 dB / 0 dB +6 dB / 0 dB VREG (5 V) +14 dB +14 dB C3D3D2 Gain Select Gain Select N.C. GND N.C. VCC VCC_D VCC_SP 7.5 Ω to 10 Ω 7.5 Ω to 10 Ω 7.5 Ω to 10 Ω 7.5 Ω to 10 Ω 1 μF AGC − Piezoelectric speaker B3 pin Operate voltage Shut-down < 0.26 VShut-down < 0.18 V Operate > 2.34 VOperate > 1.62 V VCC_D = 2.6 VVCC_D = 1.8 V

„ Pin Descriptions GroundingGroundGNDE5 Power supply VCCPower SupplyVCCE4 Reference voltage pinInputVREFE3 Speaker output R-channel(+)OutputROUT_POSE2 Grounding (For speaker R-channel) GroundGND_SPRE1 First amplifier negative feedback input R-channelInputFB_RD5 First amplifier output R-channelOutputPREOUT_RD4 GroundingGroundGNDD3 N.C.—N.C.D2 Speaker output R-channel(–) OutputROUT_NEGD1 First amplifier negative feedback input L-channelInputFB_LC5 First amplifier output L-channelOutputPREOUT_LC4 N.C.—N.C.C3 Reference voltage pin for the circuit of speaker outputInputVREF_SPC2 VCC_SP for the circuit of speaker outputPower SupplyVCC_SPC1 SDAInput / OutputSDAB4 Shut-down pin—S.DB3 N.C.—N.C.B2 Speaker output L-channel(–) OutputLOUT_NEGB1 GroundingGroundGNDA5 SCLInputSCLA4 VCC_D for logic circuit Power SupplyVCC_DA3 Speaker output L-channel (+) OutputLOUT_POSA2 Grounding (For speaker L-channel) GroundGND_SPLA1 DescriptionTypePin namePin No.

„ Absolute Maximum Ratings „ Operating Supply Voltage Range Operating ambient temperature5 Power dissipation4 Input voltage3 Supply current2 12VCC_SP —A—ICC —V—VI *3°C–20 to +70Topr *2mW113PD 3.6VCC_D NoteUnitRatingSymbolParameterA No. °C–55 to +150TstgStorage temperature6 *1V 5.0VCC Supply voltage1 *1, *21.7 to 2.6 *12.7 to 4.5VCC 5.9 to 11.5VCC_SP NoteUnitRangeSymbolParameter *1, *3 V 1.7 to 3.3 VCC_DSupply voltage range Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The values under FAST- mode. *3: The values under STANDARD- mode. Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at T a = 70°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the • PD –T a diagram in the „Technical Data and use under the condition not exceeding the allowable value. *3: Except for the powe r dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C.

—%0.50.07— —mA6.54.5— —μA1.00.1— —mA1.00.5— Vin = –26.0 dBV, f = 1 kHz, RL = 100 Ω, to THD 5th THSPOL THSPORSP reference output distortion Non-signal, STB = OFF, SP = OFF, AGC = ONIVCC2CCircuit current 2C at non-signal (VCC_SP) Non-signal, STB = ON, SP = OFF, AGC = ON IVCC2BCircuit current 2B at non-signal (VCC_SP) Non-signal, STB = OFF, SP = ON, AGC = ON IVCC1ACircuit current 1A at non-signal (VCC) —dBV14.913.912.9 Vin = –6.0 dBV, f = 1 kHz, RL = 100 Ω, VCC_SP = 10 V, AGC – SELECT = [010] VSPOA1L VSPOA1RSP AGC output level —dBV–90–114—Vin = –26.0 dBV, f = 1 kHz, RL = 100 Ω, using A curve filter VSSPOL VSSPOROutput level at SP Save —dBV–68–75—Non-Signal using A curve filter VNSPOL VNSPORSP reference output noise voltage —dBV1.00.0–1.0Vin = –26.0 dBV, f = 1 kHz, RL = 100 Ω VSPOL VSPORSP reference output level —μA100.1—Non-signal, STB = OFF, SP = OFF, AGC = ONIVCC3CCircuit current 3C at non-signal (VCC_D) —mA1.00.5—Non-signal, STB = OFF, SP = OFF, AGC = ONIVCC1CCircuit current 1C at non-signal (VCC) —μA1.00.1—Non-signal, STB = ON, SP = OFF, AGC = ONIVCC3BCircuit current 3B at non-signal (VCC_D) —μA1.00.1—Non-signal, STB = ON, SP = OFF, AGC = ONIVCC1BCircuit current 1B at non-signal (VCC) —μA100.1—Non-signal, STB = OFF, SP = ON, AGC = ONIVCC3ACircuit current 3A at non-signal (VCC_D) —mA189.0—Non-signal, STB = OFF, SP = ON, AGC = ONIVCC2ACircuit current 2A at non-signal (VCC_SP) Circuit Current I/O Characteristics Limits Typ Unit Max Note Min ConditionsSymbolParameterB No. „ Electrical Characteristics at VCC = 3.0 V, VCC_D = 1.8 V, VCC_SP = 6.1 V Note) Ta = 25°C±2°C unless otherwise specified.

—V0.1 × VCC_D—— —VVCC_D + 0.5—0.7 × VCC_D —VsdlthShut-down input Low level —VIH SCL, SDA signal input High level —V——0.9 × VCC_D—VsdhthShut-down input High level —kHz400—0—fSCL Max. frequency of SCL signal allowable to input —μA10—–10Input voltage 0.1 V to 1.7 VIiSCL, SDA signal input current —V0.2 × VCC_D—0Open corrector, sync current: 3mAVOLSDA signal output Low Level —V0.3 × VCC_D—–0.5—VIL SCL, SDA signal input Low level I2C interface The threshold voltage at Pin B3 Limits Typ Unit Max Note Min ConditionsSymbolParameterB No. „ Electrical Characteristics at VCC = 3.0 V, VCC_D = 1.8 V, VCC_SP = 6.1 V (continued) Note) Ta = 25°C±2°C unless otherwise specified.

*1μs——0.6—tHighHigh period of SCL clock35 *1μs——1.3—tLowLow period of SCL clock 34 *1μs——0.6—tHD;STAHold time of start condition33 *1μs——0.6—tSU;STASetup time of start condition32 *1μs——1.3—tBUF Bus free time between stop and start conditions31 *1μs——0.6—tSU;STOSetup time of stop condition *1μs0.9—0—tHD;DATData hold time *1μs——0.1—tSU;DATData setup time *1μs0.3———tFFalling time of SDA, SCL signal *1μs0.3———tRRising time of SDA, SCL signal I2C interface Limits Typ Unit Max Note Min ConditionsSymbolParameterB No. „ Electrical Characteristics (Reference values for design) at VDD = VMSP = VMAC = VMST = VMBX = VMLO = 5 V， VREF = 1.65 V，STBY = 3.3 V Note) Ta = 25°C±2°C unless otherwise specified. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns. Note) *1: All values are VIHmin (*2) and VILmax (*3) level standard. *2: VIHmin is the minimum limit of the signal input high level. *3: VILmax is the maximum limit of the signal input low level. tBUF tSU;DAT tHD;DAT tSU;STOtSU;STAtHD;STA tRtF tLow tHigh START CONDITION SDA SCL tR tF tHD;STA STOP CONDITION Repeated START CONDITION START CONDITION VIHmin VILmax (*2) (*3)

„ Technical Data y I2C-bus mode 1.Write mode Two transmission messages (i.e. the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following description provides information on the structure of the frame. SDA SCL START CONDITION SLAVE ADDRESS ACK SUB ADDRESS ACK DATA ACK STOP CONDITION Example of transmission messages 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 01 8 0 1 0 0 0 0 0 0 0 <Start Conditions> When the level of the SDA changes to low from high while the level of the SCL is high, the data reception of the receiver will be enabled. <Stop Conditions> When the level of the SDA changes to high from low while the level of the SCL is high, the data reception of the receiver will be aborted. <Slave Address> The slave address is a specified one unique to each device. When the address of another device is sent, the reception will be aborted. <Sub-Address> The sub-address is a specified one unique to each function. <Data> Data is information under control. <Acknowledge Bit> The acknowledge bit is used to enable the master to acknowledge the reception of data for each octet. The master acknowledges the data reception of the receiver by transmitting a high-level signal to the receiver and receiving a low-level signal returned from the receiver as shown by the dotted lines in the above Fig. The communication will be aborted if the low signal is not returned. The SDA will not change when the level of the SCL is high except start or stop conditions are enabled.

„ Technical Data (continued) y I2C-bus mode (continued) 1.Write mode (continued) (a) I 2C-bus PROTOCOL x Slave address: 10110110 (B6Hex) x Format (Normal) (b) Auto increment x Sub-address 0*Hex: Auto increment mode (When the data is sent in sequence, the sub-address will change one by one and the data will be input.) x Auto increment mode (c) Initial condition The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0(Note.1) will be absolutely "0", when the power is turned ON. (d) Sub-address Byte and Data Byte Format (*1,*2) AGC-ATT data bit1 AGC-ATT data bit2 AGC-REC data bit1 AGC-REC data bit2 AGC-REC data bit3 AGC-ON data bit1 AGC-ON data bit2 AGC-ON data bit3*1Hex (*1,*2) (*1,*2) Standby 0 → ON 1 → OFF (*1) SP Save 0 → ON 1 → OFF (*1,*2) D1 D0 LSB (*1,*2) AGC 0 → OFF 1 → ON (*1,*2) (*1) (*1,*2) (*1) (*1) Data byte (*1,*2)*2Hex GAIN 0 → +20 dB 1 → +26 dB *0Hex MSBSub- address Note) *1: <00Hex Register> D0, D4, D5, D6: Always set to "0" 。 D1: Standby ON/OFF switch D2: D2: SP Save ON/OFF switch D3: AGC ON/OFF switch D7: GAIN +20 dB / +26 dB selection <01Hex Register> D0, D1: AGC-attack-time selection D2, D3, D4: AGC-recovery-time selection D5, D6, D7: AGC-on-level selection <02Hex Register> Always set to "0". (test & adjust mode). *2: Please use these bit only Data = "0", because they are used by our company’s final test and fine-tuning AGC-on level. Note that Data = "1" is not shut-down mode. PAData 1 A A Data n Data 2ASub-addressAWSlave addressS Start condition Stop condition Acknowledge bitWrite Mode: 0 PAData byteASub-addressAWSlave addressS

„ Technical Data (continued) y I2C-bus mode (continued) 1. Write Mode (continued) (e) AGC-attack-time selection (f) AGC-recovery-time selection 0.5 ms00 1m s10 Write 01Hex Register 4 ms11 2 ms01 Attack time D0D1 1.0 s000 4.0 s001 6.0 s101 2.0 s010 Write 01Hex Register 3.0 s10 Recovery time 1.5 s0 (g) AGC-on-level selection at VCC = 3.0 V, VCC_D = 1.8 V, VCC_SP = 6.1 V *1 8.5 V ≤12 V[p-p]12.6 dBV000

11.0 V ≤ *3

11.0 V ≤

10.5 V ≤

10.0 V ≤

9.5 V ≤

9.0 V ≤

VCC_SP (Reference) *2 16.6 dBV 16.1 dBV 15.6 dBV 15.1 dBV 14.5 dBV 13.9 dBV 13.2 dBV AGC On Level

19 V[p-p]

18 V[p-p]

17 V[p-p]

16 V[p-p]

15 V[p-p]

14 V[p-p]

13 V[p-p]

(V[p-p]) 001 101 010 011 Write 01Hex Register (h) Amp. gain selection at VCC = 3.0 V, VCC_D = 1.8 V, VCC_SP = 6.1 V 26 dB1 20 dB0 Gain Write 00Hex Register Note) *1: At the time of VCC_SP = 6.1 V, output is clipped, excessive clip in AGC OFF can be prevented. *2: The supply voltage of VCC_SP at which output is not clipped. *3: Output is clipped a little.

„ Technical Data (continued) y I2C-bus mode (continued) 2. Read Mode (a) I 2C-bus PROTOCOL x Slave address 10110111 (B7Hex) x Format Read Mode: 1 (b) Sub-address Byte and Data Byte Format Sub-address *1Hex Latch data D0 Sub-address *1Hex Latch data D1 Sub-address *1Hex Latch data D2 Sub-address *1Hex Latch data D3 Sub-address *1Hex Latch data D4 Sub-address *1Hex Latch data D5 Sub-address *1Hex Latch data D6 Sub-address *1Hex Latch data D7 Data 1 Sub-address *0Hex Latch data D0 Sub-address *0Hex Latch data D1 Sub-address *0Hex Latch data D2 Sub-address *0Hex Latch data D3 Sub-address *0Hex Latch data D4 Sub-address *0Hex Latch data D5 Sub-address *0Hex Latch data D6 Sub-address *0Hex Latch data D7 Data 0 Data byte Data 2 Sub-address *2Hex Latch data D1 Sub-address *2Hex Latch data D0 LSB Sub-address *2Hex Latch data D2 Sub-address *2Hex Latch data D3 Sub-address *2Hex Latch data D4 Sub-address *2Hex Latch data D5 Sub-address *2Hex Latch data D6 D6D7 Sub-address *2Hex Latch data D7 MSB Note) At the slave address input, it is sequentially output from Data 0. There is no necessity for inputting the sub-address. This IC is compatible with I2C-bus format. Purchase of Panasonic I2C Components conveys a license under the Philips I2C patent right to use these components in an I2C systems, provided that the system conforms to the I2C standard specifications as defined by Philips. PAData 1 A Data 2AData 0ARSlave addressS The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25°C) by inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control. But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to customer concerns. y Operating temperature guarantee of I2C-bus Control

„ Technical Data (continued) yI/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Input impedance = Hi-Z Input impedance = Hi-Z Input impedance = Hi-Z Impedance I2C-BUS SCL pin SCL Hi-Z I2C-BUS SDA pin SDA Hi-Z Power supply pin for I2C-BUS— VCC_D 1.8 V(typ.) Shut-down mode pin Please do not make it open, because the open S.D pin is not fixed. S.D Hi-ZB3 DescriptionInternal circuitWaveform and voltage Pin No. VCC_D (1.8 V) GND VCC_D (1.8 V) VCC_D (1.8 V)

„ Technical Data (continued) yI/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Output impedance = Equal to or less than 1 Ω Output impedance = Equal to or less than 1 Ω Impedance Ground pin for L-channel speaker output— GND_SPL DC 0 V L-channel negative speaker output pin LOUT_NEG DC 2.7 V Power supply pin for speaker output— VCC_SP 6.1 V(typ.) L-channel positive speaker output pin LOUT_POS DC 2.7 V DescriptionInternal circuitWaveform and voltage Pin No. 20k VCC_SP(6.1 V) GND_SPL 20k GND_SPL VCC_SP(6.1 V)

„ Technical Data (continued) yI/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Input impedance = About 150 kΩ Output impedance = Equal to or less than 1 Ω Output impedance = Equal to or less than 1 Ω Impedance GND pin for R-channel speaker output— GND_SPR DC 0 V R-channel positive speaker output pin ROUT_POS DC 2.7 V The reference voltage terminal for determining DC bias of the output stage of a speaker amplifier system. Please connect an external capacitor to remove a ripple. VREF_SP DC 2.7 V R-channel negative speaker output pin ROUT_NEG DC 2.7 V DescriptionInternal circuitWaveform and voltage Pin No. VCC_SP(6.1 V) 10k 300k 300k VCC_SP(6.1 V) 20k GND_SPR 20k VCC_SP(6.1 V) GND_SPR

„ Technical Data (continued) yI/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Output impedance = Equal to or less than 10 Ω Input impedance = About 75 kΩ Impedance Ground pin— GND DC 0 V Power supply pin— VCC 3.0 V(typ.) The reference voltage terminal for determining DC bias of the input stage of a speaker amplifier system. Please connect an external capacitor to remove a ripple. VREF DC 2.5 V Output terminal of R-channel input amplifier of speaker amplifier system. Please connect external resistance for the gain setting. PREOUT_R DC 2.5 V DescriptionInternal circuitWaveform and voltage Pin No. E3 150k 150k VREG (5 V) VREG (5 V)

„ Technical Data (continued) yI/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Input impedance = Hi-Z Output impedance = Equal to or less than 10 Ω Input impedance = Hi-Z Input impedance = Hi-Z Impedance Output terminal of L-channel input amplifier of speaker amplifier system. Please connect external resistance for the gain setting. PREOUT_L DC 2.5 V Feedback terminal of L-channel input amplifier of speaker amplifier system. The gain of the L-channel input amplifier can be set by connecting an external resistance between Pin C4 and Pin C5. FB_L DC 2.5 V Feedback terminal of R-channel input amplifier of speaker amplifier system. The gain of the R-channel input amplifier can be set by connecting an external resistance between Pin D4 and Pin D5. —N.C. Feedback terminal of R-channel input amplifier of speaker amplifier system. The gain of the R-channel input amplifier can be set by connecting an external resistance between Pin D4 and Pin D5. FB_R DC 2.5 V DescriptionInternal circuitWaveform and voltage Pin No. VREG (5 V) GND VREG (5 V) GND VREG (5 V)

„ Technical Data (continued) yPower supply and logic sequence Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop performance caused in switching. 1. The sequence of the power supply and each logic 2. The sequence of VCC and VCC_SP and VCC_D This IC does not have a rising and falling order in VCC, VCC_SP, and VCC_D. Rising and falling times of them are recommended 1 ms or more. VCC VCC_SP VCC_D Off On On Off 1 ms or more1 ms or more Note) *: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off. It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and resistance linked to an input terminal (IN_R and IN_L). It is a recommendation value in a constant given in the example of „Application Circuit Example (Block Diagram). Power supply Standby SP_Save 30 ms or more * VCC, VCC_SP, VCC_D, SD After at least 30 ms has passed after the standby off, please off SP_Save. Off On Off Off On On On On Off Off On Off The basic procedure at the power-on 0 ms or more Please get Standby On simultaneously with or after SP_Save On. The basic procedure at the power-off 1. The power OFF condition. Both the Standby and the SP_Save are in the ON condition. 2. Power ON 3. Standby OFF 4. SP_Save OFF 1. The power ON condition. Both the Standby and the SP_Save are in the OFF condition. 2. SP_Save ON (= Standby ON) 3. Standby ON 4. Power OFF Please turn on the power supply first, and then get Standby OFF.

„ Technical Data (continued) yExplanation on mainly functions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 1. Power supply 1) Power supply for output amplifier The output amplifier operates with voltage applied to VCC_SP. When power supply is applied to only VCC_SP in AN12959A, the product does not operate. (In case where voltage is not applied to VCC and VCC_D), it gets in Standby condition. 2) Power supply for control system The control system operates with power supply applied to VCC pin. (I2C logic, clock generation circuit, etc.) 3) Power supply for signal system The signal system operates with the internal regulator of 5 V. 5 V, reference voltage of the internal regulator is generated from VCC_SP using VCC power supply. By setting signal voltage at 5 V, the dynamic range of the signal can be secured sufficiently. When the gain of the input amplifier is 0 dB, clip occurs at the amplitude of 3 V[p-p] (typ.) in input signal. 4) Power supply for I2C interface I2C interface operates with power supply applied to VCC_D pin. I2C circuit operates with VCC. 5) High voltage at shut-down pin Please use the power supply applied to VCC_D or apply voltage from the outside. Threshold voltage depends on the voltage to VCC_D. AN12959A output maximum amplitude VCC_SP − 1.3 V(typ.)

„ Technical Data (continued) yExplanation on mainly functions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 2. Speaker amplifier 1) the gain for a input amplifier can be set with an external resistance. Input impedance is also set with the external resistance. When the gain for the input amplifier is set at ±0 dB, the total gain for the speaker amplifier is +26 dB or +20 dB (It can be selected with I2C). When the external resistance for the input amplifier is assumed as R1, R2, Gain = 20 log (R2 / R1) Zin = R1 In case of R1 = 10 kΩ, R2 = 10 kΩ with the constants in the above fig, the gain for the input amplifier is ±0 dB and impedance is 10 kΩ. During operation, keep the voltage of R1 and R2 at more than 5 kΩ. 2) With an external capacity added to the input amplifier, LPF, which removes an unwanted high frequency element, can be constructed. When external resistance is assumed as R2, capacity as C2, In case of R2 = 10 kΩ, C2 = 1500 pF with the constants in the above fig, Cut-off frequency, fc is 10.6 kHz. LOUT_NEG LOUT_POSAGC +14 dB +14 dB AGC DET INPUT_L 10 kΩ 10 kΩ 1500 pF 0 dB BTL: +6 dB +6 dB / 0 dB I2C Logic 0.1 μF

„ Technical Data (continued) yExplanation on mainly functions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 2. Speaker amplifier (continued) 3) With the smaller capacity of the input AC coupling capacitor, HPF, which removes unwanted low frequency element, can be constructed. When input resistance is assumed as R1, and AC coupling capacitor as C1, In case of R1 = 10 kΩ, C1 = 0.1 μF, cut-off frequency, fc is 160 Hz. In case of R1 = 10 kΩ, C1 = 0.022 μF, cut-of frequency, fc is 720 Hz. 0.1 μF 4) Bus Boost circuit can be constructed by adding capacity (RBB) and resistance (CBB) to the input amplifier. The frequency to increase 3 dB is assumed as fo 20 log ((Rf + RBB) / Rin)Ao = 20 log ((Rf + RBB) / Rf)Bus Boost Gain 1 / (2 ×π × Rf × CBB)fo = Cin Rf Cf RBB CBB Rin 3. Protection circuit for speaker amplifier 1) Thermal protection circuit The thermal protection circuit operates at the Tj of approximately 150°C. The thermal protection circuit is reset automatically when the temperature drops. 2) Output pin short protection circuit x Output pin-power supply line short protection x Output-to-output pin short protection x Output pin-GND line short protection If short-circuit is no longer detected, it will return automatically. Note) Operation is not guaranteed although the protection circuit is built in. Moreover, hundred percent inspection is not guaranteed.

„ Technical Data (continued) yExplanation on mainly functions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. 4. Cautions 1) Cautions about AGC Signal output in the input amplifier is detected and converted to forward current. Compared this forward current with reference voltage, if the forward current is larger, AGC turns ON. When the frequency band of the speaker is narrower than that of the amplifier. If maximum input is made in low frequency band, AGC operates to decrease volume. Namely, low sound part is not heard from a speaker, but AGC reacts to low sound part to turn down the volume. Please carefully design so that the frequency bands is synchronized between the speaker and amplifier. Note) Frequency characteristics should be set not only for the speaker, but in the built-in condition. The below Graph shows when the values of resistance and capacity are changed. Frequency characteristics ＡＮ １２９５９Ａ -15 -10 0.01 0.1 1 10 100 Input frequency (kHz) Output level （ｄBV) VccSP=9V Vin=-22dBV AGC OFF Cin=0.039uF Cf=1500pF Rin=10K RF=5.6K CBB=0.015uF RBB=10K Cin=0.1uF Cf=1500pF Rin=10K RF=10K CBB=0 RBB=0 2) Cautions about VCC_SP ON/OFF With VCC in AN12959A always on, when VCC_SP is turned ON/OFF, I2C data is retained. When VCC_SP is turned ON → OFF → ON without I2C control, pop sound comes out, as starting time for the amplifier gets significantly long. (Input amplifier, AGC circuit, and standard voltage are provided by VCC_SP). Note) Please never fail to turn ON Standby and SP_Save with I2C first, and then turn OFF VCC_SP. Next, turn ON VCC_SP, and turn OFF Standby and SP_Save to operate amplifier with I2C. If Standby is switched from ON to OFF with I2C, the amplifier starts within a short time, as a circuit runs to quickly charge an external condenser connected to Vref pin. (When VCC_SP is turned ON → OFF → ON without Standby control, the circuit of fast charge does not run.) Please space the time of 30 ms from turning Standby ON → OFF to SP_Save OFF. 3) Cautions about shut-down with SD pin During normal operation, when a shut-down pin is turned Low directly, shock noise comes out. As SP_Save is set in mute, first turn ON SP_Save, and then turn ON Standby to stop operation. Finally, set shut-down pin to Low.

„ Technical Data (continued) ySimulation of output current waveform Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. (There is twice as much difference as between current and voltage in a piezoelectric speaker per 1 channel.) A piezoelectric speaker of ceramic lamination type is used. Output current (Set at an absolute value.) Iout(max) = 580 mA Output current 10 kHz, 15 V[p-p] Output waveform 10 kHz, 15 V[p-p] Output current (Set at an absolute value.) If output waveform is clipped without resistance of more than 7.5 Ω× 2 at amplifier output, excessive current runs. Please never fail to insert resistance in use. Excessive current can cause intermittent output signal with load-short protection operated. Piezoelectric speaker 7.5 Ω to 10 Ω 7.5 Ω to 10 Ω Current Iout(max) = 710 mA Output current (Set at an absolute value.) Output waveform 10 kHz, 15 V[p-p] No resistance at output Iout(max) = 250 mA As resistance lies at output, the clip wave gets blunt in the capacity of resistance and speaker.

„ Technical Data (continued) y PD ⎯ Ta diagram

„ Usage Notes 1. Please carry out the thermal design with sufficient margin such that the power dissipation will not be exceeded, based on the conditions of power supply, load and surrounding temperature. Although indicated also in the column of the maximum rating, the maximum rating becomes an instant and the marginal value which must not exceed. It sufficiently evaluates, and I use-wish- do so that it may not exceed certainly. Moreover, don't impress neither voltage nor current to PIN which is not indicated. It may destroy in both cases. 2. Please pay attention to the pattern layout in order to prevent damage due to short circuit between pins. In addition, for the pin configuration, please refer to the „Pin Descriptions. 3. Please absolutely do not mount the LSI in the reverse direction on to the printed-circuit-board. It might be damaged when the electricity is turned on. 4. Please do a visual inspection on the printed-circuit-board before turning on the power supply, otherwise damage might happen due to problems such as a solder-bridge between the pins of the semiconductor device. Also perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5. Please take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such a s SP output pin (Pin A2, B1, D1, E2)-power supply pin short, SP output pin-GND short, or SP output-to-SP output-pin short (load short). 6. When using the LSI for model deployment or new products, perform fully the safety verification including the long-turn reliability for each product. 7. Please do not make it open, because the open SD pin (Pin B3) is not fixed.

Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: – Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod- ucts may directly jeopardize life or harm the human body. – Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or im- provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805