AM6012 PHILIPS
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Philips Semiconductors Linear Products Product specification AM601212-Bit multiplying D/A converter 776August 31, 1994 853-0904 13721
DESCRIPTION
The AM6012 12-bit multiplying Digital-to-Analog converter provides high-speed and 0.025% differential nonlinearity over its full commercial temperature range. The D/A converter uses a 3-bit segment generator for the MSBs in conjunction with a 9-bit R-2R diffused resistor ladder to provide 12-bit resolution without costly trimming processes. This technique guarantees a very uniform step size (up to ± LSB from the ideal), monotonicity to 12 bits and integral nonlinearity to 0.05% at its differential current outputs. The dual complementary outputs of the AM6012 increase its versatility, and effectively double the peak-to-peak output swing. Digital inputs, in addition, can be configured to accept all popular logic families. While the device requires a reference input of 1mA for a 4mA full-scale current, operation is nearly independent of power supply voltage shifts. The power supply rejection ratio is ±0.001% FS/% ΔV. The devices will work from +5, -12V to ±18V rails, with as low as 230mW power consumption typical.
FEATURES
- 12-bit resolution
- Accurate to within ±0.05%
- Monotonic over temperature
- Fast settling time, 250ns typical
- Trimless design for low cost
- Differential current outputs
- High-speed multiplying capability
- Full-scale current, 4mA (with 1mA reference)
- High output compliance voltage, -5 to +10V
- Low power consumption, 230mW PIN CONFIGURATION 10 11 D 1 and F Packages NOTE: 1. Available in large SO (SOL) package only. TOP VIEW D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 IO IO COMP VREF(–) VREF(+) GND/V LC D 12 LSB D 11
APPLICATIONS
- CRT displays, computer graphics
- Robotics and machine tools
- Automatic test equipment
- Programmable power supplies
- CAD/CAM systems
- Data acquisition and control systems
- Analog-to-digital converter systems
ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 20-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C AM6012F 0584B 20-Pin Plastic Small Outline Large (SOL) Package 0 to +70°C AM6012D 0172D
Philips Semiconductors Linear Products Product specification AM601212-Bit multiplying D/A converter August 31, 1994 777 BLOCK DIAGRAM COMP V(–) 16 17 VREF (+) VREF (–) BIAS NETWORK REFERENCE AMPLIFIER 9-SEGMENT GENERATOR DECODER CURRENT SWITCHES ISEG 9-BIT R-2R D/A CONVERTER LOGIC SWITCHES IO IO 12111098765432113 LSBGND/MSB V(+) VLC B12B11B10B9b8B7B6B5B4B3B2B1 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT TA Operating temperature AM6012F 0 to +70 °C TSTG Storage temperature range -65 to +150 °C TSOLD Lead soldering temperature 10sec max 300 °C VS Power supply voltage ±18 V Logic inputs -5V to +18 V Voltage across current outputs -8V to +12 V VREF Reference inputs V14, V15 V- to V+ VREF Reference input differential voltage (V14 to V15) ±18 V IREF Reference input current (I14) 1.25 mA PD Maximum power dissipation, TA=25°C, (still-air)1 F package 1560 mW D package 1390 mW NOTES: 1. Derate above 25°C, at the following rate: F package at 12.5mW/°C D package at 11.1mW/°C
Philips Semiconductors Linear Products Product specification AM601212-Bit multiplying D/A converter August 31, 1994 778 DC ELECTRICAL CHARACTERISTICS V+=+15V, V-=-15V, IREF =1.0mA, 0°C ≤/n636861723332000000000000TA ≤/n63686172333200000000000070°C SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT Resolution 12 Bits Monotonicity 12 Bits DNL Differential nonlinearity Deviation from ideal step size ±0.025 %FS
12 Bits
NL Nonlinearity Deviation from ideal straight line ±.05 %FS IFS Full-scale current VREF =10.000V R 14-R15=10.000kΩ TA=25°C 3.935 3.999 4.063 mA TCIFS Full-scale tempco ±10 ±40 ppm/°C VOC Output voltage compliance DNL Specification guaranteed over compliance range R OUT >10M Ω typ. -5 +10 V IFSS Symmetry IFS -IFS ±0.4 ±2.0 µA IZS Zero-scale current 0.10 µA VIL VIH Logic input levels Logic “0” 0.8 V Logic “1” 2.0 IIN Logic input current VIN=-5 to +18V 40 µA VIS Logic input swing V-=-15V -5 +18 V IREF Reference current range 0.2 1.0 1.1 mA I15 Reference bias current 0 -0.5 -2.0 µA dl/dt Reference input slew rate R 14(eq)=800Ω C C =0pF 4.0 8.0 mA/µs PSSIFS+ Power supply sensitivity V+=+13.5V to +16.5V , V-=-15V ±0.0005 ±0.001 %FS/% PSSIFS- V-=-13.5V to -16.5V, V+=+15V ±0.00025 ±0.001 V+ Power supply range VOUT =0V 4.5 18 V V- -18 -10.8 I- Power supply current -13.7 -18.0 mA I- -13.7 -18.0 PD Power dissipation V+=+5V, V-=-15V 234 312 mW AC ELECTRICAL CHARACTERISTICS V+=+15V, V-=-15V, IREF =1.0mA, 0°C ≤/n636861723332000000000000TA ≤/n63686172333200000000000070°C SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT tS Settling time To ± 1/2LSB, all bits ON or OFF , TA=25°C 250 500 ns tPLH tPHL Propagation delay—all bits 50% to 50% 25 50 ns C OUT Output capacitance 20 pF
Philips Semiconductors Linear Products Product specification AM601212-Bit multiplying D/A converter August 31, 1994 779 CIRCUIT DESCRIPTION The AM6012 is a 12-bit DAC which uses diffused resistors and requires no trimming to guarantee monotonicity over the temperature range. A segmented DAC design guarantees a more uniform step size over the temperature range than is normally available with trimmed 12-bit converters. The converter features differential high compliance current outputs, wide supply range, and a multiplying reference input. In many converter applications, uniform step size is more important than conformance to an ideal straight line. Many 12-bit converters are used for high resolution rather than high linearity, since few transducers are more linear than ±0.1%. All classic binarily weighted converters require ±1/2LSB (±0.012%) linearity in order to guarantee monotonicity, which requires very tight resistor matching and tracking. The AM6012 uses conventional bipolar processing to achieve high differential linearity and monotonicity without requiring correspondingly high linearity, or conformance to an ideal straight line. One design approach which provides monotonicity without requiring high linearity is the MOS switch-resistor string. This circuit is actually a full complement to a current-switched R-2R DAC since it is slower, has a voltage output, and, if implemented at the 12-bit level, would use 4096 low tolerance resistors rather than a minimum number of high tolerance resistors as in the R-2R network. Its lack of speed and density for 12 bits are its drawbacks. With the segmented DAC approach, the 4096 required output levels are composed of 8 groups of 512 steps each. Each step group is generated by a 9-bit DAC, and each of the segment slopes is determined by one of 8 equal current sources. The resistors which determine monotonicity are in the 9-bit DAC. The major carry of the 9-bit DAC is repeated in each of the 8 segments, and requires eight times lower initial resistor accuracy and tracking to maintain a given differential nonlinearity over temperature. The operation of the segmented DAC may be visualized by assuming an input code of all zeroes. The first segment current IO is divided into 512 levels by the 9-bit multiplying DAC and fed to the output, IOUT . As the input code increases, a new segment current is selected for each 512 counts. The previous segment is fed to output IOUT where the new step group is added to it, thus ensuring monotonicity independent of segment resistor values. All higher order segments feed IOUT . With the segmented DAC approach, the precision of the 8 main resistors determines linearity only. The influence of each of these resistors on linearity is four times lower than that of the MSB resistor in an R-2R DAC. Hence, assuming the same resistor tolerances for both, the linearity of the segmented approach would actually be higher than that of an R-2R design. The step generator or 9-bit DAC is composed of a master and a slave ladder. The slave ladder generates the four least significant bits from the remainder of the master ladder by active current splitting utilizing scaled emitters. This saves ladder resistors and greatly reduces the range of emitter scaling required in the 9-bit DAC. All current switches in the step generator are high-speed fully-differential switches which are capable of switching low currents at high speed. This allows the use of a binary scaled network all the way to the least significant bit which saves power and simplifies the circuitry. Diffused resistors have advantages over thin film resistors beyond simple economy and bipolar process compatibility. The resistors are fabricated in single crystal rather than amorphous material which gives them better long term stability and tracking and much higher moisture resistance. They are diffused at 1000°C and so are resistant to changes in value due to thermal and chemical causes. Also, no burn-in is required for stability. The contact resistance between aluminum and silicon is more predictable than between aluminum and an amorphous thin film, and no sandwich metals are required to enhance or protect the contact or limit alloying. The initial match between two diffused resistors is similar to that of thin film since both are defined by photomasks and chemical etching. Since the resistors are not trimmed or altered after fabrication, their tracking and long-term characteristics are not degraded. DIFFERENTIAL VS INTEGRAL NONLINEARITY Integral nonlinearity, for the purposes of the discussion, refers to the “straightness” of the line drawn through the individual response points of a data converter. Differential nonlinearity, on the other hand, refers to the deviation of the spacing of the adjacent points from a 1 LSB ideal spacing. Both may be expressed as either a percentage of full-scale output or as fractional LSBs or both. The graphs in Figure 1 define the manner in which these parameters are specified. The left graph shows a portion of the transfer curve of a DAC with 1/2LSB INL and the (implied) DNL spec of 1 LSB. Below this is a graphic representation of the way this would appear on a CR T screen where the AM6012 is used as a display driver. On the right is a portion of the transfer curve of a DAC specified for 1/2LSB INL with LSB DNL specified and the graphic display below it. One of the characteristics of an R-2R DAC in standard form is that any transition which causes a zero LSB change (i.e., the same output for two different codes) will exhibit the same output each time that transition occurs. The same holds true for transitions causing a 2 LSB change. These two problem transitions are allowable for the standard definition of monotonicity and also allow the device to be specified very tightly for INL. The major problem arising from this error type is in A/D converter implementations. Inputs producing the same output are now represented by ambiguous output codes for an identical input. Also, two LSB gaps can cause large errors at those input levels (assuming 1/2LSB quantizing levels). It can be seen from the two figures that the DNL-specified D/A converter will yield much finer grained data than the INL-specified part, thus improving the ability of the A/D to resolve changes in the analog input.
Figure 1. Differential Linearity Comparison insure turn-on of the internal bias network.
Philips Semiconductors Linear Products Product specification AM601212-Bit multiplying D/A converter August 31, 1994 781 testing and application. The logic switch design enables propagation delays of only 25ns for each of the 12 bits. Settling time to within LSB of the LSB is therefore 25ns, with each progressively larger bit taking successively longer. The MSB settles in 250ns, thus determining the overall settling time of 250ns. Settling to 10-bit accuracy requires about 90 to 130ns. The output capacitance of the AM6012 including the package is approximately 20pF; therefore, the output RC time constant dominates settling time if RL>500Ω . Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for IREF values down to 0.5mA, with gradual increases for lower IREF values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant. Measurement of settling time requires the ability to accurately resolve ±2µA, therefore a 2.5kΩ load is needed to provide adequate drive for most oscilloscopes. At IREF values of less than 0.5mA, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from 011111111111 to 100000000000 provides an accurate indicator of settling time. This code change does not require the normal 6.2 time constants to settle to within ±0.1% of the final value, and thus settling times may be observed at lower values of IREF . AM6012 switching transients or “glitches” are very low and may be further reduced by small capacitive loads at the output at a minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference, and VLC terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1µF capacitors at the supply pins provide full transient protection. APPLICATIONS INFORMATION Reference Amplifier Setup The AM6012 is a multiplying D/A converter in which the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly zero to +1.0mA. The full range output current is a linear function of the reference current and is given by: IFR 4095 4096 x 4 x (IREF ) 3.999 IREF where IREF = I14 In positive reference applications, an external positive reference voltage forces current through R14 into the VREF(+) terminal (Pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to VREF(-) at Pin 15. Reference current flows from ground through R14 into VREF(+) as in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at Pin 15. The voltage at Pin 14 is equal to and tracks the voltage at Pin 15 due to the high gain of the internal reference amplifier. R15 (nominally equal to R14) is used to cancel bias current errors (Figure 2a). Bipolar references may be accommodated by offsetting VREF or Pin 15. The negative common-mode range of the reference amplifier is given by: VCM- =V- plus (IREF ×3kΩ ) plus 1.8V. The positive common-mode range is V+ less 1.23V. When a DC reference is used, a reference bypass capacitor is recommended. A 5.0V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R14 should be split into two resistors with the junction bypassed to ground with a 0.1µF capacitor. For most applications, the tight relationship between IREF and IFS will eliminate the need for trimming IREF . If required, full-scale trimming may be accomplished by adjusting the value of R14, or by using a potentiometer for R14. MULTIPLYING OPERATION The AM6012 provides excellent multiplying performance with an extremely linear relationship between IFS and IREF over a range of 1mA to 1µA. Monotonic operation is maintained over a typical range of IREF from 100µA to 1.0mA. REFERENCE AMPLIFIER COMPENSATION FOR MULTIPLYING APPLICATIONS reference applications will require the reference amplifier to be compensated using a capacitor from pin 16 to V-. The value of this capacitor depends on the impedance presented to Pin 14. For R14 values of 1.0, 2.5 and 5.0kΩ , minimum values of CC are 5, 12 and 25pF. Larger values of R14 require proportionately increased values of CC for proper phase margin (see Figure 2b). For fastest response to a pulse, low values of R14 enabling small CC values should be used. If Pin 14 is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and slew rate. For R14=1kΩ and CC =5pF, the reference amplifier slews at 4mA/ms enabling a transition from IREF =0 to IREF =1mA in 250ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (IREF =0) condition. Full-scale transition (0 to 1mA) occurs in 62.5ns when the equivalent impedance at Pin 14 is 800Ω and CC =0. This yields a reference slew rate of 8mA/µs which is relatively independent of RIN and VIN values. LOGIC INPUTS The AM6012 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made possible by the large input swing capability, 40µA logic input current, and completely adjustable logic threshold voltage. For V-=-15V, the logic inputs may swing between -5 and +10V. This enables direct interface with +15V CMOS logic, even when the AM6012 is powered from a +5V supply. Minimum input logic swing and minimum logic threshold voltage are given by: V- plus (IREF ×3kΩ ) plus 1.8V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (Pin 13, VLC ). For TTL interface, simply ground Pin 13. When interfacing ECL, an IREF ≤1mA is recommended. For general setup of the logic control circuit, it should be noted that Pin 13 will sink 1.1mA typical. External circuitry should be designed to accommodate this current (Figure 3).
Philips Semiconductors Linear Products Product specification AM601212-Bit multiplying D/A converter August 31, 1994 782 FREQUENCY MHz Figure 2. REFERENCE CONFIGURATION R 14 R 15 R IN C C IREF Positive reference V R+ 0V N/C 0.01 µF V R+ /R14 Negative reference 0V V R– N/C 0.01 µF –V R– /R14 Lo impedance bipolar reference VR+ 0V V IN1 (VR+ /R14) + (VIN/RIN)2 Hi impedance bipolar reference V R+ VIN N/C1 (VR+ – RIN) / R143 Pulsed reference4 VR+ 0V V IN (VR+ /R14) + (VIN/RIN)No Cap NOTES: 1. The compensation capacitor is a function of the impedance seen at the +VREF input and must be at least 5pF x R14(eq) in kΩ . For R14 < 800Ω no capacitor is necessary. 2. For negative values of VIN, VR+ / R14 must be greater than –VIN max / RIN so that the amplifier is not turned off. 3. For positive values of VIN, VR+ must be greater than –VIN max so the amplifier is not turned off. 4. For pulsed operation, VR+ provides a DC offset and may be set to zero in some cases. The impedance at Pin 14 should be 800Ω or less. 5. For optimum settling time, decouple V– with 20Ω and bypass with 22µF tantalum capacitor. 6. Reference current and reference resistor — there is a 1-to-4 scale factor between the reference current (IREF ) and the full-scale output current (IFS). If VREF = +10V and IFS = 4mA, the value of the R14 is: R 14 4 x 10V 4mA 10k R 14 R 15 a. Reference Amplifier Biasing Reference Amplifier Frequency Response Minimum Size Compensation Capacitor (IFS = 4mA, IREF = 1.0mA) R 14(EQ) (kΩ ) C C (pF) NOTE: A 0.01µF capacitor is recommended for fixed reference operation. REFERENCE AMPLIFIER AM6012 FOR ALL INPUT CODES COMP 0.1 20 (NOTE 5) IO + IO = IFS IO IO V– V+ V– I15 IREFVIN R IN R 14 R 15 VR+ VR– 22µF TANTALUM R 15 = R14 = RIN VIN C C 0.1 .01 0.1 1.0 10 RELATIVE OUTPUT , dB LARGE SIGNAL = 50% MODULATION OF 4mA FULL SCALE CURRENT SMALL SIGNAL = 1% MODULATION OF 2mA FULL SCALE CURRENT R 14 (EQ) = 2kΩ C C = 10pF
Figure 3. Interfacing Circuits for ECL, CMOS, HTL Logic Inputs
- Set the voltage ‘A’ to the desired logic input switching threshold.
- Allowable range of logic threshold is typically –5V to +13.5V when operating the DAC on ±15V supplies.
VREF(+) Must be above peak positive swing of VIN. IREF > Peak negative swing of IIN. R REF sets IFS ; R15 is for a bias current cancellation.
Figure 4. AM6012 Logic Inputs
- Any of the offset binary codes may be complemented by
reversing the output terminal pair.
Figure 5. CRT Display Driver
- Full differential drive lowers power supply voltage.
- Eliminates inverting amplifiers and transformers.
- Independent beam centering controls.
Figure 6. 12-Bit High-Speed A/D Converter
2504 SAR
Philips Semiconductors Linear Products Product specification AM601212-Bit multiplying D/A converter August 31, 1994 786 APPLICATION CIRCUITS Figure 7. NOTE: Data remains on inputs of DAC until updated by E2 pulse. Timing will depend on processor used. D 3A D 2A D 1A D 0A Q 3A Q 2A Q 1A Q 0A BUS LS373 6012 LSB MSB 1/2LS100 µP EA 1/2LS100 D 3B D 2B D 1B D 0B Q 3B Q 2B Q 1B Q 0B EB OE a. Interface With 8-Bit Microprocessor Bus a. Timing Sequence ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ DB0–3 DB4–11