AM2940 ETC
Document overview
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Technical content
: Am2940 DMA Address Generator DISTINCTIVE CHARACTERISTICS ‘© DMA Address Generation © Programmable Control Modes Generates memory address, word count and DONE Provides four types of DMA transfer control plus signal for DMA transfer operation. memory address increment/decrement. ‘© Expandable Eight-bit Slice © High Speed, Bipolar LS! Any number of Am2940's. can be cascaded to form ‘Advanced Low-Power Schottky TTL technology pro- larger memory addresses - three devices address 16 vides typical CLOCK to DONE propagation delay of megawords. 50ns and 24mA output current sink capably. ‘© Repeat Data Transfer Capability © Microprogrammable Initial memory address and word count are saved Executes 8 different instructions. so that the data transfer can be repeated. GENERAL DESCRIPTION The Am2940, a 28:pin member of Advanced Micro De- for use in peripheral controllers with OMA capability or in vices’ Am2900 family of Low-Power Schottky bipolar LS|__any other system which transfers data to or from sequential chips, is a high-speed, cascadable, eight-bit wide Direct locations of a memory. Memory Access Address Generator slice. Any number of ‘Am2940's can be cascaded to form larger addresses. The Am2940 can be programmed to increment or decre- A ment the memory address in any of four control modes, and The primary function of the device is to generate sequential 6 ecxtes eight different instructions. The initial address and memory addresses for use in the sequential transfer of data count oe ahaa ielerrtpnehaait from a memory. it also maintains a data word count W0'd count are saved internally by ‘so that they {0 or can be restored later in order to repeat the data transfer ‘and generates a DONE signal when a programmable oo Cration, terminal count has been reached. The device is designed 7 BLOCK DIAGRAM zs. mages i ———" sermon 6 > keene mtv ninua Gee OF CLOCK ‘Am2940 DMA Address Generator BDo02450 For applications information see the last part of this data sheet and Chapter Vil of Bit Slice Microprocessor Design, by Mick and Brick, McGraw-Hill Publishers. 035758 5-268 Fofer to Pago 131 for Essent! Inlnaton on Mitary Devices
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ORDERING INFORMATION
AMD products are available in several packages and operating ranges. The order number is formed by a combination of the following: Device number, speed option (if applicable), package type, operating range and screening option (if destred) Am2940 dD oc B Valid Combinations ‘Screening Option DC, DCB, DMB Blank - Standard processing FMB B - Burnin Am2940 Lc, LMB Temperature (See Operating Range) XC, XM © -Commercial (0°C to +70°C) M —Military (55°C to + 125°C) Package D-26-pin CERDIP F-28-pin flatpak L-28-pin leadless chip carrier X- Dice Valid Combinations Consult the AMD sales office in your area to Device type determine it a device is currently available in the DMA Address Generator combination you wish. Gap Pak a a Wadaran ot Aovarcod MES Dewees, Ke 035758 5-269 Refer to Page 13-1 for Essential information on Miltary Devices:
< [Pin No. [name [v0 [Description [2a 24. 25 [log [1 [Selects one of eight instrctions, [1 fact Tt [Gary.in to the accross counter, [eo [ato | [Carryout trom the aadress counter, 0 po [wer [1 [Garvin to the word counter, [10 wee [Gary trom the word counter, [Bor [v0 external dat [| tao? [© Adéress outputs under control of Output Enable input, Eq, [20 OE, Tt Adress output enable, [7 [oone | o[Transter complete signal [21 Tor | [clock input, Registers and counters chenge on the LOW-to-HIGH transition. | Am2940 ARCHITECTURE Word Counter and Word Count Register As shown in the Block Diagram, the Am2940 consists of the ‘The Word Counter and Word Count Register, which maintain following and save a word count, are similar in structure and operation © A three-bit Control Register to the Address Counter and Address Register, with the © An eight-bit Address Counter with input multiplexer ‘exception that the Word Counter increments in Control Modes © An eight-bit Address Register 1 and 3, decrements in Control Mode 0, and is disabled in © An eight-bit Word Counter with input multiplexer Control Mode 2. The LOAD WORD COUNT instruction simul- © An eight-bit Word Count Register taneously loads the Word Counter and Word Count Register. © Transfer complete circuitry © An eight-bit wide data multiplexer with three-state output. ‘Transfer Complete Circuitry butters The Transfer Complete Circuitry is a combinational logic © Three-state address output buffers with external output network which detects the completion of the data transfer ‘enable control . ‘operation in three Control Modes and generates the DONE © An instruction decoder ‘output signal. The DONE signal is an open-collector output, which can be dot-anded between chi Control Register ones. Under instruction control, tho Control Register can be loaded Data Multiplexer or read from the bidirectional DATA lines Do-D7. Contro| The Data Multiplexer is an eight-bit wide, 3-input multiplexer Register bits 0 and 1 determine the Am2940 Control Mode, _ which allows thie Address Counter, Word Counter, and Control and bit 2 determines whether the Address Counter increments Register to be read at the DATA lines, Do-D7. The Data or decrements. Figure 1 defines the Control Register format. Multiplexer and three-state Data Output Buffers are instruction controlled. Address Counter Add Output Butt ress ju fers. The Address Counter, which provides the current memory P address, is an eight-bit, binary, up/down counter with full look- The three-state Address Output Buffers allow the Address ahead carry generation. The Address Carry Input (ACI) and Counter output to be enabled onto the ADDRESS lines, Ag-A7, Address Carry Output (ACO) allow cascading to accommo- under external control. When the Output Enable input, OE A, is date larger addresses. Under instruction control, the Address. LOW, the Address output butfers are enabled; when OE, is Counter can be enabled, disabled, and loaded from the DATA HIGH, the ADDRESS lines are in the high-impedance state. inputs, Dp-D7, or the Address Register. When enabled and the ‘The Address and Data Output Buffers can sink 24mA output KCI input is LOW, the Address Counter increments/decre- ‘current over the commercial operating range. ments on the LOW-to-HIGH transition of the CLOCK input, CP. The Address Counter output can be enabled onto the three. ‘Instruction Decoder state ADDRESS outputs Ao-A7 under control of the Output The Instruction Decoder generates required internal contro! Enable input, CEA. signals as a function of the INSTRUCTION inputs, lo-le and Control ster bits, CRo-CRy. Address Register Regs oe ‘The eight-bit Address Register saves the initial address so that Clock it can be restored later in order to repeat a transfer operation. The CLOCK input, CP is used to clock the Address Register, When the LOAD ADDRESS instruction is executed, the Address Counter, Word Count Register, Word Counter, and Address Register and Address Counter are simultaneously Control Register, all on the LOW-to-HIGH transition of the CP loaded from the DATA inputs, Dp-D7. signal, 095758 5-270 Refer to Page 13-1 tor Essential Information on Miltary Devices:
= Word Count Reg. = Word Count Reg. Figure 1. Control Register Format Definition. 5 Control Mode 0 - Word Count Equals Zero and serves as a holding register for the final memory address. Carry-in, WCi, is LOW, the Word Counter decrements on the Circuitry compares the Address Counter with the Word Count. Address Register and Address Counter and the final memory LOW.
Figure 2. Am2940 Interconnections. and Word Counters. The function of the REINITIALIZE Address Register and Address Counter. “don't care" inputs for this instruction. The READ CONTROL applied, counting can be controlled by the carry inputs. and Word Counter. In Control Mode 1, DATA inputs Do-D7 are address and word count from the DATA lines.
TABLE |. Am2940 INSTRUCTIONS H Ps Octal Control Address Controi | Data | & Code Mode Reg. Register | Do-D7 ware bu CONTR 02-.CR! REGISTER Pore READ cou CONTAOL rocr | 0129 | HOLD JOR Doe REGISTER (Note 1) READ LHL WORD. 0123 | How | How | HOLD wo..0 COUNTER READ, LoHoH ADDRESS ROAC 0123 HOLD ac-D COUNTER REINTIALZE [ozs | wove [won-we| How | AR-ac [ wow | 2 | Hou COUNTERS [1] woLo” Jzeno—we| Howe | AR=Ac [How | 2 | Pepe | ais foe [was [vo [me [ove [ove [ roo | om | Pe [ome Ee renee nao of oer | WORD Lowe [em fe COUNT [1 [e-waJzeno—wel “ro [pow | Hou | near | [as | woo |S [vow [ERE | woo |e] ; ENABLE ‘COUNT ‘COUNT COUNTERS: [2 | WOLD | ENABLE | HOLO COUNT CR = Control Rog. WER = Word Count Reg. L= Low AR = Address Reg. WC = Word Counter H=HIGH AG= Address Counter = Data 2 = High Impedance Note 1: Data Bits O3-D7 are high during this instruction. APPLICATIONS ‘The Am2940 interconnections are shown in detail in Figure 2. Two Am2940's are cascaded to generate a sixteen-bit ad- ‘The Am2940 is designed for use in peripheral controllers with dress, The Am2940 ADDRESS and DATA output current sink DMA capabilty or in any othor system which transfers data to capability is 24mA over the commercial operating range. This or from sequential locations ‘of a memory. One or more allows the Am2940's to drive the System Address Bus and ‘Am2940's can be used in each peripheral controller of @ internal Three-State Bus directly, thereby eliminating the need distributed DMA system to provide the memory address and for separate bus drivers, Three-bits in the Microinstruction word count required for DMA operation. Register provide the Am2940 Instruction Inputs, Io-l2. The Figure 3 shows a block diagram of an example micropro- microprogram clock is used to clock the Am2940's and, when ‘grammed DMA peripheral controller. The Am2910A Micropro- the ENABLE COUNTERS instruction is applied, address and gram Sequencer, Microprogram Memory, and the Microin- word counting is controlled by the CNT bit of the Microinstruc- Suction Register form the microprogram control portion of ton Register. ‘this peripheral controller, The Am2940 generates the memory wyoreee and maintaing the word count required for DMA Asynchronous interface control circuitry generates System operation. An internal three-state bus provides the communi- Bus control signals and enables the Am2940 Address onto the cation path between the Microinstruction Register, the ‘System Address Bus at the appropriate time, The open- ‘Am2917 Data Transceivers, the Am2940, the Am2901C_ collector DONE outputs are dot-anded and used as a test Microprocessor, and the Device Interface Circuitry. input to the Am2910A Microprogram ‘Sequencer. 035758
5.273 Foter to Page 191 fr Essential information on sary Devos
& 1 / | : peanion Aes ~ a euon Ly Meantin } micro. | cowrnot’ | 0002221 Figure 3, DMA Peripheral Controller Block Diagram. 035758
5.274 Rete to Page 10-1 for Essential Ilormaton on Mary Devons
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES 2 Storage Temperature 4-2. sess. 65°C to + 150°C Commercial (C) Devices F3 DE Voltage Applied to Outputs For Maltery (M) Devices o POPALUTO oe eee eseeeesesreeeersnes 55°C tO + 126°C DG Output Current, Into OUpUts onsen 9OMA Shy of the. device guaranteed. wn DC Input Current . seeeees secccsere 3OMA to +5.0MA Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute ‘maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating range unless otherwise specified Typ Test Conditions (Note 2) (Note 1) ee ee put LOW Vol ire von OL Witt Ot MT opy Lil fous Tema . DONE: [unr Tank HIGH Lover (owe «) | Gosrartond est Logical HIGH votage or at wewts [20 [|| Vols | [un [input LOW Level (Note 4) | Guarantoed Input Logical LOW votage for af inputs [08] vons | [aT rmout Glamp Vonage | Voc=MIN we-tema T= 8 Vai | ee ee el a a oo" MAK Vin = BV [ar Ones [| fe | A [iocx [Output Leakage on GONE [Veo=waxvo=ssv aso a [i Tinpur GH Curent =i Voc= MAK Vesey Tt Tm | ‘Output Shor Circuit Current : : ke Cc ———— Ouput OFF Coment Voc = MAX 90.7 ae OE-24v ee i Wour= 24 ee a ee [aztroro Ts Power Supply Curent voc = MAX [tow-secw rere [Tas | [ica sia Ts) Noles 1 Typical Imis are @ Vag = 50V, 25°C ambient and maximum loading eel tons shown So MIN cr MAX, uso the appropriate valve spociied under Operating Ranges for the applicable device type. 3 Net move tran ‘one ouiput should be shorted ata time. Duration of the short ofcull test should not excoed one second. Teese input levels provde no guaranteed noise immunity and should only be static tested in a noise-froe onvironment (not functionally tested). . 5, Unstone (ste to 7) apples to ether output indviduay, but rot Both atthe same time, The sum ofthe loading on A plus 0, is limited to 2émA MIL or 32mA COM. : 095758
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& A. THREE-STATE OUTPUTS B, NORMAL OUTPUTS C. OPEN-COLLECTOR OUTPUTS i . & Veo Yeo ss ™ Ss a . 3" Vour O00 Your 00" Your O—0~ % | i | cn i ( To001081 0001220 0001100 lon py = 5O2Vee=Vou y= SO=Voe= Vou y= S220 tor + Vou for + Vou loo 1K Re Notes: 1. C_ = 50pF includes scope probe, stray wiring and capacitances without device in test fixture. 2. Sy, Sz, Sg are closed during function tests and all AC tests except output enable tests. 3. S; and S3 are closed while Sz is open for tpzy test. S1 and S2 are closed while Sg is open for tpz, test. 4. CL= 5.0pF for output disable tests. TEST OUTPUT LOADS FOR Am2940 (DIP) Test Circuit [= | aor | Atk [= | oor eo [oe | aco oak [7 [ cone TTT [io [ woo soak For additonal information on testing, see section “Guidelines on Testing Am2900 Family Devices.” z 095758 . 5276 otro Pope 19: fo Esser nlason on Matary Dewees
SWITCHING CHARACTERISTICS 2 The tables below define the Am2940 switching characteristics. Tables A are set-up and hold times relative to the clock LOW-to- F3 HIGH transition. Tables B are combinational delays. Tables C are clock requirements. All measurements are made at 1 5V with input levels at OV or 3V. All values are inns with C= 50pF except output disable times (GE to A and I to D) which are specified or a SpF load. 1, GUARANTEED CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE ‘Am2940DC (Ta =0 to +70°C, Voc = 4.76 to 5.25V, Cy = 5OpF) A. Set-up and Hold Times B. Combinational Delays (Relative to clock LoW-to HIGH transition) [revit | REG | WOO | An? | DONE | Dor | Cee oe] pea tea,-|-|-|[- | wo [oe | we fs [oe | -|-[-[- |) rar | als | cP Fe pete] Gee Lele t+TeT C. Clock Requirements D. Enable/Disbable Times [wnmim Gok rowtme [= [m=] [Fom| To | Diabe [cra [| | wioinun Gock HIGH Tine | [re | |e | or | o% | 8 [rs | [cmaxmim Goek Frewency [7 [wie] [OE | Aor | 2s | a | os | Il. GUARANTEED CHARACTERISTICS OVER MILITARY OPERATING RANGE ‘Am2940DM, FM (Tc =-55 to + 125°C, Voc = 4.5 to 5.5V, Cl. = SOpF) A. Set-up and Hold Times B. Combinational Delays (Relative to clock LOW :to-HIGH transition) [tees | R60 [ WES | har | DONE | 57 | eee] Pepa wo (Note 3) (Note 1) C. Clock Requirements: D. Enable/Disable Times (wan GoxtowTme [ [=] [Fom| te | Diabie | enabe [| | Cwnimum cock HIGH Tine [25 [ms | | toe | oo | 2 | a [os | [maximum Clock Frewency [16 [mme| [OE | Aor | a | 90 | vs | ‘Notes: 1. Control modes 0, 1, and 3 only. 2. Wi to DONE occurs only in control modes 0 and 1 3. CP to DONE occurs only in control modes 0, 1, and 2. 035758 son pt Pg 191 et rer ota ree
Figure 4. Switching Waveforms. ‘See Tables A for ts and th for various inputs. See Tables B for combinational delays from clock and other inputs to outputs.
- Insure the part is adequately decoupled at the test head. ‘of Vjj4 until the noise has settled. AMD recommends using
Large changes in Vco current when the dovice switches Vi_ SOV and Vi >3.0V for AC tests. start to oscillate at high frequency. of tests. as much as 400mA in 5-8ns. inductance in the ground cable Fairchild Sentry programs, under license.