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/C0065/C0077/C0050/C0054/C0076/C0083/C0051/C0048 SEMICONDUCTOR TECHNICAL DATA DUAL DIFFERENTIAL/ QUAD SINGLE–ENDED LINE DRIVERS
ORDERING INFORMATION
MC26LS30D T A = – 40° to +85°C Plastic DIP SO–16 PIN CONNECTIONS Order this document by AM26LS30/D PC SUFFIX PLASTIC PACKAGE CASE 648 D SUFFIX PLASTIC PACKAGE CASE 751B (SO–16) FN SUFFIX PLASTIC PACKAGE CASE 775 AM26LS30FN PLCC–20 In B/En AB Mode NC Gnd In C/En CD Out B SR–B NC SR–C Out C Input A VCC NC SR–A Out A In D NC SR–D Out D VEE 3 2 1 20 19 9 10 11 12 13 161 8 9 Input C/ Enable CD (Top View) SR–A Output A Output B Input D VEE SR–D Output D Output C SR–C SR–B Gnd VCC Input A Mode Input B/ Enable AB 1MOTOROLA ANALOG IC DEVICE DATA /C0065/C0100/C0118/C0097/C0110/C0099/C0101 /C0073/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0068/C0117/C0097/C0108 /C0068/C0105/C0102/C0102/C0101/C0114/C0101/C0110/C0116/C0105/C0097/C0108 /C0040/C0069/C0073/C0065/C0045/C0052/C0050/C0050/C0045/C0065/C0041/C0047 /C0081/C0117/C0097/C0100 /C0083/C0105/C0110/C0103/C0108/C0101/C0045/C0069/C0110/C0100/C0101/C0100 /C0040/C0069/C0073/C0065/C0045/C0052/C0050/C0051/C0045/C0065/C0041 /C0076/C0105/C0110/C0101 /C0068/C0114/C0105/C0118/C0101/C0114/C0115 The AM26LS30 is a low power Schottky set of line drivers which can be configured as two differential drivers which comply with EIA–422–A standards, or as four single–ended drivers which comply with EIA–423–A standards. A mode select pin and appropriate choice of power supplies determine the mode. Each driver can source and sink currents in excess of 50 mA. In the differential mode (EIA–422–A), the drivers can be used up to 10 Mbaud. A disable pin for each driver permits setting the outputs into a high impedance mode within a ±10 V common mode range. In the single–ended mode (EIA–423–A), each driver has a slew rate control pin which permits setting the slew rate of the output signal so as to comply with EIA–423–A and FCC requirements and to reduce crosstalk. When operated from symmetrical supplies (±5.0 V), the outputs exhibit zero imbalance. The AM26LS30 is available in a 16–pin plastic DIP and surface mount package. Operating temperature range is –40° to +85°C.
- Operates as Two Differential EIA–422–A Drivers, or Four Single–Ended EIA–423–A Drivers
- High Impedance Outputs in Differential Mode
- Short Circuit Current Limit In Both Source and Sink Modes
- ±/n63686172000000000000000010 V Common Mode Range on High Impedance Outputs
- ±/n63686172000000000000000015 V Range on Inputs
- Low Current PNP Inputs Compatible with TTL, CMOS, and MOS Outputs
- Individual Output Slew Rate Control in Single–Ended Mode
- Replacement for the AMD AM25LS30 and National Semiconductor DS3691 Representative Block Diagrams Single–Ended Mode EIA–423–A Differential Mode EIA–422–A Enable CD Enable AB Out D Out C Out B Out A VCC – 1 VEE – 8 Input D Input A Input A SR–A Out A Gnd – 5 Mode – 4 SR–B SR–C Out D SR–D Out C Out BInput B Input C Input D Motorola, Inc. 1995This document contains information on a new product. Specifications and information herein are subject to change without notice.
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MAXIMUM OPERATING CONDITIONS (Pin numbers refer to DIP and SO–16 packages only.) Rating Symbol Value Unit Power Supply Voltage VCC VEE –0.5, +7.0 –7.0, +0.5 Vdc Input Voltage (All Inputs) Vin –0.5, +20 Vdc Applied Output Voltage when in High Impedance Mode (VCC = 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1) Vza ±15 Vdc Output Voltage with VCC , VEE = 0 V Vzb ±15 Output Current IO Self limiting – Junction Temperature TJ –65, +150 °C Devices should not be operated at these limits. The “Recommended Operating Conditions” table provides conditions for actual device operation. RECOMMENDED OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Power Supply Voltage (Differential Mode) VCC VEE +4.75 –0.5 5.0 +5.25 +0.3 Vdc Power Supply Voltage (Single–Ended Mode) VCC VEE +4.75 –5.25 +5.0 –5.0 +5.25 –4.75 Input Voltage (All Inputs) Vin 0 – +15 Vdc Applied Output Voltage (when in High Impedance Mode) Vza –10 – +10 Applied Output Voltage, VCC = 0 Vzb –10 – +10 Output Current IO –65 – +65 mA Operating Ambient T emperature (See text) TA –40 – +85 °C All limits are not necessarily functional concurrently. ELECTRICAL CHARACTERISTICS (EIA–422–A differential mode, Pin 4 /C0112 0.8 V, –40°C /C0116TA /C011685°C, 4.75 V /C0112 VCC /C0112 5.25 V, VEE = Gnd, unless otherwise noted. Pin numbers refer to DIP and SO–16 packages only.) Characteristic Symbol Min Typ Max Unit Output Voltage (see Figure 1) Differential, RL = ∞ , VCC = 5.25 V Differential, RL = 100 Ω , VCC = 4.75 V Change in Differential Voltage, RL = 100 Ω (Note 4) Offset Voltage, RL = 100 Ω Change in Offset Voltage*, RL = 100 Ω VOD1 VOD2 ΔVOD2 VOS ΔVOS 2.0 4.2 2.6 2.5 6.0 400 3.0 400 Vdc Vdc mVdc Vdc mVdc Output Current (each output) Power Off Leakage, VCC = 0, –10 V /C0112 VO /C0112 +10 V High Impedance Mode, VCC = 5.25 V, –10 V /C0112 VO /C0112 +10 V Short Circuit Current (Note 2) High Output Shorted to Pin 5 (TA = 25°C) High Output Shorted to Pin 5 (–40°C /C0116 TA /C0116+85°C) Low Output Shorted to +6.0 V (TA = 25°C) Low Output Shorted to +6.0 V (–40°C /C0116 TA /C0116 +85°C) IOLK IOZ ISC– ISC– ISC+ ISC+ –100 –100 –150 –150 –95 +100 +100 –60 –50 150 150 µA mA Inputs Low Level Voltage High Level Voltage Current @ Vin = 2.4 V Current @ Vin = 15 V Current @ Vin = 0.4 V Current, 0 /C0112 Vin /C0112 15 V, VCC = 0 Clamp Voltage (Iin = –12 mA) VIL VIH IIH IIHH IIL IIX VIK 2.0 –200 –1.5 –8.0 0.8 100 Vdc Vdc µA Vdc Power Supply Current (VCC = +5.25 V, Outputs Open) (0 /C0112 Enable /C0112 VCC ) ICC – 16 30 mA NOTES: 1. All voltages measured with respect to Pin 5. 2.Only one output shorted at a time, for not more than 1 second. 3. Typical values established at +25°C, VCC = +5.0 V, VEE = –5.0 V. 4. Vin switched from 0.8 to 2.0 V. 5. Imbalance is the difference between VO2 with Vin /C0116 0.8 V and VO2 with Vin /C0117 2.0 V.
3MOTOROLA ANALOG IC DEVICE DATA TIMING CHARACTERISTICS (EIA–422–A differential mode, Pin 4 /C0112 0.8 V, TA = 25°C, VCC = 5.0 V, VEE = Gnd, (Notes 1 and 3) unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Differential Output Rise Time (Figure 3) tr – 70 200 ns Differential Output Fall Time (Figure 3) tf – 70 200 ns Propagation Delay Time – Input to Differential Output Input Low to High (Figure 3) Input High to Low (Figure 3) tPDH tPDL 200 200 ns Skew Timing (Figure 3) tPDH to tPDL /n636861720000000000000000for Each Driver Max to Min tPDH Within a Package Max to Min tPDL Within a Package tSK1 tSK2 tSK3 9.0 2.0 2.0 ns Enable Timing (Figure 4) Enable to Active High Differential Output Enable to Active Low Differential Output Enable to 3–State Output From Active High Enable to 3–State Output From Active Low tPZH tPZL tPHZ tPLZ 150 190 110 300 350 350 300 ns ELECTRICAL CHARACTERISTICS (EIA–423–A single–ended mode, Pin 4 /C0113 2.0 V, –40°C /C0116 TA /C0116 85°C, 4.75 V /C0112 VCC , |VEE /C0112 5.25 V, (Notes 1 and 3) unless otherwise noted). Characteristic Symbol Min Typ Max Unit Output Voltage (VCC = VEE = 4.75 V) Single–Ended Voltage, RL = ∞ (Figure 2) Single–Ended Voltage, RL = 450 Ω , (Figure 2) Voltage Imbalance (Note 5), RL = 450 Ω VO1 VO2 ΔVO2 4.0 3.6 4.2 3.95 0.05 6.0 6.0 0.4 Vdc Slew Control Current (Pins 16, 13, 12, 9) ISLEW – ±120 – µA Output Current (Each Output) Power Off Leakage, VCC = VEE = 0, –6.0 V /C0112 VO /C0112 +6.0 V Short Circuit Current (Output Short to Ground, Note 2) Vin /C0112 0.8 V (TA = 25°C) Vin /C0112 0.8 V (–40°C /C0116 TA /C0116 +85°C) Vin /C0119 2.0 V (TA = 25°C) Vin /C0119 2.0 V (–40°C /C0116 TA /C0116 +85°C) IOLK ISC+ ISC+ ISC– ISC– –100 –150 –150 –95 +100 150 150 –60 –50 µA mA Inputs Low Level Voltage High Level Voltage Current @ Vin = 2.4 V Current @ Vin = 15 V Current @ Vin = 0.4 V Current, 0 /C0112 Vin /C0112 15 V, VCC = 0 Clamp Voltage (Iin = –12 mA) VIL VIH IIH IIHH IIL IIX VIK 2.0 –200 –1.5 –8.0 0.8 100 Vdc Vdc µA Vdc Power Supply Current (Outputs Open) VCC = +5.25 V, VEE = –5.25 V, Vin = 0.4 V ICC IEE –22 –8.0 mA TIMING CHARACTERISTICS (EIA–423–A single–ended mode, Pin 4 /C0113 2.0 V, TA = 25°C, VCC = 5.0 V, VEE = –5.0 V, (Notes 1 and 3) unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Output Timing (Figure 5) Output Rise Time, CC = 0 Output Fall Time, CC = 0 Output Rise Time, CC = 50 pF Output Fall Time, CC = 50 pF tr tf tr tf 3.0 3.0 300 300 ns µs Rise Time Coefficient (Figure 16) C rt – 0.06 – µs/pF Propagation Delay Time, Input to Single Ended Output (Figure 5) Input Low to High, CC = 0 Input High to Low, CC = 0 tPDH tPDL 100 100 300 300 ns Skew Timing, CC = 0 (Figure 5) tPDH to tPDL for Each Driver Max to Min tPDH Within a Package Max to Min tPDL Within a Package tSK4 tSK5 tSK6 2.0 5.0 ns
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Figure 1. Differential Output Test Figure 2. Single–Ended Output Test Figure 3. Differential Mode Rise/Fall Time and Data Propagation Delay
- tSK1 = tPDH –tPDL for each driver.
- tSK2 computed by subtracting the shortest tPDH from the longest tPDH of the 2 drivers within a package.
- tSK3 computed by subtracting the shortest tPDL from the longest tPDL of the 2 drivers within a package.
1.5 VVin 0 V
Figure 4. Differential Mode Enable Timing 2.Above tests conducted by monitoring output current levels. Figure 5. Single–Ended Mode Rise/Fall Time and Data Propagation Delay
- tSK4 = tPDH –tPDL for each driver.
- tSK5 computed by subtracting the shortest tPDH from the longest tPDH of the 4 drivers within a package.
- tSK6 computed by subtracting the shortest tPDL from the longest tPDL of the 4 drivers within a package.
0.1 VSS /RL
0.5 VSS /RL
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Figure 6. Differential Output Voltage Figure 7. Internal Bias Current Figure 8. Short Circuit Current Figure 9. Input Current versus Figure 10. Output Voltage versus Figure 11. Output Voltage versus
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(Pin numbers refer to DIP and SO–16 packages only.)
Description
The AM26LS30 is a dual function line driver – it can be configured as two differential output drivers which comply with EIA–422–A Standard, or as four single–ended drivers which comply with EIA–423–A Standard. The mode of operation is selected w ith the M ode p in (Pin 4 ) and appropriate power supplies (see Table 1). Each of the four outputs is capable of sourcing and sinking 60 to 70 mA while providing s ufficient voltage to e nsure p roper data transmission. As differential drivers, data rates to 10 Mbaud can be transmitted over a twisted pair for a distance determined by the cable characteristics. EIA–422–A Standard provides guidelines for cable length versus data rate. The advantage of a differential (balanced) system over a single–ended system is greater noise immunity, common mode rejection, and higher data rates. Where extraneous noise sources are not a problem, the AM26LS30 may be configured as four single–ended drivers transmitting data rates to 100 Kbaud. Crosstalk among wires within a cable is controlled by the use of the slew rate control pins on the AM26LS30. Mode Selection (Differential Mode) In this mode (Pins 4 and 8 at ground), only a +5.0 V supply ±5% is required at VCC . Pins 2 and 7 are the driver inputs, while Pins 10, 11, 14 and 15 are the outputs (see Block Diagram on page 1). The two outputs of a driver are always complementary and the differential voltage available at each pair of outputs is shown in Figure 6 for VCC = 5.0 V. The differential output voltage will vary directly with VCC . A “high” output can only source current, while a “low” output can only sink current (except for short circuit current – see Figure 8). The two outputs will be in a high impedance mode when the respective Enable input (Pin 3 or 6) is high, or if VCC /C0112 1.1 V. Output leakage current over a common mode range of ±/n63686172000000000000000010 V is typically less than 1.0 µA. The outputs have short circuit current limiting, typically, less than 100 mA over a voltage range of 0 to +6.0 V (see Figure 8). Short circuits should not be allowed to last indefinitely as the IC may be damaged. Pins 9, 12, 13 and 16 are not normally used when in this mode, and should be left open. (Single–Ended Mode) In this mode (Pin 4 ≥ 2.0 V) VCC requires +5.0 V, and VEE requires –5.0 V, both ±5.0%. Pins 2, 3, 6, and 7 are inputs for the four drivers, and Pins 15, 14, 11, and 10 (respectively) are the outputs. The four drivers are independent of each other, and each output will be at a positive or a negative voltage depending on its input state, the load current, and the supply voltage. Figures 10 & 11 indicate the high and low output voltages for VCC = 5.0 V, and VEE = –5.0 V. The graph of Figure 10 will vary directly with VCC , and the graph of Figure 11 will vary directly with VEE . A “high” output can only source current, while a “low” output can only sink current (except short circuit current – see Figure 14). The outputs will be in a high impedance mode only if VCC /C0112 1.1 V. Changing VEE to 0 V does not set the outputs to a high impedance mode. Leakage current over a common mode range of ±10 V is typically less than 1.0 µA. The outputs have short circuit current limiting, typically less than 100 mA over a voltage range of ±6.0 V (see Figure 14). Short circuits should not be allowed to last indefinitely as the IC may be damaged. Capacitors connected between Pins 9, 12, 13, and 16 and their respective outputs will provide slew rate limiting of the output transition. Figure 16 indicates the required capacitor value to obtain a desired rise or fall time (measured between the 10% and 90% points). The positive and negative transition times will be within ≈ ±5% of each other. Each output may be set to a different slew rate if desired. Inputs The five inputs determine the state of the outputs in accordance with Table 1. All inputs (regardless of the operating mode) have a nominal threshold of +1.3 V, and their voltage must be kept within a range of 0 V to +15 V for proper operation. If an input is taken more than 0.3 V below ground, excessive currents will flow, and the proper operation of the drivers will be affected. An open pin is equivalent to a logic high, but good design practices dictate that inputs should n ever be left open. Unused inputs should b e connected to ground. The characteristics of the inputs are shown in Figure 9. Power Supplies VCC requires +5.0 V, ±5%, regardless of the mode of operation. The supply current is determined by the IC’s internal bias requirements and the total load current. The internally required current is a function of the load current and is shown in Figure 7 for the differential mode. In the single–ended mode, VEE must be –5.0 V, ±5% in order to comply with EIA–423–A standards. Figures 12 and 13 indicate the internally required bias currents as a function of total load current (the sum of the four output loads). The discontinuity at 0 load current exists due to a change in bias current when the inputs are switched. The supply currents vary ≈ ± 2.0 mA as VCC and VEE are varied from 4.75 V to 5.25 V. Sequencing of the supplies during power–up/power–down is not required. Bypass capacitors (0.1 µF minimum on each supply pin) are recommended to ensure proper operation. Capacitors reduce noise induced onto the supply lines by the switching action of the drivers, particularly where long P.C. board tracks are involved. Additionally, the capacitors help a bsorb transients induced onto the drivers’ outputs from the external cable (from ESD, motor noise, nearby computers, etc.).
TA = ambient air temperature near the IC package. suitability of the package types is calculated as follows. Figure 10. Note that the term (VCC – VOH ) is constant for a
10 MOTOROLA ANALOG IC DEVICE DATA
Figure 17. Although EIA–422–A does not specifically address calculating the maximum driver current. Figure 18. Multiple drivers on a single data line are not shield) in the cable so as to provide a common reference. operated in two other modes. operate the same as previously described. to each receiver and driver should be as short as possible. theoretically required only at the receiving end of the cable. end to prevent damage to the driver.
12 MOTOROLA ANALOG IC DEVICE DATA
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– B F C S H G D J L M 16 PL SEATING 1 8 916 K PLANE–T– MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 /C0095/C0095/C0095/C0095 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 1 8 16 9 SEATING PLANE F JM R X 45/C0095 G
8 PLP–B–
–A– M0.25 (0.010) B S –T– D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 /C0095 /C0095 /C0095 /C0095 PC SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R D SUFFIX PLASTIC PACKAGE CASE 751B–05 (SO–16) ISSUE J
13MOTOROLA ANALOG IC DEVICE DATA OUTLINE DIMENSIONS –M– –N– –L– Y BRK W V D D SL–MM0.007 (0.180) N ST SL–MM0.007 (0.180) N ST SL–MS0.010 (0.250) N STX G1 B U Z VIEW D–D 20 1 SL–MM0.007 (0.180) N ST SL–MM0.007 (0.180) N ST SL–MS0.010 (0.250) N ST C G VIEW S E J R Z A 0.004 (0.100) –T– SEATING PLANE SL–MM0.007 (0.180) N ST SL–MM0.007 (0.180) N ST H VIEW S K F NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.385 0.395 9.78 10.03 B 0.385 0.395 9.78 10.03 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 R 0.350 0.356 8.89 9.04 U 0.350 0.356 8.89 9.04 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Z 2 10 2 10 G1 0.310 0.330 7.88 8.38 /C0095 /C0095 /C0095 /C0095 FN SUFFIX PLASTIC PACKAGE CASE 775–02 ISSUE C
14 MOTOROLA ANALOG IC DEVICE DATA
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