AM2504

AM2502 ETC

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Eight-Bit/Twelve-Bit Successive Approximation IY store Distinctive Characteristics © Contains all the storage and control for successive © Can be used as serial-to-parallel converter or ring approximation A-to-D converters. counters. © Provision for register extension or truncation. © Electrically tested and optically inspected dice for © Can be operated in START-STOP or continuous the assemblers of hybrid products. conversion mode. FUNCTIONAL DESCRIPTION clock LOW-to-HIGH transition in order to guarantee correct resetting. The Am2502, Am2603 ond Am2504 are Sit and 12-bit TTL Sue. After the clock has gone HIGH resetting the roster, the 5 signal is cessive Approximation Registers. The registers contain al the digital femnoved. On the next clock LOW-to-HIGH transition the data on the Control and storoge necessary for successive approximation analog-to- __D input is set into the Qy11) register bit and the Qgl10) register bit is, digital conversion. They can also be used in digital systems as the set to @ LOW ready for the next clock cycle. On the next clock LOW. control and storage element in recursive digital routines toHIGH transition data enters the Og(10} register bit and Qg(9) is set ‘The registers consist of a set of master latches that act as the control 10.8 LOW. This operation is repeated for each register bit in fuen until elements in the device and change state when the input clock is LOW, the register has been filled. When the data goes into Qp, the CC signal ‘nd a set of slave latches that hold the register data and change on the 9928 LOW, and the register is inhibited from férther change until resat input clock LOW-to-HIGH transition, Externally the device acts as a BY ® Stert signal special purpose sarielto-parael converter that dccopts “ata at the D ia. order ta allow complementary conversion the complomentary input of the register and sends the date to the appropriate slave latch output of the most significant register bit is made available. An active to appear at the rogister output and the DO output on the Am2502 LOW enable input, E, on the AM2503 ond Am2504 allows devices to land Am2504 when the clock goes from LOW-to-HIGH. There are no be connected tagether to form a longer register by connecting the festritions on the data input; ft can change state at any time except clock, D, and § inputs together and connecting the CC output of one uring the setup timme just ptior to the clock trensition. At the same davice to the E input of the next les significant device, When the Start ‘ime thet data enters the register bit the next less significant bit is set signal resets the register, the E signal goes HIGH, forcing the Qy(11) bit to 8 LOW ready for the next iteration, HIGH and inhibiting the device from accepting data until the previous “The cegister is reset by holding the § (Start) signal LOW during the device js full and its CC goes LOW. If only one device is used the E Glock LOWGHIGH transition. The regis synchronauly resets to input should be held at a LOW logic level (Ground)._ fall che bits are the state Qy{11) LOW, (Note 2) and all the remaining register outputs ot required, the register may be truncated and conversion time saved HIGH, The EC (Conversion Complete) signal is also set HIGH at this by using a regster output going LOW rather than the CC signal to time, The signal should not be brought back HIGH until after the indicate the end of conversion, LOGIC DIAGRAMS peel] TT eel aoe gee Notes: 1. Cell logic is repeated for register stages. Og to Oy Am2502/3, Qg to Oy Am2504 2. Numbers in parentheses ore for Am2504. cme LOGIC SYMBOLS CONNECTION DIAGRAMS — Top Views i ii D-16, P-16 0-24, P-24 ces uuc226 ogo Bs Ba “Be Vee = Pin 24 B <q: Be vee= Pin 16 Guo pint2 = = co: Se = GND = Ping NC = Ping 10, 18.22 uczer Note: Pin 1 is marked for orientation. czas at ‘039208-ANA

MAXIMUM RATINGS (Above which the useful life may be impaired) Storage Temperature =65 10 +150°C Supply Voltage to Ground Potential Continuous. =05t0 +7V DC Voltage Applied to Outputs for High Output State =05 to +Voc max DC input Voltage =05 to +56V Output Current, Into Outputs 30mA DC Input Current =30 to +5.0mA ELECTRICAL CHARACTERISTICS over operating temperature and voltage ranges Typ Typ Parameters Description Test Conditions (ote 1} {Note 1) Units Ce ‘Output LOW Veo = MIN, to, = 8:6mA ma sme "| fe] | fe | cP, 0,5 ~16 -04 Ie Input HIGH Current co = MAK Vw = 5 wf 40) «| “| “eet HIGH Gurent | Veg = MAK = Sv [io || to [ise [ova srorcraGunon | ver=woxvour=oov || -w [as] as [wa ) we fos | | [xc {fs [os [fs [ss | hy Power Supply Current | voo = MAK | Am2s(a3 pw [feo foo [fa Ta | “ meres | e ms [pe [To [wo [ets] | pmasayos | 2“ | [20 [wo [| 30 Tae | | [xc [fo fm] To [as | Notes: 1. Typical Limits are at Voc = 5.0V, 25°C ambient and maximum toading. SWITCHING CHARACTERISTICS Ta = 25°C, Voc = +5.0V, CL = 15pF Parameters Description | win] tye [wax [win [ typ | mex | unite [_ TnGioaynomaNGHmaondy | «|» | pa pm] ‘aid ‘Tum Off Delay CP to Oy or Ory HIGH 35 [30 | 100 | 140 [ies | Tunney ecw ca [we [as fe | 4s) __| Soe Time Data tpt a te(8)__ | Setup Time Start Input so | «6 | fpont6) | TumOnDeay EW arcHHiGh | anasoaamasosy | | ws | 2 | | so | 7 | [iors | Mamaniow GoaPumewar fm we | | ow | | [ent | Mona GHOoa ewan emf | | Lime | Mesum ceorFremerey fs | | fas | so || we |

_ Am2502/3/4 Family un SWITCHING TIME WAVEFORMS “ —_H y KEY TO TIMING DIAGRAM ON, + — . |— au | NOMEN, HELL i sma | Teas vO of ove | — | JI Oy. | XXSTEOOAOOEATAROOOOSOOIOOO? SYRIA, OOOO Wh se Ses. ‘el eal ROTEL Feo. bape whos | FGRES en | we uN Lil N\\ | ea DEFINITION OF TERMS SUBSCRIPT TERMS: lon Output HIGH current, forced out of output Voy test. H_ HIGH, applying to a HIGH logic level or when used with Vc toy. Output LOW current, forced into the output in Voy test. to indicate high Voc value. iy, Reverse input load current

1 Input Negative Current Current flowing out of the device

L_LOW, applying to LOW logic level or when used with Voc 0 Positive Current Current flowing into the device. Indicate lew Voc value. Vin. Minimum logic HIGH input voltage © Output Vi__ Maximum logie LOW input voltage. FUNCTIONAL TERMS: Vow Minimum logic HIGH output voltage with output HIGH Fan-Out The logic HIGH or LOW output drive capability in current lon flowing out of output, terms of Input Unit Loads. Vot Maximum logic LOW output voltage with output LOW cur- Input Unit Load One T? L gate input load. In the HIGH state it rent Ig, flowing into output. is equal to hy and in the LOW state itis equal to ht SWITCHING TERMS: ( Measured at the 1.5V logic level). GP The clock input of the register. tau The propagation delay from the clock signal LOW-HIGH CC The conversion complete output. This output remains HtGH transition to an output signal HiGH-LOW transition. during a conversion and goes LOW when a conversion isComplete. —£ The propagation delay from the clock signa! LOW-HIGH D The serial data input of the register. transition to an output signal LOW-HIGH transition E The register enable. This input is used to expand the length of —_t,4_(E) The propagation delay from the Enable signal HIGH- the register and when HIGH forces the Q7(11) register output — LOW transition to the Q7(11) output signal HIGH-LOW trans- HIGH and inhibits conversion. When not used for expansion the ition enable is held at a LOW logic level (Ground). toge(E) ‘The propagation delay from the Enable signal LOW: Q7(11) The true output of the MSB of the register. HIGH transition to Q7(11) output signal LOW-HIGH transition. (11) The complement output of the MSB of the register. t(D) Setup time required for the logic level to be present at the Q;i = 7(114) t0.0 The outputs of the register. data input prior to the clock transition from LOW to HIGH in der for the register to respond. The data input should remain 3 The start input. If the start input is held LOW for at least a lock period the register will be reset to Q7(11) LOW and all the steady between t, max. and t, min. before the clock remaining outputs HIGH, A start pula hate LOW for ashorar 46) Set-up time require fr 9 LOW level vo be present atthe period of time can be used if it meets the set-up time require § input prior to the clock transition from LOW to HIGH in order ments of the § input. for the register to be reset, or time required for a HIGH level to, DO. The carat data output, (The D input delayed one bith be present on S before the HIGH to LOW clock transition to prevent resetting. OPERATIONAL TERMS: tw(CP) The minimum clock pulse width (LOW or HIGH) hy. Forward input load current. axa tesbired for proper register operation.

| USER NOTES FOR A/D CONVERSION Time Inputs ‘Outputs 1. The register can be used with either current switches inputs ONPG _|_ that require a low voltage level to turn the switch on, ee KKK turn the current switch on. If current switches are used o x LL xX x XK KX xX XK XX XX which turn on with 2 low logic level the resulting digital 1 OpHL xX LH HOH M HOH OH OH output from the register is active LOW. That is, a logic 2 Dg HL Dp o,L HH HH HOH OH 1" js represented as 2 low voltage level. If current swit- 3. De HL Dg 0 OL HH HH HOH ches are used that turn on with a high logic level then. t DLHL Oe 0; 0g D,t HH HORM the digital output is active HIGH; a logic “1”is repre- sented as a high voltage level.

5 Oy HL 04 D7 Og D5 gL HH HK H

Bee eee oe oe on Oy LH mH | 2 Fora maximum digital eror of #4LSB the comparator 2 307 06 Os Pa Da must be biased, If current switches that require a high

7 Dy HL Dz Dz Dg Os Og 03 07 L HH | voltage level to turn on are used, the comparator should

& 0g HL Dy Dy Dg Dg Dg Dy O_O; L_H | be biased +%4LSB and if the current switches require @ 9X HL Og 07 Og Dg Dg D3 Dz Dy Oy L high logic level to turn on then the comparator must be 0X XL xX Dy OG De Dg D3 Dy Dy Dp L | biased —4LSB, xX NH OX HNC NC NC NC NC NC NC NC | 3 The register, by suitable selection of resistor ladder net- work, can be used to perform either binary or BCD | conversion. Additional data input gating should be used to eliminate the possibility of false BCD codes. H1© PAGH Voltage Lave! 4, The register can be used to perform 2's complement Caron venage tev conversion by offsetting the comparator % full range X= Don't Care +% LSB and using the complement of the MSB Qy, NC = No Change (041) asthe sign bit. Note: Truth Table for Am2504 is extend to include 5. If the register is truncated and operated in the continuous 12 outputs conversion mode a lock-up condition may occur on power fon, This situation can be overcome by making the START input the OR function of CC and the appropriate register output. | ‘Am25(L)02/3 TIMING CHART an a uct ae

‘Am2502/3/4 Family ‘Am2502/3 LOADING RULES (IN UNIT LOADS) Am2504 LOADING RULES (IN UNIT LOADS} Input Fanout Input Fanout Pin Unit Load = Output Output Pin Unit Load = Output Output Input/Output No.’s LOW HIGH HIGH LOW Input/Output No.’s LOW HIGH HIGH LOW _E (503) 118 2 - oa 116 2) = DO (2502) 1 _ 2 6 DO 2 0- = 2 6 a <r oe 3 = = 2 6 Q% 3 - 1206 Qy 4 - - 12 6 a a a) ) i fe 38 we a D 7 i 1 = = Q, Ea = 12 6 ceo too — NG = s wo 1 20 = _ 2 nod 1 - — 4% Mm — = 2 6 | GND 22 = ~ Qs WZ = 2 6 cP 4391 Mo a a Soo a a NCO 8 = 3, Ln So Vee eS = = a, 7 = 12 6 MSI INTERFACING RULES eB Equivalent Qy 9 = 12 6 Input Unit Load | Qe Interfacing Digital Family HIGH LOW —0_____—_= = —- ee a, 2 = 12 6 Advanced Micro Devices 9300/2500 Series 1 1 NC 2 - =~ FSC Series9300 0 i 1 oy 3B - -— 2 6 Advanced Micro Devices 64/7400 MM fg Ti Series 4/7400 ee National Series DM 75/85, 1 1 DTL Series 930 12 1 NC = No Connection INPUT/OUTPUT INTERFACE CONDITIONS Voltage Interface Conditions — LOW & HIGH Current Interface Conditions - LOW aet aid oavenvow 4 ata. i 3 Bs Yin, . h Far) meus ty eur i Bue Mapes wotraae b | 23 oe 17s Pod Ye “|, \\

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£ ppt” You aed “auaee” Current Interface Conditions — HIGH > a2 moat auTPut omiviNG Aut Load ba wanity ve tie 1 Been gh oniwn veviee onveworvice 1 “ ‘ + ! om oot Vou, Mag — ! — 7 1 ‘rs ono = uc

‘Am2502/3/4 APPLICATION Continuous Conversion Analog-to-Digital Converter Tit | ——— . eal a boss Metallization and Pad Layouts Am2502 ‘Am2503 Am2504 oo a Yee e ne vee wy =F | voc ome ee Pa. > o dg eiemeet * Peete ie 5 ag ) Sea Beerte’. Sah ORDERING INFORMATION* ‘Order Order Package Temperature Number Number ‘Type Range Bits 7Aa5000M 7Ara6L000M ‘Hemet DP “Ht 250 3 ‘Am25030M Am25L03DM Hermetic DIP —55 to +125°C 8 ‘nm28040M Am2s.o1DM Hermetic DIP “8810 11250 2 Amas02eM ‘Am2SLOOFM Flat Package “Seto 11250 3 Am2503FM “Am25LO03FM Flat Package 55 to +125°C 8 ‘Am2504FM ANDSLOAPM ‘lat Package “sso 1256 2 /Am2502XM_ “Am25L02XM_ Dice —8$ to +125°C 8 Amas0axM ‘nm26L08XM Dice Seto +125 8 mas0axM ‘ama5.04%M Dice “85 125°C 8 7250200 ‘Am25.0200——~*Hermneve DIP Ot +700 3 Am2503DC ‘Am25L030C Hermetic DIP_ Oto +70°C 8 nr250406 jamasioaD0 Hermetic OP Oto +706 2 Am2502PC Am25L02PC Plastic Oto +70°C 8 ‘ames0aPC ‘AmasL02PC Plastic Ow 1706 8 amos0aPe pores Paste Oto +706 rs ‘nmas0oxe pusrets Dice Ow 1700 3 ‘ama503X¢ n25i09KC Dice de 700 3 amos0axe Aamesi0axe Dee Ow 1700 2 ___tmasoaxe _amastoaxc Dee Also available with burn-in processing, To order add sutfox B to part number. Ce a