Low Power, 12-Bit Analog-to-Digital Converter datasheet (Rev. A)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SBAS357,A]
- PDF pages: 23
Technical content
/C0066/C0117/C0114/C0114/C0262/C0066/C0114/C0111/C0119/C0110 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0102/C0114/C0111/C0109 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115
FEATURES
DESCRIPTION
APPLICATIONS
LOW-POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I C INTERFACE Complete 12-Bit Data Acquisition System in The ADS1000 is an I C-compatible serial interface a Tiny SOT-23 Package Analog-to-Digital (A/D) converter with differential inputs and bits of resolution in a tiny SOT23-6 Low Current Consumption: Only μ A package. Conversions are performed ratiometrically, Integral Nonlinearity: 1LSB Max using the power supply as the reference voltage. The Single-Cycle Conversion ADS1000 operates from a single power supply ranging from 2.7V to 5.5V. Programmable Gain Amplifier Gain or The ADS1000 performs conversions at a rate of 128 128SPS Data Rate samples per second (SPS). The onboard programmable gain amplifier (PGA), which offers I C Interface with Two Available Addresses gains of up to allows smaller signals to be Power Supply: 2.7V to 5.5V measured with high resolution. In single-conversion Pin- and Software-Compatible with 16-Bit mode, the ADS1000 automatically powers down after ADS1100 a conversion, greatly reducing current consumption during idle periods. The ADS1000 is designed for considerations. Typical instrumentation, consumer goods, and voltage Industrial Process Control monitoring. Consumer Goods Temperature Measurement Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. I2C is a trademark of NXP Semiconductors, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2006 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
www.ti.com PACKAGE/ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS (1) NOTE:□Marking□text□direction□indicates□pin□1.□Marking□text□depends□on□I C□address;□see□Package□Option□Addendum. BD0 VIN/c45 VDD SDA SCL GND VIN+ BD1 VIN/c45 VDD SDA SCL GND VIN+ I C□address:□□1001000 I C□address:□□1001001 ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet or see the TI website at www.ti.com Over operating free-air temperature range (unless otherwise noted). ADS1000 UNIT V DD to GND 0.3 to V Input Current (Momentary) 100 mA Input Current (Continuous) mA Voltage to GND, V IN+ V IN 0.3 to V DD to +0.3 V Voltage to GND, SDA, SCL 0.5 to V Maximum Junction Temperature, T J +150 C Operating Temperature to +125 C Storage Temperature to +150 C Lead Temperature (soldering, 10s) +300 C (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PIN CONFIGURATIONS Submit Documentation Feedback Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1000
www.ti.com ELECTRICAL CHARACTERISTICS ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 All specifications at C to +85 V DD 5V, GND 0V, and all PGAs, unless otherwise noted. ADS1000 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-Scale Input Voltage IN+ IN V DD /PGA (1) V Analog Input Voltage V IN+ V IN to GND GND 0.2 V DD 0.2 V Differential Input Impedance 2.4/PGA M Ω Common-Mode Input Impedance M Ω SYSTEM PERFORMANCE Resolution No Missing Codes Bits Data Rate 104 128 184 SPS Integral Nonlinearity (INL) 0.1 LSB Offset Error LSB Gain Error 0.01 0.1 DIGITAL INPUT/OUTPUT Logic Level V IH 0.7 VDD V V IL GND 0.5 0.3 V DD V V OL I OL 3mA GND 0.4 V Input Leakage I IH V IH 5.5V μ A I IL V IL GND μ A POWER-SUPPLY REQUIREMENTS Power-Supply Voltage V DD 2.7 5.5 V Supply Current Power-Down 0.05 μ A Active 150 μ A Power Dissipation μ A V DD 5.0V 450 750 μ W V DD 3.0V 210 μ W (1) Each input, V IN+ and V IN must meet the absolute input voltage specifications. Copyright 2006 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS1000
www.ti.com TYPICAL CHARACTERISTICS 250 225 200 175 150 125 100 10 100 1k 10k I 2C Bus Frequency (kHz) IVDD (µA) 25/C0095C −40/C0095C 125/C0095C 120 100 IVDD (µA) −60 −40 −20 0 20 40 60 80 100 120 140 Temperature (/C0095C) VDD = 5V VDD = 2.7V PGA = 8 PGA = 4 PGA = 2 PGA = 1 2.0 1.0 0.0 1.0 2.0 /c45 /c45 /c4540 /c4520 0 20 40 60 80 100 120 140/c4560 T emperature□(°C) Offset□Error□(mV) PGA□=□8 PGA□=□4 PGA□=□1 PGA□=□2 0.04 0.03 0.02 0.01 0.00 0.01 0.02 0.03 0.04 /c45 /c45 /c45 /c45 /c4540 /c4520 0 20 40 60 80 100 120 140/c4560 T emperature□(°C) Gain□Error□(%) VDD = 2.7V VDD = 5V 160 144 128 112 Data Rate (SPS) −60 −40 −20 0 20 40 60 80 100 120 140 Temperature (/C0095C) ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 At T A C and V DD 5V, unless otherwise indicated. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs I C BUS FREQUENCY Figure Figure OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE Figure Figure DATA RATE vs TEMPERATURE Figure Submit Documentation Feedback Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1000
www.ti.com THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTER RESET AND POWER-UP OUTPUT CODE CALCULATION I C INTERFACE Output Code/C00432048(PGA)/C0466V IN/C0041/C0042V IN− V DD /C0467 CLOCK GENERATOR USING THE ADS1000 OPERATING MODES ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 conversion has been completed, the ADS1000 places The ADS1000 is a fully differential, 12-bit A/D the result in the output register, and immediately converter. The ADS1000 allows users to obtain begins another conversion. When the ADS1000 is in precise measurements with a minimum of effort, and continuous conversion mode, the ST/BSY bit in the the device is extremely easy to design with and configuration register always reads '1'. configure. In single conversion mode, the ADS1000 waits until The ADS1000 consists of an A/D converter core with the ST/BSY bit in the conversion register is set to '1'. adjustable gain, a clock generator, and an I C When this happens, the ADS1000 powers up and interface. Each of these blocks are described in detail performs a single conversion. After the conversion in the sections that follow. completes, the ADS1000 places the result in the output register, resets the ST/BSY bit to '0' and powers down. Writing a '1' to ST/BSY while a conversion is in progress has no effect. The ADS1000 uses a switched-capacitor input stage. To external circuitry, it looks roughly like a resistance. When switching from continuous conversion mode to The resistance value depends on the capacitor single conversion mode, the ADS1000 will complete values and the rate at which they are switched. The the current conversion, reset the ST/BSY bit to '0' and switching clock is generated by the onboard clock power-down the device. generator, so its frequency, nominally 275kHz, is dependent on supply voltage and temperature. The capacitor values depend on the PGA setting. When the ADS1000 powers up, it automatically The common-mode and differential input impedances performs a reset. As part of the reset, the ADS1000 are different. For a gain setting of PGA, the sets all of the bits in the configuration register to their differential input impedance is typically 2.4M Ω /PGA. respective default settings. The common-mode impedance is typically Ω The ADS1000 responds to the I C General Call Reset command. When the ADS1000 receives a General Call Reset, it performs an internal reset, exactly as though it had just been powered on. The ADS1000 outputs codes in binary two s complement format. The output code is confined to the range of numbers: 2048 to 2047, and is given by: The ADS1000 communicates through an I C (Inter-Integrated Circuit) interface. The I C interface is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I C bus only drive the bus lines low, by connecting them to ground; they never drive the bus lines high. Instead, the bus wires are pulled high by pull-up The ADS1000 generator. resistors, so the bus wires are high when no device is The Typical Characteristics show variations in data driving them low. This way, two devices cannot rate over supply voltage and temperature. It is not conflict; if two devices drive the bus simultaneously, possible to operate the ADS1000 with an external there is no driver contention. clock. Communication on the I C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I C devices The ADS1000 operates in one of two modes: can act as masters or slaves, but the ADS1000 can continuous conversion and single conversion. only act as a slave device. In continuous conversion mode, the ADS1000 continuously performs conversions. Once a Copyright 2006 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS1000
www.ti.com ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 An I C bus consists of two lines, SDA and SCL. SDA Every byte transmitted on the I C bus, whether it be carries data; SCL provides the clock. All data is address or data, is acknowledged with an transmitted across the I C bus in groups of eight bits. acknowledge bit. When a master has finished To send a bit on the I C bus, the SDA line is driven to sending a byte, eight data bits, to a slave, it stops the bit level while SCL is low Low on SDA driving SDA and waits for the slave to acknowledge indicates the bit is '0'; a High indicates the bit is '1'). the byte. The slave acknowledges the byte by pulling Once the SDA line has settled, the SCL line is SDA low. The master then sends a clock pulse to brought high, then low. This pulse on SCL clocks the clock the acknowledge bit. Similarly, when a master SDA bit into the receiver shift register. has finished reading a byte, it pulls SDA low to acknowledge to the slave that it has finished reading The I C bus is bidirectional: the SDA line is used both the byte. It then sends a clock pulse to clock the bit. for transmitting and receiving data. When a master (Remember that the master always drives the clock reads from a slave, the slave drives the data line; line.) when a master sends to a slave, the master drives the data line. The master always drives the clock line. A not-acknowledge is performed by simply leaving The ADS1000 never drives SCL, because it cannot SDA high during an acknowledge cycle. If a device is act as a master. On the ADS1000, SCL is an input not present on the bus, and the master attempts to only. address it, it will receive a not-acknowledge because no device is present at that address to pull the line Most of the time the bus is idle, no communication low. takes place, and both lines are high. When communication takes place, the bus is active. Only When a master has finished communicating with a master devices can start a communication. They do slave, it may issue a stop condition. When a stop this by causing a start condition on the bus. Normally, condition is issued, the bus becomes idle again. A the data line is only allowed to change state while the master may also issue another start condition. When clock line is low. If the data line changes state while a start condition is issued while the bus is active, it is the clock line is high, it is either a start condition or its called a repeated start condition counterpart, a stop condition. A start condition is A timing diagram for an ADS1000 I C transaction is when the clock line is high and the data line goes shown in Figure Table gives the parameters for from high to low. A stop condition is when the clock this diagram. line is high and the data line goes from low to high. After the master issues a start condition, it sends a byte that indicates with which slave device it wants to communicate. This byte is called the address byte Each device on an I C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device. Submit Documentation Feedback Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1000
www.ti.com t(BUF) t(HDST A) t(LOW) tR tF t(HDDA T) t(HIGH) t(SUST A) t(SUDA T) t(HDST A) t(SUSTO) SCL SDA P S S P ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 Figure I C Timing Diagram Table Timing Diagram Definitions FAST MODE HIGH-SPEED MODE PARAMETER MIN MAX MIN MAX UNITS SCLK Operating Frequency f (SCLK) 0.4 3.4 MHz Bus Free Time Between STOP and START t (BUF) 600 160 ns Condition Hold Time After Repeated START Condition. t (HDSTA) 600 160 ns After this period, the first clock is generated. Repeated START Condition Setup Time t (SUSTA) 600 160 ns STOP Condition Setup Time t (SUSTO) 600 160 ns Data Hold Time t (HDDAT) ns Data Setup Time t (SUDAT) 100 ns SCLK Clock Low Period t (LOW) 1300 160 ns SCLK Clock High Period t (HIGH) 600 ns Clock/Data Fall Time t F 300 160 ns Clock/Data Rise Time t R 300 160 ns Copyright 2006 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS1000
www.ti.com ADS1000 I C ADDRESSES I C GENERAL CALL REGISTERS OUTPUT REGISTER I C DATA RATES ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 mode must be activated. To activate High-speed mode, send a special address byte of 00001XXX The ADS1000 I C address is either 1001000 or following the start condition, where the XXX bits are 1001001, set at the factory. The address is identified unique to the Hs-capable master. This byte is called with an or an within the orderable name. the Hs master code (Note that this is different from The two different I C variants are also marked normal address bytes; the low bit does not indicate differently. Devices with an I C address of 1001000 read/write status.) The ADS1000 will not have packages marked BD0 while devices with an acknowledge this byte; the I C specification prohibits I C address of 1001001 are marked with BD1 See acknowledgment of the Hs master code. On receiving the Package/Ordering Information Table for a a master code, the ADS1000 will switch on its complete listing of the ADS1000 I C addresses and High-speed mode filters, and will communicate at up tape and reel size. to 3.4MHz. The ADS1000 switches out of Hs mode with the next stop condition. For more information on High-speed mode, consult The ADS1000 responds to General Call Reset, which the I C specification. is an address byte of 00h followed by a data byte of 06h. The ADS1000 acknowledges both bytes. On receiving a General Call Reset, the ADS1000 The ADS1000 has two registers that are accessible performs a full internal reset, just as though it had via its I C port. The output register contains the result been powered off and then on. If a conversion is in of the last conversion; the configuration register process, it is interrupted; the output register is set to allows users to change the ADS1000 operating mode zero, and the configuration register returns to its and query the status of the device. default setting. The ADS1000 always acknowledges the General Call address byte of 00h, but it does not acknowledge any The 16-bit output register contains the result of the General Call data bytes other than 04h or 06h. last conversion in binary two s complement format. Since the port yields bits of data, the ADS1000 outputs right-justified and sign-extended codes. This output format makes it possible to perform averaging The I C bus operates in one of three speed modes: using a 16-bit accumulator. Standard which allows a clock frequency of up to 100kHz; Fast which allows a clock frequency of up to Following reset or power-up, the output register is 400kHz; and High-speed mode (also called Hs cleared to '0'; it remains zero until the first conversion mode), which allows a clock frequency of up to is completed. Therefore, if a user reads the ADS1000 3.4MHz. The ADS1000 is fully compatible with all just after reset or power-up, the output register will three modes. read '0'. No special action needs to be taken to use the The output register format is shown in Table ADS1000 in Standard or Fast modes, but High-speed Table OUTPUT REGISTER BIT NAME D15 (1) D14 (1) D13 (1) D12 (1) D11 D10 (1) D15 D12 are sign extensions of 12-bit data. Submit Documentation Feedback Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1000
www.ti.com CONFIGURATION REGISTER READING FROM THE ADS1000 WRITING TO THE ADS1000 ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 A user controls the ADS1000 operating mode and Bits PGA PGA settings via the 8-bit configuration register. The Bits and control the ADS1000 gain setting; see configuration register format is shown in Table The Table default setting is 80H. Table PGA Bits Table CONFIGURATION REGISTER PGA1 PGA0 GAIN (1) (1) (1) ST/BSY SC PGA1 PGA0 Bit ST/BSY The meaning of the ST/BSY bit depends on whether (1) Default setting. it is being written to or read from. In single conversion mode, writing a '1' to the ST/BSY bit causes a conversion to start, and writing a '0' has no effect. In continuous conversion mode, the ADS1000 ignores the value written to ST/BSY. A user can read the output register and the
contents
mode, ST/BSY of the configuration register from the ADS1000. To do indicates whether the A/D converter is busy taking a this, address the ADS1000 for reading, and read conversion. If ST/BSY is read as '1', the A/D three bytes from the device. The first two bytes are converter is busy, and a conversion is taking place; if the output register contents; the third byte is the '0', no conversion is taking place, and the result of the configuration register contents. last conversion is available in the output register. A user does not always have to read three bytes from In continuous mode, ST/BSY is always read as '1'. the ADS1000. If only the needed, read only two bytes. Bits and must be set to zero. Reading more than three bytes from the ADS1000 has no effect. All of the bytes beginning with the Bit SC fourth byte will be FFh. See Figure for a timing SC controls whether the ADS1000 is in continuous diagram of an ADS1000 read operation. conversion or single conversion mode. When SC is '1', the ADS1000 is in single conversion mode; when SC is '0', the ADS1000 is in continuous conversion A user can write new mode. The default setting is '0'. register (the change). To do this, address the ADS1000 for writing, and write one byte to it. This byte is written into the Bits and must be set to zero. configuration register. Writing more than one byte to the ADS1000 has no effect. The ADS1000 ignores any bytes sent to it after the first one, and will only acknowledge the first byte. See Figure for a timing diagram of an ADS1000 write operation. Copyright 2006 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS1000
www.ti.com Frame□1:□I C□Slave□Address□Byte Frame□2:□Output□Register□Upper□Byte Start□By Master ACK□By ADS1000 ACK□By Master From ADS1000 From ADS1000 1 9 1 9
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- ··SDA SCL SDA (Continued) SCL (Continued) 1 0 0 1 A2 A1 A0 R/W D15 D14 D13 D12 D11 D10 D9 D8 Frame□3:□Output□Register□Lower□Byte Frame□4:□Configuration□Register (Optional) ACK□By Master Stop□By Master ACK□By Master From ADS1000 1 9 1 D7 D6 D5 D4 D3 D2 D1 D0 ST/ BSY 0 0 SC 0 0 PGA1 PGA0 Frame□1:□I C□Slave□Address□Byte Frame□2:□Configuration□Register Start□By Master ACK□By ADS1000 ACK□By ADS1000 1 9 1 9 SDA SCL 0 0 1 A2 A1 A0 R/W ST/ BSY 0 0 SC PGA1 PGA0 Stop□By Master 0 0 ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 Figure Timing Diagram for Reading from the ADS1000 Figure Timing Diagram for Writing to the ADS1000 Submit Documentation Feedback Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1000
www.ti.com APPLICATION INFORMATION BASIC CONNECTIONS VIN/c45VIN+ SCL GND VDD SDA ADS1000 Positive□Input (0V□to□5V) Negative□Input (0V□to□5V) VDD VDD 4.7 F□(typ.)/c109 Microcontroller□or Microprocessor with□I C□Port SCL SDA I C□Pull-Up□Resistors 1k to□10k (typ.)/c87 /c87 ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 The ADS1000 interfaces directly to standard mode, fast mode, and high-speed mode I C controllers. Any microcontroller I C peripheral, including master-only For many applications, connecting the ADS1000 is and non-multiple-master I C peripherals, will work extremely simple. A basic connection diagram for the with the ADS1000. The ADS1000 does not perform ADS1000 is shown in Figure clock-stretching (that is, it never pulls the clock line The fully differential voltage input of the ADS1000 is low), so it is not necessary to provide for this unless ideal for connection to differential sources with other devices are on the same I C bus. moderately low source impedance, such as bridge Pull-up resistors are necessary on both the SDA and sensors and thermistors. Although the ADS1000 can SCL lines because I C bus drivers are open-drain. read bipolar differential signals, it cannot accept The size of these resistors depends on the bus negative voltages on either input. It may be helpful to operating speed and capacitance of the bus lines. think of the ADS1000 positive voltage input as Higher-value resistors consume less power, but noninverting, and of the negative input as inverting. increase the transition times on the bus, limiting the When the ADS1000 is converting, it draws current in bus speed. Lower-value resistors allow higher speed short spikes. The 0.1 μ F bypass capacitor supplies at the expense of higher power consumption. Long the momentary bursts of extra current needed from bus lines have higher capacitance and require the supply. smaller pullup resistors to compensate. The resistors should not be too small; if they are, the bus drivers may not be able to pull the bus lines low. Figure Typical Connections of the ADS1000 Copyright 2006 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS1000
www.ti.com CONNECTING MULTIPLE DEVICES VIN/c45VIN+ SCL GND VDD SDA ADS1000 VDD Microcontroller□or Microprocessor with□I C□Port SCL SDA NOTE:□ADS1000□power and□input□connections omitted□for□clarity. SDA SCL I C□Pull-Up□Resistors 1k to□10k (typ.)/c87 /c87 VDD Microcontroller□or Microprocessor with□I C□Port VIN/c45VIN+ SCL GND VDD SDA ADS1000A0 V IN/c45VIN+ SCL GND VDD SDA ADS1000A1 V IN/c45VIN+ SCL GND VDD SDA ADS1100A2NOTE:□ADS1000□power and□input□connections omitted□for□clarity. USING GPIO PORTS FOR I C ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 Connecting two ADS1000s to a single bus is almost trivial. An example showing two ADS1000s and one ADS1100 connected on a single bus is shown in Figure Multiple devices can be connected to a single bus (provided that their addresses are different). Note that only one set of pull-up resistors is needed per bus. A user might find that he or she needs to lower the pull-up resistor values slightly to compensate for the additional bus capacitance presented by multiple devices and increased line length. Figure 11. Using GPIO with a Single ADS1000 Bit-banging I C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and output modes to apply the proper bus states. To drive the line low, the pin is set to output a '0'; to let the line go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is pulling the line low, this device will read as a '0' in the port input register. Note that no pull-up resistor is shown on the SCL line. In this simple case, the resistor is not needed; the microcontroller can simply leave the line on output, and set it to '1' or '0' as appropriate. It can do this because the ADS1000 never drives its clock line low. This technique can also be used with multiple devices, and has the advantage of lower current consumption resulting from the absence of a resistive pull-up. If there are any devices on the bus that may drive their clock lines low, the above method should not be used; the SCL line should be high-Z or zero and a pull-up resistor provided as usual. Note also that this cannot be done on the SDA line in any case, because the ADS1000 does drive the SDA line low Figure 10. Connecting Multiple ADS1000s from time to time, as all I C devices do. Some microcontrollers have selectable strong pull-up circuits built into the GPIO ports. In some cases, Most microcontrollers have programmable these can be switched on and used in place of an input/output pins that can be set in software to act as external pull-up resistor. Weak pull-ups are also inputs or outputs. If an I C controller is not available, provided on some microcontrollers, but usually these the ADS1000 can be connected to GPIO pins, and are too weak for I C communication. If there is any the I C bus protocol simulated, or bit-banged, in doubt about the matter, test the circuit before software. An example of this for a single ADS1000 is committing it to production. shown in Figure Submit Documentation Feedback Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1000
www.ti.com SINGLE-ENDED INPUTS LOW-SIDE CURRENT MONITOR VIN/c45VIN+ SCL GND VDD SDA ADS1000 VDD Output Codes 0 2048/c45 Filter□Capacitor 33pF□to□100pF (typ.) 0V V Single-Ended /c45 DD NOTES:□□(1)□Pull-down□resistor□to□allow□accurate□swing□to□0V. (2)□R is□sized□for□a□50mV□drop□at□full-scale□current.S V Load RS (2) 1k/c87 G□=□12.5 /c45 5V OPA335 R 49.9k /c87 (1) FS□=□0.63V 5V5V 11.5k/c87 ADS1000 I C (PGA□Gain□=□8) 5V□FS ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 amplifier, which can output fully differential signals. This device can also help recover the lost bit noted Although the ADS1000 has a fully differential input, it previously for single-ended positive signals. can easily measure single-ended signals. A simple Level-shifting can also be performed using the single-ended connection scheme is shown in DRV134. Figure The ADS1000 is configured for single-ended measurement by grounding either of its input pins, usually V IN and applying the input signal to V IN+ The single-ended signal can range from Figure shows a circuit for a low-side shunt-type 0.2V to V DD 0.3V. The ADS1000 loses no linearity current monitor. The circuit reads the voltage across anywhere in its input range. Negative voltages cannot a shunt resistor, which is sized as small as possible be applied to this circuit because the ADS1000 inputs while still giving a readable output voltage. This can only accept positive voltages. voltage is amplified by an OPA335 low-drift op-amp, and the result is read by the ADS1000. Figure 12. Measuring Single-Ended Inputs The ADS1000 input range is bipolar differential with respect to the reference, that is, V DD The Figure 13. Low-Side Current Measurement single-ended circuit shown in Figure covers only half the ADS1000 input scale because it does not It is recommended that the ADS1000 be operated at produce differentially negative inputs; therefore, one a gain of The gain of the OPA335 can then be set bit of resolution is lost. The DRV134 balanced line lower. For a gain of the op amp should be driver can be employed to regain this bit for configured to give a maximum output voltage of no single-ended signals. greater than 0.75V. If the shunt resistor is sized to Negative input voltages must be level-shifted. A good provide a maximum voltage drop of 50mV at candidate for this function is the THS4130 differential full-scale current, the full-scale input to the ADS1000 is 0.63V. Copyright 2006 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS1000
www.ti.com ADDITIONAL RECOMMENDATIONS ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 stabilized; this momentary spike can damage the ADS1000. Sometimes this damage is incremental The ADS1000 is fabricated in a small-geometry and results in slow, long-term failure which can be low-voltage process. The analog inputs feature distastrous for permanently installed, low- protection diodes to the supply rails. However, the maintenance systems. current-handling ability of these diodes is limited, and the ADS1000 can be permanently damaged by If using an op amp or other front-end circuitry with the analog input voltages that remain more than ADS1000, be sure to take the performance approximately 300mV beyond the rails for extended characteristics of this circuitry into account; a chain is periods. One way to protect against overvoltage is to only as strong as its weakest link. place current-limiting resistors on the input lines. The Any data converter is only as good as its reference. ADS1000 analog inputs can withstand momentary For the ADS1000, the reference is the power supply, currents of as large as 10mA. and the power supply must be clean enough to The previous paragraph does not apply to the I C achieve the desired performance. If a power-supply ports, which can both be driven to regardless of filter capacitor is used, it should be placed close to the supply. the V DD pin, with no vias placed between the capacitor and the pin. The trace leading to the pin If the ADS1000 is driven by an op amp with high should be as wide as possible, even if it must be voltage supplies, such as 12V, protection should be necked down at the device. provided, even if the op amp is configured so that it will not output out-of-range voltages. Many op amps seek to one of the supply rails immediately when power is applied, usually before the input has Submit Documentation Feedback Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): ADS1000
www.ti.com ADS1000 SBAS357A SEPTEMBER 2006 REVISED OCTOBER 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 2006) to Revision A Page Changed logic level min value from (0.7GND) to (0.7VDD) Copyright 2006 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS1000
www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADS1000A0IDBVR Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD0 ADS1000A0IDBVR.B Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD0 ADS1000A0IDBVT Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD0 ADS1000A0IDBVT.B Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD0 ADS1000A0IDBVTG4 Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD0 ADS1000A1IDBVR Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD1 ADS1000A1IDBVR.B Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD1 ADS1000A1IDBVT Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD1 ADS1000A1IDBVT.B Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD1 ADS1000A1IDBVTG4 Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 BD1 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1
www.ti.com 11-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS1000 :
- Automotive : ADS1000-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1000A0IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 ADS1000A0IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 ADS1000A1IDBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 ADS1000A1IDBVT SOT-23 DBV 6 250 180.0 180.0 18.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2020 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.25 3.0 2.6 2X 0.95 1.45 0.90 0.15
0.00 TYP
6X 0.50 0.25 0.6
0.3 TYP
0 TYP
1.9 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/G 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/G 08/2024 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/G 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4
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