ADC78H89 7-Channel, 500 KSPS, 12-Bit A/D Converter datasheet (Rev. D)

Document overview

  • Manufacturer or author: Texas Instruments, Incorporated [SNAS201,D]
  • PDF pages: 26

Technical content

www.ti.com SNAS201D –APRIL 2003–REVISED MARCH 2013 ADC78H897-Channel,500KSPS,12-BitA/DConverter Check forSamples: ADC78H89 1FEATURES DESCRIPTION The ADC78H89 is a low-power, seven-channel 23• Seven InputChannels CMOS 12-bitanalog-to-digitalconverterwith a• VariablePower Management conversionthroughputof500 KSPS. The converteris

  • IndependentAnalog and DigitalSupplies based on a successive-approximationregister architecturewithan internaltrack-and-holdcircuit.It• SPI™ /QSPI™ /MICROWIRE ™ /DSP Compatible can be configuredtoacceptup toseven inputsignals• Packaged in16-Lead TSSOP on pinsAIN1 throughAIN7. The output serialdata is straightbinary,and isAPPLICATIONS compatiblewithseveralstandards,such as SPI™ ,• Automotive Navigation QSPI ™ , MICROWIRE ™ , and many common DSP
  • PortableSystems serialinterfaces.
  • MedicalInstruments The ADC78H89 may be operatedwithindependent
  • MobileCommunications analogand digitalsupplies.The analogsupply(AVDD ) can range from +2.7V to +5.25V, and the digital• Instrumentationand ControlSystems supply(DVDD )can rangefrom+2.7V toAV DD .Normal power consumptionusing a +3V or +5V supplyisKEY SPECIFICATIONS 1.5 mW and 8.3 mW, respectively.The power-down
  • Conversion Rate:500 KSPS featurereduces the power consumption to just 0.3µW usinga +3V supply,or 0.5µW usinga +5V• DNL: ± 1 LSB (max) supply.The ADC78H89 is packaged in a 16-lead• INL:± 1 LSB (max) TSSOP package. Operation over the industrial
  • Power Consumption temperaturerangeof−40°C to+85°C isensured. – 3V Supply:1.5mW (typ) – 5V Supply:8.3mW (typ) Connection Diagram Figure1. 16-Lead TSSOP See PW Package Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2TRI-STATE isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2003–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNAS201D –APRIL 2003–REVISED MARCH 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Block Diagram Pin Descriptionsand EquivalentCircuits Pin No. Symbol EquivalentCircuit Description ANALOG I/O 5 -11 AIN1 toAIN7 Analoginputs.These signalscan rangefrom0V toAV DD . Thispinisnotconnectedinternally,and can be leftfloating,ortiedto2 NC ground. DIGITAL I/O Digitalclockinput.The rangeoffrequenciesforthisinputis50 kHz 16 SCLK to8 MHz, withensuredperformanceat8 MHz. Thisclockdirectly controlstheconversionand readoutprocesses. Digitaldataoutput.The outputsamplesareclockedoutofthispinon15 DOUT fallingedges oftheSCLK pin. Digitaldatainput.The ADC78H89 's ControlRegisterisloaded14 DIN throughthispinon risingedges oftheSCLK pin. Chipselect.On thefallingedge ofCS, a conversionprocessbegins.1 CS Conversionscontinueas longas CS isheldlow. POWER SUPPLY Positiveanalogsupplypin.Thispinshouldbe connectedtoa quiet +2.7V to+5.25V sourceand bypassedtoGND with0.1µF ceramic3 AV DD monolithicand 1 µF tantalumcapacitorslocatedwithin1 cm ofthe power pin. Positivedigitalsupplypin.Thispinshouldbe connectedtoa +2.7V 13 DV DD toAV DD supply,and bypassedtoGND witha 0.1µF ceramic monolithiccapacitorlocatedwithin1 cm ofthepower pin. The groundreturnforbothanalogand digitalsupplies.These pins aretieddirectlytogetherinternally,so must be connectedtothe4,12 GND same potential.Ifany potentialexistsacrossthesepins,large currentswillflowthroughthedevice.

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www.ti.com SNAS201D –APRIL 2003–REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1)(2) AnalogSupplyVoltageAV DD −0.3Vto6.5V DigitalSupplyVoltageDV DD −0.3VtoAV DD + 0.3V,max 6.5V Voltageon Any PintoGND −0.3VtoAV DD +0.3V InputCurrentatAny Pin (3) ±10 mA Package InputCurrent(3) ±20 mA Power DissipationatTA = 25°C See (4) ESD Susceptibility(5) Human Body Model 2500V Machine Model 250V SolderingTemperature,Infrared,10 seconds (6) 260°C JunctionTemperature +150°C StorageTemperature −65°C to+150°C (1) Absolutemaximum ratingsarelimitingvalueswhichindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatings indicateconditionsforwhichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forspecificationsand test conditions,see theElectricalCharacteristics.The specificationsapplyonlyforthetestconditionslisted.Some performance characteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND = 0V,unlessotherwisespecified. (3) When theinputvoltageatany pinexceedsthepower supplies(thatis,VIN < AGND orVIN > VA orVD ),thecurrentatthatpinshouldbe limitedto10 mA. The 50 mA maximum package inputcurrentratinglimitsthenumber ofpinsthatcan safelyexceed thepower supplies withan inputcurrentof10 mA tofive. (4) The absolutemaximum junctiontemperature(TJmax) forthisdeviceis150°C. The maximum allowablepower dissipationisdictatedby TJmax, thejunction-to-ambientthermalresistance(θJA),and theambienttemperature(TA),and can be calculatedusingtheformula PD MAX = (TJmax − TA)/θJA.The valuesformaximum power dissipationlistedabove willbe reachedonlywhen theADC78H89 is operatedina severefaultcondition(e.g.when inputoroutputpinsaredrivenbeyond thepower supplyvoltages,orthepower supply polarityisreversed).Obviously,such conditionsshouldalwaysbe avoided. (5) Human body model is100 pF capacitordischargedthrougha 1.5kΩ resistor.Machine model is220 pF dischargedthroughZERO ohms. (6) See http://www.ti.com/forothermethods ofsolderingsurfacemount devices. OPERATING RATINGS (1)(2) OperatingTemperatureRange −40°C ≤ TA ≤ +85°C AV DD SupplyVoltage +2.7V to+5.25V DV DD SupplyVoltage +2.7V toAV DD DigitalInputPinsVoltageRange -0.3VtoAV DD ClockFrequency 50 kHz to8 MHz AnalogInputVoltage 0V toAV DD (1) Absolutemaximum ratingsarelimitingvalueswhichindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatings indicateconditionsforwhichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forspecificationsand test conditions,see theElectricalCharacteristics.The specificationsapplyonlyforthetestconditionslisted.Some performance characteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND = 0V,unlessotherwisespecified. PACKAGE THERMAL RESISTANCE Package θJA 16-leadTSSOP on 4-layer,2 oz.PCB 96°C /W Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC78H89

SNAS201D –APRIL 2003–REVISED MARCH 2013 www.ti.com ADC78H89 CONVERTER ELECTRICAL CHARACTERISTICS (1) The followingspecificationsapplyforAV DD = DV DD = +2.7V to5.25V,fSCLK = 8 MHz, fSAMPLE = 500 KSPS unlessotherwise noted.BoldfacelimitsapplyforTA = TMIN toTMAX :allotherlimitsTA = 25°C. Symbol Parameter Conditions Typical Limits Units(2) STATIC CONVERTER CHARACTERISTICS ResolutionwithNo MissingCodes AV DD = +5.0V,DV DD = +3.3V 12 Bits INL IntegralNon-Linearity AV DD = +5.0V,DV DD = +3.3V ±1 LSB (max) DNL DifferentialNon-Linearity AV DD = +5.0V,DV DD = +3.3V ±1 LSB (max) OE OffsetError AV DD = +5.0V,DV DD = +3.3V ±2 LSB (max) OEM OffsetErrorMatch AV DD = +5.0V,DV DD = +3.3V ±2 LSB (max) GE Gain Error AV DD = +5.0V,DV DD = +3.3V ±3 LSB (max) GEM Gain ErrorMatch AV DD = +5.0V,DV DD = +3.3V ±3 LSB (max) DYNAMIC CONVERTER CHARACTERISTICS AV DD = +5.0V,DV DD = +3.0V,THD TotalHarmonicDistortion -86 dBfIN = 40.2kHz,−0.02dBFS AV DD = +5.0V,DV DD = +3.0V,SFDR Spurious-FreeDynamic Range 88 dBfIN = 40.2kHz,−0.02dBFS AV DD = +5.0V,DV DD = +3.0V,Channel-to-ChannelCrosstalk -82 dBfIN = 40.2kHz IntermodulationDistortion,Second Order AV DD = +5.0V,DV DD = +3.0V, -93 dBTerms fa = 40.161kHz,fb = 41.015kHz IMD IntermodulationDistortion,ThirdOrder AV DD = +5.0V,DV DD = +3.0V, -90 dBTerms fa = 40.161kHz,fb = 41.015kHz AV DD = +5V 11 MHz FPBW -3dB FullPower Bandwidth AV DD = +3V 8 MHz ANALOG INPUT CHARACTERISTICS 0 toVIN InputRange VAV DD IDCL DC Leakage Current ±1 µA (max) InTrackMode 33 pF C INA InputCapacitance InHoldMode 3 pF DIGITAL INPUT CHARACTERISTICS DV DD = +4.75Vto+5.25V 2.4 V (min) VIH InputHighVoltage DV DD = +2.7V to+3.6V 2.1 V (min) VIL InputLow Voltage DV DD = +2.7V to+5.25V 0.8 V (max) IIN InputCurrent VIN = 0V orDV DD ±0.01 1 µA (max) C IND InputCapacitance 2 4 pF (max) DIGITAL OUTPUT CHARACTERISTICS ISOURCE = 200 µA,VOH OutputHighVoltage DV DD −0.5 V (min)DV DD = +2.7V to+5.25V VOL OutputLow Voltage ISINK = 200 µA 0.4 V (max) IOZH ,IOZL TRI-STATE Leakage Current ±1 µA (max) C OUT TRI-STATE OutputCapacitance 2 4 pF (max) OutputCoding Straight(Natural)Binary (1) Data sheetmin/max specificationlimitsarespecifiedby design,test,orstatisticalanalysis. (2) TestedlimitsarespecifiedtoAOQL (AverageOutgoingQualityLevel).

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www.ti.com SNAS201D –APRIL 2003–REVISED MARCH 2013 ADC78H89 CONVERTER ELECTRICAL CHARACTERISTICS (1)(continued) The followingspecificationsapplyforAV DD = DV DD = +2.7V to5.25V,fSCLK = 8 MHz, fSAMPLE = 500 KSPS unlessotherwise noted.BoldfacelimitsapplyforTA = TMIN toTMAX :allotherlimitsTA = 25°C. Symbol Parameter Conditions Typical Limits Units(2) POWER SUPPLY CHARACTERISTICS (CL = 10 pF)(3) 2.7 V (min)AV DD , Analogand DigitalSupplyVoltages AV DD ≥ DV DDDV DD 5.25 V (max) AV DD = DV DD = +4.75V to+5.25V, 1.65 2.3 mA (max)fSAMPLE = 500 KSPS, fIN = 40 kHzTotalSupplyCurrent,Normal Mode (Operational,CS low) AV DD = DV DD = +2.7V to+3.6V, 0.5 2.3 mA (max)fSAMPLE = 500 KSPS, fIN = 40 kHz IDD AV DD = DV DD = +4.75V to+5.25V, 0.1 µAfSAMPLE = 0 KSPSTotalSupplyCurrent,Shutdown (CS high) AV DD = DV DD = +2.7V to+3.6V, 0.1 µAfSAMPLE = 0 KSPS AV DD = DV DD = +4.75V to+5.25V 8.3 12 mW (max)Power Consumption,Normal Mode (Operational,CS low) AV DD = DV DD = +2.7V to+3.6V 1.5 8.3 mW (max) PD AV DD = DV DD = +4.75V to+5.25V 0.5 µWPower Consumption,Shutdown (CS high) AV DD = DV DD = +2.7V to+3.6V 0.3 µW AC ELECTRICAL CHARACTERISTICS fSCLK Maximum ClockFrequency 8 MHz (max) Minimum ClockFrequency 50 kHz fS Maximum Sample Rate 500 KSPS (min) tCONV ConversionTime 13 13 SCLK cycles 40 % (min) DC DutyCycle 50 60 % (max) tACQ Track/HoldAcquisitionTime Full-ScaleStepInput 3 SCLK cycles ThroughputTime ConversionTime + AcquisitionTime 16 SCLK cycles fRATE ThroughputRate 500 KSPS (min) tAD ApertureDelay 4 ns (3) Exceptpower supplypins. ADC78H89 TIMING SPECIFICATIONS The followingspecificationsapplyforAV DD = DV DD = +2.7V to5.25V,fSCLK = 8 MHz, C L = 50 pF,Boldfacelimitsapplyfor TA = TMIN toTMAX :allotherlimitsTA = 25°C. Symbol Parameter Conditions Typical Limits Units t1a SCLK HightoCS FallSetupTime See (1) 10 ns (min) t1b SCLK Low toCS FallHoldTime See (1) 10 ns (min) t2 DelayfromCS UntilDOUT TRI-STATE ™ Disabled 30 ns (max) t3 Data Access Time afterSCLK FallingEdge 30 ns (max) t4 Data SetupTime PriortoSCLK RisingEdge 10 ns (max) t5 Data ValidSCLK HoldTime 10 ns (max) t6 SCLK HighPulseWidth 0.4x tSCLK ns (min) t7 SCLK Low PulseWidth 0.4x tSCLK ns (min) t8 CS RisingEdge toDOUT High-Impedance 20 ns (max) (1) Clockmay be inany state(highorlow)when CS isasserted,withtherestrictionson setupand holdtimegivenby t1a and t1b. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC78H89

DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC DB11 DB9 DB8 DB1 1687654321 DB0 DIN DOUT SCLK CS ADC78H89 SNAS201D –APRIL 2003–REVISED MARCH 2013 www.ti.com Timing Diagrams Figure2. ADC78H89 OperationalTiming Diagram Figure3. Timing TestCircuit Figure4. ADC78H89 SerialTiming Diagram Figure5. SCLK and CS Timing Parameters

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10‡ A A ++Alog20 =THD ADC78H89 www.ti.com SNAS201D –APRIL 2003–REVISED MARCH 2013 SpecificationDefinitions ACQUISITION TIME isthe timerequiredto acquirethe inputvoltage.That is,itistimerequiredforthe hold capacitortochargeup totheinputvoltage. APERTURE DELAY isthetimebetween thefourthfallingSCLK edge ofa conversionand thetimewhen the inputsignalisacquiredorheldforconversion. CONVERSION TIME isthetimerequired,aftertheinputvoltageisacquired,fortheADC toconverttheinput voltagetoa digitalword. CROSSTALK isthecouplingofenergyfromone channelintotheotherchannel,ortheamount ofsignalenergy fromone analoginputthatappearsatthemeasured analoginput. DIFFERENTIAL NON-LINEARITY (DNL) isthemeasure ofthemaximum deviationfromtheidealstepsizeof1 LSB. DUTY CYCLE istheratioofthetimethata repetitivedigitalwaveform ishightothetotaltimeofone period.The specificationherereferstotheSCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) isanothermethod ofspecifyingSignal-to-Noise and DistortionorSINAD. ENOB isdefinedas (SINAD -1.76)/6.02and says thattheconverterisequivalenttoa perfectADC ofthis(ENOB) number ofbits. FULL POWER BANDWIDTH isa measure of the frequencyat which the reconstructedoutputfundamental drops3 dB belowitslowfrequencyvaluefora fullscaleinput. LSB),afteradjustingforoffseterror. INTEGRAL NON-LINEARITY (INL)isa measure ofthedeviationofeach individualcode froma linedrawn from negativefullscale(½ LSB below thefirstcode transition)throughpositivefullscale(½ LSB above thelastcode transition).The deviationofany givencode fromthisstraightlineismeasured fromthecenterofthatcode value. INTERMODULATION DISTORTION (IMD)isthecreationofadditionalspectralcomponents as a resultoftwo sinusoidalfrequenciesbeingappliedtotheADC inputatthesame time.Itisdefinedas theratioofthepower in thebothsecond order(orallfourthirdorder)intermodulationproductstothesum ofthepower inbothofthe originalfrequencies.IMD isusuallyexpressedindBFS. MISSING CODES arethoseoutputcodes thatwillneverappearattheADC outputs.The ADC78H89 isensured nottohave any missingcodes. 0.5LSB). SIGNAL TO NOISE RATIO (SNR) istheratio,expressedindB, oftherms valueoftheinputsignaltotherms value of the sum of allotherspectralcomponents below one-halfthe sampling frequency,not including harmonicsord.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Istheratio,expressedindB,oftherms valueofthe inputsignaltotherms valueofalloftheotherspectralcomponents below halftheclockfrequency,including harmonicsbutexcludingd.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) isthedifference,expressedindB, between therms valuesofthe inputsignaland thepeak spurioussignal,where a spurioussignalisany signalpresentintheoutputspectrum thatisnotpresentattheinput. TOTAL HARMONIC DISTORTION (THD) istheratio,expressedindB, expressedindB ordBc,oftherms total ofthefirstfiveharmoniccomponents attheoutputtotherms leveloftheinputsignalfrequencyas seen atthe output.THD iscalculatedas (1) where Af1 istheRMS power oftheinputfrequencyattheoutputand Af2 throughAf6 aretheRMS power inthe first5 harmonicfrequencies. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC78H89

SNAS201D –APRIL 2003–REVISED MARCH 2013 www.ti.com THROUGHPUT TIME isthe minimum timerequiredbetween the startof two successiveconversion.Itisthe acquisitiontimeplustheconversiontime.Inthecase oftheADC78H89, thisis16 SCLK periods.

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www.ti.com SNAS201D –APRIL 2003–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2kHz unlessotherwisestated. DNL DNL Figure6. Figure7. INL INL Figure8. Figure9. DNL vs.Supply INL vs.Supply Figure10. Figure11. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC78H89

SNAS201D –APRIL 2003–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2kHz unlessotherwisestated. SNR vs.Supply THD vs.Supply Figure12. Figure13. ENOB vs.Supply SNR vs.InputFrequency Figure14. Figure15. THD vs.InputFrequency ENOB vs.InputFrequency Figure16. Figure17.

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www.ti.com SNAS201D –APRIL 2003–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 500 KSPS, fSCLK = 8 MHz, fIN = 40.2kHz unlessotherwisestated. SpectralResponse SpectralResponse Figure18. Figure19. Power Consumption vs.Throughput Figure20. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC78H89

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APPLICATION INFORMATION

An operationaltimingdiagramand a serialinterfacetimingdiagramfortheADC78H89 areshown intheTiming Diagrams section.CS ischipselect,which initiatesconversionsand frames the serialdata transfers.SCLK (serialclock)controlsboththeconversionprocessand thetimingofserialdata.DOUT istheserialdataoutput pin,where a conversionresultissentas a serialdatastream,MSB first.Data tobe writtentotheADC78H89's ControlRegisterisplacedon DIN,theserialdatainpin. The conversionprocessand serialdatatimingare controlledby theSCLK. Each conversionrequires16 SCLK cyclesto complete.Conversionsare begun by bringingCS low. Several conversionscan be executed sequentiallyina singleserialframe,whichisdefinedas thetimebetween fallingand risingedges ofCS. IfCS is heldlowcontinuously,theADC78H89 willperformconversionscontinuously. Each timeCS goes low,a conversionprocessisinitiatedsimultaneouslywitha loadoftheControlRegister.The new contentsoftheControlRegisterwillaffectthenextconversion.There isthusa one sample delaybetween selectinga new inputchanneland observingthecorrespondingoutput. Basic operationof the ADC78H89 begins withCS going low and initiatinga conversionprocess and data transfer.At thistimetheDOUT pincomes outofthehighimpedance state.The converterenterstrackmode at thefirstfallingedge ofSCLK afterCS isbroughtlow,and beginstoacquiretheinputsignal.Acquisitionofthe inputsignalcontinuesduringthe firstthreeSCLK cyclesafterthe fallingedge of CS. Thisacquisitiontimeis denotedby tACQ .The convertergoes fromtracktoholdmode on thefourthfallingedge ofSCLK, and theanalog inputsignalissampled atthistime(seeFigure2). The ADC78H89 supportsidlingSCLK eitherhighorlow between conversions,when CS ishigh.The SCLK may alsorun continuouslywhileCS ishigh.Regardlessof whetherthe clockisidled,SCLK isinternallygated off when CS isbroughthigh.IfSCLK isinthelow statewhen CS goes high,thesubsequentfallofCS willgenerate a fallingedge oftheinternalversionofSCLK, puttingtheADC intothetrackmode. Thisisseen as thefirstfalling edge ofSCLK. IfSCLK isinthehighstatewhen CS goes high,theADC entersthetrackmode on thefirstfalling edge of SCLK afterthe fallingedge of CS (see Figure2).In both cases,a totalof sixteenfallingedges are requiredtocompletetheacquisitionand conversionprocess. SixteenSCLK cyclesare requiredto read a completesample from the ADC78H89. Each bitof the sample (includingleadingzeros)isvalidon subsequentrisingedges ofSCLK. The ADC78H89 willproducefourleading zeroson DOUT, followedby twelvedatabits,most significantfirst.The finaldatabit,DB0, willbe clockedouton the16thSCLK fallingedge,and willbe validon thefollowingrisingedge.Depending upon theapplication,the firstedge on SCLK afterCS goes low may be eithera fallingedge ora risingedge.IfthefirstSCLK edge after CS goes low isa fallingedge,allfourleadingzeroswillbe validon thefirstfourrisingedges ofSCLK. Ifthefirst SCLK edge afterCS goes low is a risingedge, the firstleadingzero may not be set up in time fora microprocessoror DSP toread itcorrectly.The remainingdatabitsare stillclockedouton thefallingedges of SCLK, so thattheyarevalidon therisingedges ofSCLK. Controlinformationmust be writtentotheControlRegisterwhenever a conversionisperformed.Informationis writtentotheControlRegisteron thefirsteightrisingedges ofSCLK ofeach conversion.Itisimportantthatthe DIN lineissetup withthecorrectinformationwhen readingdatafrom theADC78H89. The inputchanneltobe sampled inthenextconversionprocessisdeterminedby writinginformationtotheControlRegisterinthecurrent conversion. On therisingedges ofSCLK afterCS isbroughtlow,dataisloadedthroughtheDIN pintotheControlRegister, MSB first.Sincethedataon theDIN pinistransferredwhiletheconversiondataisbeingread,16 serialclocks are requiredforeach data transfer.The controlregisteronlyloadsthe informationon the first8 risingSCLK edges;DIN isignoredforthelast8 risingedges.Table1 describesthebitfunctions,where MSB indicatesthe firstbitofinformationintheloadeddata.Atpower-up,thecontrolregisterdefaultstoallzerosinthebitlocations. Table1.ControlRegisterBits Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

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www.ti.com SNAS201D –APRIL 2003–REVISED MARCH 2013 Table2.ControlRegisterBitDescriptions Bit#: Symbol: Description 7,6,2,1,0 DONTC Don'tcare.The valueofthisbitdoes notaffectthedevice. 5 ADD2 These threebitsdeterminewhichinputchannelwillbe sampled and convertedon thenextfallingedge ofCS. The mapping between codes and channelsisshown inTable3.4 ADD1

3 ADD0

Table3.InputChannel Selection ADD2 ADD1 ADD0 InputChannel 0 0 0 AIN1 (Default) 0 0 1 AIN2 0 1 0 AIN3 0 1 1 AIN4 1 0 0 AIN5 1 0 1 AIN6 1 1 0 AIN7 1 1 1 GND ADC78H89 OPERATION The ADC78H89 is a successive-approximationanalog-to-digitalconverterdesigned around a charge- redistributiondigital-to-analogconverter.SimplifiedschematicsoftheADC78H89 inbothtrackand holdmodes areshown inFigure21 and Figure22,respectively.InFigure21,theADC78H89 isintrackmode: switchSW1 connectsthe samplingcapacitorto one of seven analog inputchannelsthroughthe multiplexer,and SW2 balancesthe comparatorinputs.The ADC78H89 isin thisstateforthe firstthreeSCLK cyclesafterCS is broughtlow. The userdoes notneed toworryaboutany kindofpower-updelaysordummy conversionswiththeADC78H89. The partisabletoacquireinputtofullresolutioninthefirstconversionimmediatelyfollowingpower-up.The first conversionafterpower up willbe thatofthefirstchannel. Figure22 shows the ADC78H89 in hold mode: switchSW1 connects the sampling capacitorto ground, maintainingthesampled voltage,and switchSW2 unbalancesthecomparator.The controllogictheninstructs thecharge-redistributionDAC toadd or subtractfixedamounts ofchargefrom thesamplingcapacitoruntilthe comparatorisbalanced.When the comparatorisbalanced,the digitalword suppliedto the DAC isthe digital representationoftheanaloginputvoltage.The ADC78H89 isinthisstateforthelastthirteenSCLK cyclesafter CS isbroughtlow. Figure21. ADC78H89 inTrack Mode Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC78H89

SNAS201D –APRIL 2003–REVISED MARCH 2013 www.ti.com Figure22. ADC78H89 inHold Mode ADC78H89 TRANSFER FUNCTION The outputformatof the ADC89H89 isstraightbinary.Code transitionsoccur midway between successive integerLSB values.The LSB widthfortheADC78H89 isAV DD /4096.The idealtransfercharacteristicisshown inFigure23. Figure23. IdealTransferCharacteristic TYPICAL APPLICATION CIRCUIT A typicalapplicationof the ADC78H89 isshown inFigure24. The splitanalogand digitalsuppliesare both providedinthisexample by theTexas InstrumentsLP2950 low-dropoutvoltageregulator,availableina varietyof fixedand adjustableoutputvoltages.The analogsupplyisbypassed witha capacitornetworklocatedcloseto theADC78H89. The digitalsupplyisseparatedfrom theanalogsupplyby an isolationresistorand conditioned withadditionalbypass capacitors.The ADC78H89 uses theanalogsupply(AVDD )as itsreferencevoltage,so it isveryimportantthatAV DD be keptas cleanas possible.Because oftheADC78H89's lowpower requirements,it isalsopossibletouse a precisionreferenceas a power supplytomaximizeperformance.The four-wireinterface isalsoshown connectedtoa microprocessororDSP.

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www.ti.com SNAS201D –APRIL 2003–REVISED MARCH 2013 Figure24. TypicalApplicationCircuit ANALOG INPUTS An equivalentcircuitforone of the ADC78H89's inputchannelsisshown in Figure25. At the startof each conversion,one oftheADC78H89's seven channelsareselected.DiodesD1 and D2 provideESD protectionfor theanaloginputs.At no timeshouldan analoginputbe beyond (AVDD + 300 mV) or(GND -300 mV), as these ESD diodeswillbeginconducting,whichcouldcause erraticoperation. The capacitorC1 inFigure25 typicallyhas a valueof3 pF,and ismainlythepackage pincapacitance.Resistor R1 istheon resistanceofthemultiplexerand track/holdswitch,and istypically500 ohms. CapacitorC2 isthe ADC78H89 samplingcapacitor,and istypically30 pF.The ADC78H89 willdeliverbestperformancewhen driven by a low-impedancesourcetoeliminatedistortioncaused by thechargingofthesamplingcapacitor. Figure25. EquivalentInputCircuit Inapplicationswhere dynamic performanceiscritical,theADC78H89 mightneed tobe drivenwitha low output- impedance amplifier.Inaddition,when usingtheADC78H89 tosample AC signals,a band-passorlow-passfilter willreduceharmonicsand noise,improvingdynamicperformance. DIGITAL INPUTS AND OUTPUTS The ADC78H89's digitalinputs(SCLK, CS, and DIN)arelimitedby and cannotexceed theanalogsupplyvoltage AV DD .The digitalinputpinsarenotpronetolatch-up;SCLK, CS, and DIN may be assertedbeforeDV DD without any risk. POWER SUPPLY CONSIDERATIONS The ADC78H89 has two supplies,althoughtheycouldbothhave thesame potential.There aretwo majorpower supplyconcernswiththisproduct.They arerelativepower supplylevels,includingpower-onsequencing,and the effectofdigitalsupplynoiseon theanalogsupply. Power Management The ADC78H89 isa dual-supplydevice.These two suppliesshare ESD resources,and thus care must be exercisedtoensurethatthepower suppliesare appliedinthecorrectsequence.To avoidturningon theESD diodes,the digitalsupply (DVDD ) cannot exceed the analog supply (AVDD ) by more than 300 mV. The ADC78H89's analogpower supplymust,therefore,be appliedbefore(orconcurrentlywith)the digitalpower supply. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC78H89

SNAS201D –APRIL 2003–REVISED MARCH 2013 www.ti.com The ADC78H89 isfullypowered-upwhenever CS islow,and fullypowered-down whenever CS ishigh,withone exception:theADC78H89 automaticallyenterspower-down mode between the16thfallingedge ofa conversion and the1stfallingedge ofthesubsequentconversion(seeFigure2). The ADC78H89 can performmultipleconversionsback toback;each conversionrequires16 SCLK cycles.The ADC78H89 willperformconversionscontinuouslyas longas CS isheldlow. The usermay tradeoffthroughputforpower consumptionby simplyperformingfewerconversionsperunittime. The Power Consumption vs.Sample Rate curveintheTypicalPerformanceCurves sectionshows thetypical power consumptionoftheADC78H89 versusthroughput.To calculatethepower consumption,simplymultiply the fractionof timespentinthe normal mode by the normal mode power consumption(8.3mW withAV DD = DV DD = +3.6V,forexample),and add thefractionoftimespentinshutdown mode multipliedby theshutdown mode power dissipation(0.3mW withAV DD = DV DD = +3.6V). Power Supply Noise Considerations The chargingofany outputloadcapacitancerequirescurrentfrom thedigitalsupply,DV DD .The currentpulses requiredfrom thesupplytochargetheoutputcapacitancewillcause voltagevariationson thedigitalsupply.If these variationsare largeenough, they could cause degrade SNR and SINAD performanceof the ADC. Furthermore,iftheanalogand digitalsuppliesare tieddirectlytogether,thenoiseon thedigitalsupplywillbe coupled directlyintothe analog supply,causinggreaterperformancedegradationthan noise on the digital supply.Furthermore,dischargingtheoutputcapacitancewhen thedigitaloutputgoes froma logichightoa logic low willdump currentintothe die substrate,which isresistive.Load dischargecurrentswillcause "ground bounce"noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.The largeris theoutputcapacitance,themore currentflowsthroughthediesubstrateand thegreateristhenoisecoupledinto theanalogchannel,degradingnoiseperformance. The firstsolutionisto decouplethe analogand digitalsuppliesfrom each other,or use separatesuppliesfor them,tokeep digitalnoiseoutoftheanalogsupply.To keep noiseoutofthedigitalsupply,keep theoutputload capacitanceas smallas practical.Iftheloadcapacitanceisgreaterthan25 pF, use a 100 Ω seriesresistorat the ADC output,locatedas closeto the ADC outputpinas practical.Thiswilllimitthe charge and discharge currentoftheoutputcapacitanceand improvenoiseperformance.

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REVISION HISTORY

Changes from RevisionC (March 2013)toRevisionD Page Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADC78H89

www.ti.com 1-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADC78H89CIMT/NOPB Active Production TSSOP (PW) | 16 92 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 78H89 CIMT ADC78H89CIMT/NOPB.A Active Production TSSOP (PW) | 16 92 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 78H89 CIMT ADC78H89CIMT/NOPB.B Active Production TSSOP (PW) | 16 92 | TUBE - Call TI Call TI -40 to 85 ADC78H89CIMTX/NOPB Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 78H89 CIMT ADC78H89CIMTX/NOPB.A Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 78H89 CIMT ADC78H89CIMTX/NOPB.B Active Production TSSOP (PW) | 16 2500 | LARGE T&R - Call TI Call TI -40 to 85 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 1-Nov-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC78H89CIMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADC78H89CIMT/NOPB PW TSSOP 16 92 495 8 2514.6 4.06 ADC78H89CIMT/NOPB.A PW TSSOP 16 92 495 8 2514.6 4.06 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

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