ADC10080 10-Bit, 80 MSPS, 3V, 78.6 mW A/D Converter datasheet (Rev. H)

Document overview

  • Manufacturer or author: Texas Instruments, Incorporated [SNAS177,H]
  • PDF pages: 27

Technical content

www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 ADC1008010-Bit,80MSPS,3V,78.6mW A/DConverter Check forSamples: ADC10080 1FEATURES DESCRIPTION The ADC10080 is a monolithicCMOS analog-to- 2• Single+3.0V Operation digitalconvertercapableof convertinganalog input• SelectableFull-ScaleInputSwing signalsinto10-bitdigitalwords at 80 Megasamples

  • 400 MHz −3 dB InputBandwidth (1) per second (MSPS). This converter uses a differential,pipelinearchitecturewith digitalerror• Low Power Consumption correctionand an on-chipsample-and-holdcircuitto• Standby Mode provide a complete conversion solutionand to
  • On-Chip Referenceand Sample-and-Hold minimize power consumption, while providing Amplifier excellentdynamic performance.A unique sample- and-holdstageyieldsa full-powerbandwidthof 400• OffsetBinaryor Two ’s Complement Data MHz. Operatingon a single3.0V power supply,thisFormat device consumes just 78.6 mW at 80 MSPS,• SeparateAdjustableOutput DriverSupply includingthe referencecurrent.The Standby feature reducespower consumptiontojust15 mW. KEY SPECIFICATIONS The differentialinputsprovidea fullscaleselectable• Resolution:10 Bits inputswing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, withthe possibilityof a single-endedinput.Fulluse of the• Conversion Rate:80 MSPS differentialinput is recommended for optimum• FullPower Bandwidth: 400 MHz performance.An internal+1.2V precisionbandgap• DNL: ±0.25LSB (typ) referenceisused tosettheADC full-scalerange,and
  • SNR (fIN = 10 MHz): 59.5dB (typ) alsoallowstheusertosupplya bufferedreferenced voltagefor those applicationsrequiringincreased• SFDR (fIN = 10 MHz): −78.7dB (typ) accuracy.The outputdata formatisuser choiceof• Power Consumption, 80 Msps: 78.6mW offsetbinaryortwo’s complement. This device is availablein the 28-lead TSSOPAPPLICATIONS package and will operate over the industrial• Ultrasoundand Imaging temperaturerangeof−40°C to+85°C.
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  • DSP FrontEnds (1) The inputbandwidthislimitedusinga 10 pF capacitor between VIN − and VIN Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2003–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM CONNECTION DIAGRAM Figure1. 28-Lead TSSOP Package Package Number PW

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www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 Table1.PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol EquivalentCircuit Description ANALOG I/O Invertinganaloginputsignal.Witha 1.2Vreferencethefull-scale

12 VIN

− inputsignallevelisa differential1.0VP-P.Thispinmay be tiedto VCOM (pin4)forsingle-endedoperation. Non-invertinganaloginputsignal.Witha 1.2Vreferencethefull-13 VIN scaleinputsignallevelisa differential1.0VP-P. Referenceinput.Thispinshouldbe bypassedtoVSSA witha 0.1µF 6 VREF monolithiccapacitor.VREF is1.20Vnominal.Thispinmay be driven by a 1.20Vexternalreferenceifdesired.Do notloadthispin.

7 VREFT

4 VCOM

These pinsarehighimpedance referencebypasspinsonly. Connecta 0.1µF capacitorfromeach ofthesepinstoVSSA .These pinsshouldnotbe loaded.VCOM may be used tosettheinput common inputvoltage,VCM .8 VREFB Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com Table1.PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued) Pin No. Symbol EquivalentCircuit Description DIGITAL I/O Digitalclockinput.The rangeoffrequenciesforthisinputis20 MHz1 CLK to80 MHz. The inputissampled on therisingedge ofthisinput. DF = “1”Two ’s Complement15 DF DF = “0”OffsetBinary Thisisthestandbypin.When high,thispinsetstheconverterinto28 STBY standbymode. When thispinislow,theconverterisinactivemode. IRS = “VDDA ”2.0VP-P differentialinputrange IRS = “VSSA ”1.5VP-P differentialinputrangeIRS (InputRange5 IRS = “Floating”1.0VP-P differentialinputrangeSelect) IfusingbothVIN+ and VIN-pins,(ordifferentialmode),thenthe peak-to-peakvoltagereferstothedifferentialvoltage(VIN+ -VIN-). 16–20, Digitaloutputdata.D0 istheLSB and D9 istheMSB ofthebinaryD0 –D923–27 outputword. ANALOG POWER Positiveanalogsupplypins.These pinsshouldbe connectedtoa quiet3.0Vsourceand bypassedtoanaloggroundwitha 0.1µF2,9,10 VDDA monolithiccapacitorlocatedwithin1 cm ofthesepins.A 4.7µF capacitorshouldalsobe used inparallel. 3,11,14 VSSA Ground returnfortheanalogsupply. DIGITAL POWER PositivedigitalsupplypinsfortheADC10080's outputdrivers.This pinshouldbe bypassedtodigitalgroundwitha 0.1µF monolithic 22 VDDIO capacitorlocatedwithin1 cm ofthispin.A 4.7µF capacitorshould alsobe used inparallel.The voltageon thispinshouldneverexceed thevoltageon VDDA by more than300 mV. The groundreturnforthedigitalsupplyfortheoutputdrivers.This

21 VSSIO pinshouldbe connectedtothegroundplane,butnotnearthe

analogcircuitry. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1)(2)(3) VDDA ,VDDIO 3.9V Voltageon Any PintoGND −0.3VtoVDDA orVDDIO +0.3V InputCurrenton Any Pin ±25 mA Package InputCurrent(4) ±50 mA Package DissipationatT = 25°C See (5) ESD Susceptibility(6) Human Body Model 2500V Machine Model 250V SolderingTemperatureInfrared,10 sec.(7) 235°C StorageTemperature −65°C to+150°C (1) Allvoltagesaremeasured withrespecttoGND = VSSA = VSSIO = 0V,unlessotherwisespecified. (2) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications (4) When thevoltageatany pinexceedsthepower supplies(VIN < VSSA orVIN > VDDA ),thecurrentatthatpinshouldbe limitedto25 mA. The 50 mA maximum package inputcurrentratinglimitsthenumber ofpinsthatcan safelyexceed thepower supplieswithan input currentof25 mA totwo. (5) The absolutemaximum junctiontemperature(TJmax) forthisdeviceis150°C. The maximum allowablepower dissipationisdictatedby TJmax, thejunction-to-ambientthermalresistance(θJA),and theambienttemperature(TA),and can be calculatedusingtheformula PD MAX = (TJmax − TA)/θJA.Inthe28-pinTSSOP, θJA is96°C/W, so PD MAX = 1,302mW at25°C and 677 mW atthemaximum operatingambienttemperatureof85°C. Note thatthepower dissipationofthisdeviceundernormaloperationwilltypicallybe about78.6 mW. The valuesformaximum power dissipationlistedabove willbe reachedonlywhen theADC10080 isoperatedina severefault condition. (6) Human body model is100 pF capacitordischargedthrougha 1.5kΩ resistor.Machine model is220 pF dischargedthrough0Ω. (7) The 235°C reflowtemperaturereferstoinfraredreflow.ForVapor Phase Reflow(VPR) thefollowingconditionsapply:Maintainthe temperatureatthetopofthepackage body above 183°C fora minimum of60 seconds.The temperaturemeasured on thepackage body must notexceed 220°C. Onlyone excursionabove 183°C isallowedperreflowcycle.The analoginputsareprotectedas shown below.Inputvoltagemagnitudeup to500 mV beyond thesupplyrailswillnotdamage thisdevice.However,inputerrorswillbe generatediftheinputgoes above VDDA orVDDIO and belowVSSA orVSSIO . OPERATING RATINGS (1)(2) OperatingTemperatureRange −40°C ≤ TA ≤ +85°C VDDA (SupplyVoltage) +2.7V to+3.6V VDDIO (OutputDriverSupplyVoltage) +2.5V toVDDA VREF 1.20V |VSSA –VSSIO | ≤ 100 mV ClockDutyCycle 30 to70 % (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND = VSSA = VSSIO = 0V,unlessotherwisespecified. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com CONVERTER ELECTRICAL CHARACTERISTICS Unlessotherwisespecified,thefollowingspecificationsapplyforVSSA = VSSIO = 0V (1)(1)(2),VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P,STBY = 0V,VREF = 1.20V(External),fCLK = 80 MHz, 50% DutyCycle,C L = 10 pF/pin.BoldfacelimitsapplyforTA = TMIN toTMAX :allotherlimitsTA = 25°C.(3)(1)(2) Symbol Parameter Conditions Min Typ Max Units STATIC CONVERTER CHARACTERISTICS No MissingCodes ensured 10 Bits INL IntegralNon-Linearity(4) FIN = 500 kHz,0 dB FullScale −1.4 ±0.5 +1.6 LSB DNL DifferentialNon-Linearity FIN = 500 kHz,0 dB FullScale −0.9 ±0.25 +1.0 LSB PositiveError −1.6 +0.5% +2.0 % FS GE Gain Error NegativeError −1.6 −0.07% +2.0 % FS OE OffsetError(VIN+ = VIN−) −1.4 0.11 1.7 % FS Under Range OutputCode 0 Over Range OutputCode 1023 FPBW FullPower Bandwidth 400 MHz REFERENCE AND INPUT CHARACTERISTICS VCM Common Mode InputVoltage 0.5 1.5 V OutputVoltageforuse as an inputVCOM 1.45 Vcommon mode voltage(5) VREF InternalReferenceVoltage 1.2 V ExternalReverenceVoltage 1.0 1.2 1.5 V InternalReferenceVoltageVREFTC ±80 ppm/°CTemperatureCoefficient C IN VIN InputCapacitance(eachpinto 4 pFVSSA ) POWER SUPPLY CHARACTERISTICS STBY = 1 5 6.3 mA IVDDA AnalogSupplyCurrent STBY 0 25 32 mA STBY = 1,fIN= 0 Hz 0 mA IVDDIO DigitalSupplyCurrent(6) STBY 0,fIN = 0 Hz 1.2 1.4 mA STBY = 1 15 18.9 mW PWR Power Consumption(7) STBY = 0 78.6 100.2 mW (1) Withthetestconditionfor2 VP-P differentialinput,the10-bitLSB is1.95mV. (2) TypicalfiguresareatTA = TJ = 25°C and representmost likelyparametricnorms.TestlimitsareensuredtoAOQL (AverageOutgoing QualityLevel). (3) To ensureaccuracy,itisrequiredthat|VDDA –VDDIO |≤ 100 mV and separatebypasscapacitorsareused ateach power supplypin. (4) TimingspecificationsaretestedatTTL logiclevels,VIL= 0.4Vfora fallingedge,and VIH = 2.4Vfora risingedge. (5) VCOM istypicalvalue,measured atroom temperature.Itisnotensuredby test.Thispinshouldnotbe loaded. (6) IVDDIO isthecurrentconsumed by theswitchingoftheoutputdriversand isprimarilydeterminedby loadcapacitanceon theoutputpins, thesupplyvoltage,VDDIO ,and therateatwhichtheoutputsareswitching(whichissignaldependent).IDR = VDR x (C0 x f0 + C 1 x f1 + C 2 + f2 +....C11 x f11)where VDR istheoutputdriversupplyvoltage,C n isthetotalloadcapacitanceon theoutputpin,and fn isthe averagefrequencyatwhichthepinistoggling. (7) Power consumptionincludesoutputdriverpower.(fIN = 0 MHz).

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www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 DC AND LOGIC ELECTRICAL CHARACTERISTICS Unlessotherwisespecified,thefollowingspecificationsapplyforVSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,VREF = 1.20V(External),fCLK = 80 MHz, 50% DutyCycle,C L = 10 pF/pin.BoldfacelimitsapplyforTA = TMIN to TMAX :allotherlimitsTA = 25°C (1)(2)(3) Symbol Parameter Conditions Min Typ Max Units CLK, DF, STBY, SENSE Logical“1”InputVoltage 2 V Logical“0”InputVoltage 0.8 V Logical“1”InputCurrent +10 µA Logical“0”InputCurrent −10 µA D0 –D9 OUTPUT CHARACTERISTICS Logical“1”OutputVoltage IOUT = −0.5mA VDDIO −0.2 V Logical“0”OutputVoltage IOUT = 1.6mA 0.4 V DYNAMIC CONVERTER CHARACTERISTICS (4) 9.3 9.5 BitsfIN = 10.0MHz 9.1 ENOB EffectiveNumber ofBits 9.3 9.5 BitsfIN = 39 MHz 8.9 58.5 59.5 dBfIN = 10.0MHz 57.7 SNR Signal-to-NoiseRatio 58.0 59.2 dBfIN = 39 MHz 57.0 58.0 dBfIN = 10.0MHz 59.256.3 SINAD Signal-to-NoiseRatio+ Distortion 57.6 dBfIN = 39 MHz 59.055.6 −74.1fIN = 10.0MHz −87.0 dBc−68.7 2nd HD 2nd Harmonic −69.5fIN = 39 MHz −82 dBc−62.7 −65fIN = 10.0MHz −72.3 dBc−58.6 3rdHD 3rdHarmonic −64.7fIN = 39 MHz −74.5 dBc−57.6 (1) To ensureaccuracy,itisrequiredthat|VDDA –VDDIO |≤ 100 mV and separatebypasscapacitorsareused ateach power supplypin. (2) Withthetestconditionfor2 VP-P differentialinput,the10-bitLSB is1.95mV. (3) TypicalfiguresareatTA = TJ = 25°C and representmost likelyparametricnorms.TestlimitsareensuredtoAOQL (AverageOutgoing QualityLevel). (4) Optimum dynamicperformancewillbe obtainedby keepingthereferenceinputat+1.2V. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS Unlessotherwisespecified,thefollowingspecificationsapplyforVSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,VREF = 1.20V,(ExternallySupplied)fCLK = 80 MHz, 50% DutyCycle,C L = 10 pF/pin.Boldfacelimitsapplyfor TA = TMIN toTMAX :allotherlimitsTA = 25°C (1)(2)(3)(4) Min Typ MaxSymbol Parameter Conditions Units(4) (4) (4) CLK, DF, STBY, SENSE fCLK 1 Maximum ClockFrequency 80 MHz (min) fCLK 2 Minimum ClockFrequency 20 MHz tCH ClockHighTime 6.25 ns tCL ClockLow Time 6.25 ns ConversionLatency 6 Cycles T = 25°C 2 3.5 5 nsData OutputDelayaftera RisingClocktOD Edge 1 6 ns tAD ApertureDelay 1 ns tAJ ApertureJitter 2 ps (RMS) DifferentialVIN stepfrom±3V Over Range RecoveryTime to0V togetaccurate 1 ClockCycle conversion tSTBY StandbyMode ExitCycle 20 Cycles (1) To ensureaccuracy,itisrequiredthat|VDDA –VDDIO |≤ 100 mV and separatebypasscapacitorsareused ateach power supplypin. (2) Withthetestconditionfor2 VP-P differentialinput,the10-bitLSB is1.95mV. (3) TypicalfiguresareatTA = TJ = 25°C and representmost likelyparametricnorms.TestlimitsareensuredtoAOQL (AverageOutgoing QualityLevel). (4) TimingspecificationsaretestedatTTL logiclevels,VIL= 0.4Vfora fallingedge,and VIH = 2.4Vfora risingedge. SpecificationDefinitions APERTURE DELAY isthetimeaftertherisingedge oftheclocktowhen theinputsignalisacquiredorheldfor conversion. APERTURE JITTER (APERTURE UNCERTAINTY) isthevariationinaperturedelayfromsample tosample. Aperturejittermanifestsitselfas noiseintheoutput. COMMON MODE VOLTAGE (VCM ) isthed.c.potentialpresentatbothsignalinputstotheADC. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) isthemeasure ofthemaximum deviationfromtheidealstepsizeof1 LSB. DUTY CYCLE istheratioofthetimethata repetitivedigitalwaveform ishightothetotaltimeofone period.The specificationherereferstotheADC clockinputsignal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) isanothermethod ofspecifyingSignal-to-Noise and DistortionorSINAD. ENOB isdefinedas (SINAD -1.76)/6.02and statesthattheconverteris equivalenttoa perfectADC ofthis(ENOB) number ofbits. FULL POWER BANDWIDTH isa measure ofthefrequencyatwhichthereconstructedoutputfundamental drops3 dB belowitslowfrequencyvaluefora fullscaleinput. GAIN ERROR isthedeviationfromtheidealslopeofthetransferfunction.Itcan be calculatedas: Gain Error= PositiveFull-ScaleError− NegativeFull-ScaleError (1) INTEGRAL NON LINEARITY (INL)isa measure ofthedeviationofeach individualcode froma linedrawn from negativefullscalethroughpositivefullscale.The deviationofany givencode fromthisstraightlineis measured fromthecenterofthatcode value. MISSING CODES arethoseoutputcodes thatwillneverappearattheADC outputs.The ADC10080 isensured nottohave any missingcodes. NEGATIVE FULL SCALE ERROR isthedifferencebetween theinputvoltage(VIN + − VIN −)justcausinga

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www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 transitionfromnegativefullscaletothefirstcode and itsidealvalueof0.5LSB. OFFSET ERROR istheinputvoltagethatwillcause a transitionfroma code of01 1111 1111 toa code of10 0000 0000. OUTPUT DELAY isthetimedelayaftertherisingedge oftheclockbeforethedataupdateispresentedatthe outputpins. PIPELINE DELAY (LATENCY) isthenumber ofclockcyclesbetween initiationofconversionand when that dataispresentedtotheoutputdriverstage.Data forany givensample isavailableattheoutputpinsthe PipelineDelayplustheOutputDelayafterthesample istaken.New dataisavailableateveryclockcycle, butthedatalagstheconversionby thepipelinedelay. POSITIVE FULL SCALE ERROR isthedifferencebetween theactuallastcode transitionand itsidealvalueof 1½ LSB belowpositivefullscale. SIGNAL TO NOISE RATIO (SNR) istheratio,expressedindB,oftherms valueoftheinputsignaltotherms valueofthesum ofallotherspectralcomponents belowone-halfthesamplingfrequency,notincluding harmonicsorDC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Istheratio,expressedindB,oftherms valueof theinputsignaltotherms valueofalloftheotherspectralcomponents belowhalftheclockfrequency, includingharmonicsbutexcludingDC. SPURIOUS FREE DYNAMIC RANGE (SFDR) isthedifference,expressedindB,between therms valuesofthe inputsignaland thepeak spurioussignal,where a spurioussignalisany signalpresentintheoutput spectrumthatisnotpresentattheinput. TOTAL HARMONIC DISTORTION (THD) istheratio,expressedindBc,oftherms totalofthefirstsixharmonic levelsattheoutputtothelevelofthefundamentalattheoutput.THD iscalculatedas: where

  • f1 istheRMS power ofthefundamental(output)frequencyand f2 throughf6 aretheRMS power inthe first6 harmonicfrequencies. (2) Second Harmonic Distortion(2nd Harm) isthedifferenceexpressedindB,between theRMS power inthe inputfrequencyattheoutputand thepower inits2nd harmoniclevelattheoutput. ThirdHarmonic Distortion(3rdHarm) isthedifference,expressedindB,between theRMS power intheinput frequencyattheoutputand thepower inits3rdharmoniclevelattheoutput. Timing Diagram Figure2. Clock and Data Timing Diagram Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com TransferCharacteristics Figure3. Inputvs.Output TransferCharacteristic

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www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,VREF = 1.2V(External),fCLK = 80 MHz, fIN ,39 MHz, 50% DutyCycle. DNL DNL vs.fCLK Figure4. Figure5. DNL vs.Clock Duty Cycle (DC input) DNL vs.Temperature Figure6. Figure7. INL INL vs.fCLK Figure8. Figure9. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,VREF = 1.2V(External),fCLK = 80 MHz, fIN ,39 MHz, 50% DutyCycle. INL vs.Clock Duty Cycle SNR vs.VDDIO Figure10. Figure11. SNR vs.VDDA SNR vs.fCLK Figure12. Figure13. INL vs.Temperature SNR vs.Clock Duty Cycle Figure14. Figure15.

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www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,VREF = 1.2V(External),fCLK = 80 MHz, fIN ,39 MHz, 50% DutyCycle. SNR vs.Temperature THD vs.VDDA Figure16. Figure17. THD vs.VDDIO THD vs.fCLK Figure18. Figure19. SNR vs.IRS THD vs.IRS Figure20. Figure21. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,VREF = 1.2V(External),fCLK = 80 MHz, fIN ,39 MHz, 50% DutyCycle. SINAD vs.VDDA SINAD vs.VDDIO Figure22. Figure23. THD vs.Clock Duty Cycle SINAD vs.Clock Duty Cycle Figure24. Figure25. THD vs.Temperature SINAD vs.Temperature Figure26. Figure27.

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www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,VREF = 1.2V(External),fCLK = 80 MHz, fIN ,39 MHz, 50% DutyCycle. SINAD vs.fCLK SFDR vs.VDDIO Figure28. Figure29. SINAD vs.IRS SFDR vs.fCLK Figure30. Figure31. SFDR vs.VDDA SFDR vs.IRS Figure32. Figure33. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,VREF = 1.2V(External),fCLK = 80 MHz, fIN ,39 MHz, 50% DutyCycle. SFDR vs.Clock Duty Cycle SpectralResponse @ 10 MHz Input Figure34. Figure35. SFDR vs.Temperature SpectralResponse @ 39 MHz Input Figure36. Figure37. Power Consumption vs.fCLK Figure38.

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2.5V Max VCM + 1V VCM VCM - 1V 0V Min 2.5V Max VCM + 0.5V VCM VCM - 0.5V 0V Min ADC10080 www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADC10080 uses a pipelinearchitectureand has errorcorrectioncircuitryto help ensure maximum performance.Differentialanalog inputsignalsare digitizedto 10 bits.In differentialmode each analog input signalshouldhave a peak-to-peakvoltageequalto1.0V,0.75V or 0.5V,dependingon thestateoftheIRS pin (pin5),and be centeredaround VCM and be 180° out of phase witheach other.Ifsingleended operationis desired,VIN-may be tiedtotheVCOM pin(pin4).A singleended inputsignalmay thenbe appliedtoVIN+,and shouldhave a mid range valueof VCOM . The signalamplitudeshouldbe 2.0V,1.5V or 1.0V peak-to-peak, dependingon thestateortheIRS pin(pin5).

APPLICATION INFORMATION

The ADC10080 has two analogsignalinputs,VIN+ and VIN−.These two pinsforma differentialinputpair.There isone common mode pinVCOM thatmay be used tosetthecommon mode inputvoltage. VCOM PIN This pin suppliesa voltageforpossibleuse to set the common mode inputvoltage.This pin may alsobe connectedtoVIN-,so thatVIN+ may be used as a singleended input.Thispinshouldbe bypassed withatleasta 0.1uF capacitor.Do notloadthispin. SIGNAL INPUTS The signalinputsareVIN+ and VIN−.The inputsignalamplitudeisdefinedas VIN+ − VIN− and isrepresentedin Figure39: Figure39. InputVoltageWaveforms fora 2VP-P DifferentialInput A singleended inputsignalisshown inFigure40. Figure40. InputVoltageWaveform fora 2VP-P SingleEnded Input The internalswitchingactionattheanaloginputscauses energytobe outputfromtheinputpins.As thedriving sourcetriestocompensate forthis,itadds noisetothesignal.To preventthis,use 18Ω seriesresistorsateach of the signalinputpinswitha 25 pF capacitoracrossthe inputs,as shown inFigure41. These components shouldbe placedclosetotheADC because theinputpinsoftheADC isthemost sensitivepartofthesystem and thisisthelastopportunitytofiltertheinput.The two 18Ω resistorsand the25 pF capacitorforma low-pass filterwitha -3dB frequencyof177 MHz. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com CLK PIN The CLK signalcontrolsthetimingofthesamplingprocess.Drivetheclockinputwitha stable,low jitterclock signalinthefrequencyrangeindicatedintheAC ElectricalCharacteristicsTablewithriseand falltimesofless than 2 ns.The tracecarryingthe clocksignalshouldbe as shortas possibleand shouldnot crossany other signalline,analogordigital,noteven at90°.The CLK signalalsodrivesan internalstatemachine.IftheCLK is interrupted,or itsfrequencyistoo low,the charge on internalcapacitorscan dissipateto the pointwhere the accuracyoftheoutputdatawilldegrade.Thisiswhat limitsthelowestsample rate.The dutycycleoftheclock signalcan affecttheperformanceofany A/D Converter.Because achievinga precisedutycycleisdifficult,the ADC10080 is designed to maintainperformanceover a range of duty cycles.While itis specifiedand performanceisensuredwitha 50% clockdutycycle,performanceistypicallymaintainedwithminimum clocklow and hightimesindicatedintheAC ElectricalCharacteristicsTable.Bothminimum highand lowtimesmay notbe heldsimultaneously. STBY PIN The STBY pin,when high,holdstheADC10080 ina power-down mode toconservepower when theconverteris notbeingused.The power consumptioninthisstateis15 mW. The outputdatapinsareundefinedinthismode. Power consumptionduringpower-down isnot affectedby the clockfrequency,or by whetherthereisa clock signalpresent.The datainthepipelineiscorruptedwhileinpower down. DF PIN The DF (DataFormat)pin,when high,forcestheADC10080 tooutputthe2’s complement dataformat.When DF istiedlow,theoutputformatisoffsetbinary. IRS PIN The IRS (InputRange Select)pindefinesthe inputsignalamplitudethatwillproduce a fullscaleoutput.The tablebelowdescribesthefunctionoftheIRS pin. Table2. IRS Pin Functions IRS Pin Full-ScaleInput VDDA 2.0VP-P VSSA 1.5VP-P Floating 1.0VP-P OUTPUT PINS The ADC10080 has 10 TTL/CMOS compatibleData Output pins.The offsetbinarydata ispresentat these outputswhiletheDF and STBY pinsare low.Be verycarefulwhen drivinga highcapacitancebus.The more capacitancethe outputdriversmust charge foreach conversion,the more instantaneousdigitalcurrentflows throughVDDIO and VSSIO . These largechargingcurrentspikescan cause on-chipnoiseand coupleintothe analogcircuitry,degradingdynamic performance.Adequate bypassing,limitingoutputcapacitanceand careful attentionto the ground planewillreduce thisproblem.Additionally,bus capacitancebeyond the specified10 pF/pinwillcause tOD toincrease,making itdifficulttoproperlylatchtheADC outputdata.The resultcouldbe an apparentreductionin dynamic performance.To minimizenoise due to outputswitching,minimizethe load currentsat the digitaloutputs.This can be done by minimizingload capacitanceand by connectingbuffers between the ADC outputsand any othercircuitry,which willisolatethe outputsfrom traceand othercircuit capacitancesand limittheoutputcurrents,which couldotherwiseresultinperformancedegradation.Only one driveninputshouldbe connectedtotheADC outputpins.

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www.ti.com SNAS177H –JULY 2003–REVISED MARCH 2013 APPLICATION SCHEMATICS The followingfiguresshow simpleexamples of usingthe ADC10080. Figure41 shows a typicaldifferentially driveninput.Figure42 shows a singleended applicationcircuit. Figure41. A Simple ApplicationUsing a DifferentialDrivingSource Figure42. A Simple ApplicationUsing a SingleEnded DrivingSource Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ADC10080

SNAS177H –JULY 2003–REVISED MARCH 2013 www.ti.com

REVISION HISTORY

Changes from RevisionG (March 2013)toRevisionH Page

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www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADC10080CIMT/NOPB Active Production TSSOP (PW) | 28 48 | TUBE Yes SN Level-3-260C-168 HR -40 to 85 ADC10080 CIMT ADC10080CIMT/NOPB.A Active Production TSSOP (PW) | 28 48 | TUBE Yes SN Level-3-260C-168 HR -40 to 85 ADC10080 CIMT ADC10080CIMTX/NOPB Active Production TSSOP (PW) | 28 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 ADC10080 CIMT ADC10080CIMTX/NOPB.A Active Production TSSOP (PW) | 28 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 ADC10080 CIMT (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10080CIMTX/NOPB TSSOP PW 28 2500 356.0 356.0 36.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADC10080CIMT/NOPB PW TSSOP 28 48 495 8 2514.6 4.06 ADC10080CIMT/NOPB.A PW TSSOP 28 48 495 8 2514.6 4.06 Pack Materials-Page 3

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