ADC10040/ADC10040Q 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter datasheet (Rev. M)

Document overview

  • Manufacturer or author: Texas Instruments, Incorporated [SNAS224,M]
  • PDF pages: 28

Technical content

www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 ADC10040/ADC10040Q10-Bit,40MSPS,3V,55.5mW A/DConverter Check forSamples: ADC10040 1FEATURES DESCRIPTION The ADC10040 is a monolithicCMOS analog-to- 2• Single+3.0V Operation digitalconvertercapableof convertinganalog input• Selectable2.0VP-P,1.5VP-P,or 1.0VP-P full- signalsinto10-bitdigitalwords at 40 Megasamplesscaleinputswing per second (MSPS). This converter uses a

  • 400 MHz −3 dB InputBandwidth differential,pipelinearchitecturewith digitalerror correctionand an on-chipsample-and-holdcircuitto• Low Power Consumption provide a complete conversionsolution,and to• Standby Mode minimize power consumption, while providing
  • On-Chip Referenceand Sample-and-Hold excellentdynamic performance.A unique sample- Amplifier and-holdstageyieldsa full-powerbandwidthof 400 Accommodate 2.5Vand 3.3VLogic Families The differentialinputsprovidea fullscaleselectable• AEC-Q100 Grade 3 Qualified inputswing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, withthe
  • 28-PinTSSOP Package possibilityof a single-endedinput.Fulluse of the differentialinput is recommended for optimum performance.An internal+1.2V precisionbandgapKEY SPECIFICATIONS referenceisused tosettheADC full-scalerange,and• Resolution:10 Bits alsoallowstheusertosupplya bufferedreferenced
  • Conversion Rate:40 MSPS voltagefor those applicationsrequiringincreased accuracy.The outputdata formatisuser choiceof• FullPower Bandwidth: 400 MHz offsetbinaryortwo’s complement.• DNL: ±0.3LSB typ) The ADC10040Q runson an AutomotiveGrade Flow• SNR (fIN = 11 MHz): 59.6dB (typ) and isAEC-Q100 Grade 3 Qualified.• SFDR (fIN = 11 MHz): -80dB (typ) This device is availablein the 28-lead TSSOP• Power Consumption, 40 MHz: 55.5mW package and will operate over the industrial temperaturerangeof−40°C to+85°C.APPLICATIONS
  • Ultrasoundand Imaging
  • Instrumentation
  • CellularBase Stations/Communications Receivers
  • Sonar/Radar
  • xDSL
  • WirelessLocalLoops
  • Data AcquisitionSystems
  • DSP FrontEnds Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2003–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com Connection Diagram Figure1. TSSOP Package See Package Number PW0028A Block Diagram

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www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 Pin Descriptionsand EquivalentCircuits Pin No. Symbol EquivalentCircuit Description ANALOG I/O Invertinganaloginputsignal.Witha 1.2Vreferencethefull-scale

12 VIN

− inputsignallevelisa differential1.0VP-P.Thispinmay be tiedto VCOM (pin4)forsingle-endedoperation. Non-invertinganaloginputsignal.Witha 1.2Vreferencethefull-13 VIN scaleinputsignallevelisa differential1.0VP-P. ReferenceVoltage.Thisdeviceprovidesan internal1.2Vreference. externalreferenceifdesired.Do notloadthispin. 7 VREFT These pinsarehighimpedance referencebypasspinsonly.Connect a 0.1µF capacitorfromeach ofthesepinstoVSSA .These pins4 VCOM shouldnotbe loaded.VCOM may be used tosettheinputcommon mode voltageVCM .8 VREFB DIGITAL I/O Digitalclockinput.The rangeoffrequenciesforthisinputis20 MHz1 CLK to40 MHz. The inputissampled on therisingedge ofthisinput. DF = “1”Two ’s Complement15 DF DF = “0”OffsetBinary Thisisthestandbypin.When high,thispinsetstheconverterinto28 STBY standbymode. When thispinislow,theconverterisinactivemode. IRS = “VDDA ”2.0VP-P inputrange IRS = “VSSA ”1.5VP-P inputrangeIRS (InputRange5 IRS = “Floating”1.0VP-P inputrangeSelect) IfusingbothVIN+ and VIN-pins,(ordifferentialmode),thenthe peak-to-peakvoltagereferstothedifferentialvoltage(VIN+ -VIN-). Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC10040

SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com Pin Descriptionsand EquivalentCircuits(continued) Pin No. Symbol EquivalentCircuit Description 16–20, Digitaloutputdata.D0 istheLSB and D9 istheMSB ofthebinaryD0 –D923–27 outputword. ANALOG POWER Positiveanalogsupplypins.These pinsshouldbe connectedtoa quiet3,0Vsourceand bypassedtoanaloggroundwitha 0.1µF2,9,10 VDDA monolithiccapacitorlocatedwithin1 cm ofthesepins.A 4.7µF capacitorshouldalsobe used inparallel. 3,11,14 VSSA Ground returnfortheanalogsupply. DIGITAL POWER PositivedigitalsupplypinsfortheADC10040 ’s outputdrivers.This pinshouldbe bypassedtodigitalgroundwitha 0.1µF monolithic 22 VDDIO capacitorlocatedwithin1 cm ofthispin.A 4.7µF capacitorshould alsobe used inparallel.The voltageon thispinshouldneverexceed thevoltageon VDDA by more than300 mV. The groundreturnforthedigitalsupplyfortheoutputdrivers.This

21 VSSIO pinshouldbe connectedtothegroundplane,butnotnearthe

analogcircuitry. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 AbsoluteMaximum Ratings(1)(2)(3) VDDA ,VDDIO 3.9V Voltageon Any PintoGND −0.3VtoVDDA orVDDIO +0.3V InputCurrenton Any Pin ±25 mA Package InputCurrent(4) ±50 mA Package DissipationatT = 25°C See (5) ESD Susceptibility Human Body Model(6) 2500V Machine Model(6) 250V SolderingTemperatureInfrared,10 sec.(7) 235°C StorageTemperature −65°C to+150°C (1) Allvoltagesaremeasured withrespecttoGND = VSSA = VSSIO = 0V,unlessotherwisespecified. (2) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (4) When thevoltageatany pinexceedsthepower supplies(VIN < VSSA orVIN > VDDA ),thecurrentatthatpinshouldbe limitedto25 mA. The 50 mA maximum package inputcurrentratinglimitsthenumber ofpinsthatcan safelyexceed thepower supplieswithan input currentof25 mA totwo. (5) The absolutemaximum junctiontemperature(TJmax) forthisdeviceis150°C. The maximum allowablepower dissipationisdictatedby TJmax, thejunction-to-ambientthermalresistance(θJA),and theambienttemperature(TA),and can be calculatedusingtheformula PD MAX = (TJmax − TA)/θJA.Inthe28-pinTSSOP, θJA is96°C/W, so PD MAX = 1,302mW at25°C and 677 mW atthemaximum operatingambienttemperatureof85°C. Note thatthepower dissipationofthisdeviceundernormaloperationwilltypicallybe about55.5 mW. The valuesformaximum power dissipationlistedabove willbe reachedonlywhen theADC10040 isoperatedina severefault condition. (6) Human body model is100 pF capacitordischargedthrougha 1.5kΩ resistor.Machine model is220 pF dischargedthrough0Ω. (7) The 235°C reflowtemperaturereferstoinfraredreflow.ForVapor Phase Reflow(VPR) thefollowingconditionsapply:Maintainthe temperatureatthetopofthepackage body above 183°C fora minimum of60 seconds.The temperaturemeasured on thepackage body must notexceed 220°C. Onlyone excursionabove 183°C isallowedperreflowcycle. OperatingRatings(1)(2) OperatingTemperatureRange −40°C ≤ TA ≤ +85°C VDDA (SupplyVoltage) +2.7V to+3.6V VDDIO (OutputDriverSupplyVoltage) +2.5V toVDDA VREF 1.20V |VSSA –VSSIO | ≤ 100 mV ClockDutyCycle 30 to70 % (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notensurespecificperformancelimits.Forensuredspecificationsand testconditions,see the ElectricalCharacteristics.The ensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmay degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND = VSSA = VSSIO = 0V,unlessotherwisespecified. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC10040

SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com ConverterElectricalCharacteristics Unlessotherwisespecified,thefollowingspecificationsapplyforVSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,ExternalVREF = 1.20V,fCLK = 40 MHz, 50% DutyCycle,C L = 10 pF/pin.BoldfacelimitsapplyforTA = TMIN to TMAX :allotherlimitsTA = 25°C. (1)(2)(3) Symbol Parameter Conditions Min Typ Max Units STATIC CONVERTER CHARACTERISTICS No MissingCodes Ensured 10 Bits FIN = 250 kHz,−0 dB FullINL IntegralNon-Linearity −1.0 ±0.3 +1.0 LSBScale FIN = 250 kHz,−0 dB FullDNL DifferentialNon-Linearity −0.9 ±0.3 +0.9 LSBScale PositiveError −1.5 +0.4 +1.9 % FS GE Gain Error NegativeError −1.5 −0.01 +1.9 % FS OE OffsetError(VIN+ = VIN−) −1.4 0.12 +1.6 % FS Under Range OutputCode 0 Over Range OutputCode 1023 FPBW FullPower Bandwidth(4) 400 MHz REFERENCE AND INPUT CHARACTERISTICS VCM Common Mode InputVoltage 0.5 1.5 V OutputVoltageforuse as an inputVCOM 1.45 Vcommon mode voltage(5) VREF ReferenceVoltage 1.2 V VREFTC ReferenceVoltageTemperature ±80 ppm/°CCoefficient C IN VIN InputCapacitance(eachpinto 4 pFVSSA ) POWER SUPPLY CHARACTERISTICS STBY = 1 4.5 6.0 mA IVDDA AnalogSupplyCurrent STBY = 0 18 25 mA STBY = 1,fIN = 0 Hz 0 mA IVDDIO DigitalSupplyCurrent(6) STBY = 0,fIN = 0 Hz 0.6 0.8 mA STBY = 1 13.5 18 mW PWR Power Consumption(7) STBY = 0 55.5 77 mW (1) To ensureaccuracy,itisrequiredthat|VDDA –VDDIO |≤ 100 mV and separatebypasscapacitorsareused ateach power supplypin. (2) Withthetestconditionfor2 VP-P differentialinput,the10-bitLSB is1.95mV. (3) TypicalfiguresareatTA = TJ = 25°C and representmost likelyparametricnorms.TestlimitsareensuredtoTI's AOQL (Average OutgoingQualityLevel). (4) The inputbandwidthislimitedusinga capacitorbetween VIN − and VIN (5) VCOM isa typicalvalue,measured atroom temperature.Itisnotensuredby test.Do notloadthispin. (6) VDDIO isthecurrentconsumed by theswitchingoftheoutputdriversand isprimarilydeterminedby loadcapacitanceon theoutputpins, thesupplyvoltage,VDR ,and therateatwhichtheoutputsareswitching(whichissignaldependent).IDR = VDR x (C0 x f0 + C 1 x f1 + C 2 + f2 +....C11 x f11)where VDR istheoutputdriversupplyvoltage,C n isthetotalloadcapacitanceon theoutputpin,and fn istheaverage frequencyatwhichthepinistoggling. (7) Power consumptionincludesoutputdriverpower.(fIN = 0 MHz).

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www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 DC and Logic ElectricalCharacteristics Unlessotherwisespecified,thefollowingspecificationsapplyforVSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,ExternalVREF = 1.20V,fCLK = 40 MHz, 50% DutyCycle,C L = 10 pF/pin.BoldfacelimitsapplyforTA = TMIN to TMAX :allotherlimitsTA = 25°C (1)(2)(3) Symbol Parameter Conditions Min Typ Max Units CLK, DF, STBY, SENSE Logical“1”InputVoltage 2 V Logical“0”InputVoltage 0.8 V Logical“1”InputCurrent +10 µA Logical“0”InputCurrent −10 µA D0 –D9 OUTPUT CHARACTERISTICS Logical“1”OutputVoltage IOUT = −0.5mA VDDIO − 0.2 V Logical“0”OutputVoltage IOUT = 1.6mA 0.4 V DYNAMIC CONVERTER CHARACTERISTICS (4) 9.4, 9.6 BitsfIN = 11 MHz 9.3 ENOB EffectiveNumber ofBits 9.4, 9.6 BitsfIN = 19 MHz 9.3 58.7, 59.6 dBfIN = 11 MHz 58.1 SNR Signal-to-NoiseRatio 58.6, 59.5 dBfIN = 19 MHz 58 58.6, dBfIN = 11 MHz 59.558 SINAD Signal-to-NoiseRatio+ Distortion 58.5, dBfIN = 19 MHz 59.457.8 −75.9,fIN = 11 MHz −89 dBc−74.7 2nd HD 2nd Harmonic −74.4,fIN = 19 MHz −86 dBc−73 −69.5,fIN = 11 MHz −78 dBc−67.5 3rdHD 3rdHarmonic −68.8,fIN = 19 MHz −77 dBc−66.7 −75.8,fIN = 11 MHz −80 dBc−74.5SpuriousFreeDynamic RangeSFDR (Excluding2nd and 3rdHarmonic) −75.7,fIN = 19 MHz −80 dBc−74.3 (1) To ensureaccuracy,itisrequiredthat|VDDA –VDDIO |≤ 100 mV and separatebypasscapacitorsareused ateach power supplypin. (2) Withthetestconditionfor2 VP-P differentialinput,the10-bitLSB is1.95mV. (3) TypicalfiguresareatTA = TJ = 25°C and representmost likelyparametricnorms.TestlimitsareensuredtoTI's AOQL (Average OutgoingQualityLevel). (4) Optimum dynamicperformancewillbe obtainedby keepingthereferenceinputinthe+1.2V. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC10040

SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com AC ElectricalCharacteristics Unlessotherwisespecified,thefollowingspecificationsapplyforVSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P (fullscale),STBY = 0V,ExternalVREF = 1.20V,fCLK = 40 MHz, 50% DutyCycle,C L = 10 pF/pin.BoldfacelimitsapplyforTA = TMIN toTMAX :allotherlimitsTA = 25°C (1)(2)(3) Symbol Parameter Conditions Min(3) Typ (3) Max (3) Units CLK, DF, STBY, SENSE fCLK 1 Maximum ClockFrequency 40 MHz (min) fCLK 2 Minimum ClockFrequency 20 MHz tCH ClockHighTime 12.5 ns tCL ClockLow Time 12.5 ns tCONV ConversionLatency 6 Cycles T = 25°C 2 3.3 5 nsData OutputDelayaftera RisingClocktOD Edge 1 6 ns tAD ApertureDelay 1 ns tAJ ApertureJitter 2 ps (RMS) DifferentialVIN stepfrom±3V Over Range RecoveryTime to0V togetaccurate 1 ClockCycle conversion tSTBY StandbyMode ExitCycle 20 Cycles (1) Withthetestconditionfor2 VP-P differentialinput,the10-bitLSB is1.95mV. (2) TypicalfiguresareatTA = TJ = 25°C and representmost likelyparametricnorms.TestlimitsareensuredtoTI's AOQL (Average OutgoingQualityLevel). (3) TimingspecificationsaretestedatTTL logiclevels,VIL= 0.4Vfora fallingedge,and VIH = 2.4Vfora risingedge.

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www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 SpecificationDefinitions APERTURE DELAY isthetimeaftertherisingedge oftheclocktowhen theinputsignalisacquiredorheldfor conversion. APERTURE JITTER (APERTURE UNCERTAINTY) isthe variationinaperturedelayfrom sample to sample. Aperturejittermanifestsitselfas noiseintheoutput. COMMON MODE VOLTAGE (VCM )isthed.c.potentialpresentatbothsignalinputstotheADC. CONVERSION LATENCY See PIPELINE DELAY. DIFFERENTIAL NON-LINEARITY (DNL) isthemeasure ofthemaximum deviationfromtheidealstepsizeof1 LSB. DUTY CYCLE istheratioofthetimethata repetitivedigitalwaveform ishightothetotaltimeofone period.The specificationherereferstotheADC clockinputsignal. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) isanothermethod ofspecifyingSignal-to-Noise and DistortionorSINAD. ENOB isdefinedas (SINAD -1.76)/6.02and statesthattheconverterisequivalentto a perfectADC ofthis(ENOB) number ofbits. FULL POWER BANDWIDTH isa measure of the frequencyat which the reconstructedoutputfundamental drops3 dB belowitslowfrequencyvaluefora fullscaleinput. GAIN ERROR isthedeviationfromtheidealslopeofthetransferfunction.Itcan be calculatedas: Gain Error= Pos.Full-ScaleError− Neg. Full-ScaleError (1) INTEGRAL NON LINEARITY (INL)isa measure ofthedeviationofeach individualcode froma linedrawn from negativefullscalethroughpositivefullscale.The deviationofany givencode fromthisstraightlineismeasured fromthecenterofthatcode value. MISSING CODES arethoseoutputcodes thatwillneverappearattheADC outputs.The ADC10040 isensured nottohave any missingcodes. NEGATIVE FULL SCALE ERROR is the differencebetween the inputvoltage(VIN + − VIN −) justcausinga transitionfromnegativefullscaletothefirstcode and itsidealvalueof0.5LSB. OFFSET ERROR istheinputvoltagethatwillcause a transitionfrom a code of01 1111 1111 toa code of10 0000 0000. OUTPUT DELAY isthetimedelayaftertherisingedge oftheclockbeforethedataupdateispresentedatthe outputpins. PIPELINE DELAY (LATENCY) isthenumber ofclockcyclesbetween initiationofconversionand when thatdata ispresentedto the outputdriverstage.Data forany givensample isavailableat the outputpinsthe Pipeline Delay plustheOutputDelay afterthesample istaken.New dataisavailableateveryclockcycle,butthedata lagstheconversionby thepipelinedelay. POSITIVE FULL SCALE ERROR isthedifferencebetween theactuallastcode transitionand itsidealvalueof 1½ LSB belowpositivefullscale. SIGNAL TO NOISE RATIO (SNR) istheratio,expressedindB, oftherms valueoftheinputsignaltotherms value of the sum of allotherspectralcomponents below one-halfthe sampling frequency,not including harmonicsorDC. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Istheratio,expressedindB,oftherms valueofthe inputsignaltotherms valueofalloftheotherspectralcomponents below halftheclockfrequency,including harmonicsbutexcludingd.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) isthedifference,expressedindB, between therms valuesofthe inputsignaland thepeak spurioussignal,where a spurioussignalisany signalpresentintheoutputspectrum thatisnotpresentattheinput. Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC10040

SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com TOTAL HARMONIC DISTORTION (THD) istheratio,expressedindBc,oftherms totalofthefirstsixharmonic levelsattheoutputtothelevelofthefundamentalattheoutput.THD iscalculatedas: (2) where f1 istheRMS power ofthefundamental(output)frequencyand f2 throughf6 aretheRMS power inthefirst 6 harmonicfrequencies. SECOND HARMONIC DISTORTION (2ND HARM) isthedifferenceexpressedindB,between theRMS power in theinputfrequencyattheoutputand thepower inits2nd harmoniclevelattheoutput. THIRD HARMONIC DISTORTION (3RD HARM) isthedifference,expressedindB, between theRMS power in theinputfrequencyattheoutputand thepower inits3rdharmoniclevelattheoutput. Timing Diagram Figure2. Clock and Data Timing Diagram TransferCharacteristics Figure3. Inputvs.Output TransferCharacteristic

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www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 TypicalPerformance Characteristics Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,ExternalVREF = 1.2V,fCLK = 40 MHz, fIN = 19 MHz, 50% DutyCycle. Figure4.DNL Figure5.DNL vs.fCLK Figure6.DNL vs.Clock Duty Cycle (DC input) Figure7.DNL vs.Temperature Figure8.INL Figure9.INL vs.fCLK Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC10040

SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,ExternalVREF = 1.2V,fCLK = 40 MHz, fIN = 19 MHz, 50% DutyCycle. Figure10.INL vs.Clock Duty Cycle Figure11.SNR vs.VDDIO Figure12.SNR vs.VDDA Figure13.SNR vs.fCLK Figure14.INL vs.Temperature Figure15.SNR vs.Clock Duty Cycle

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www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 TypicalPerformance Characteristics(continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,ExternalVREF = 1.2V,fCLK = 40 MHz, fIN = 19 MHz, 50% DutyCycle. Figure16.SNR vs.Temperature Figure17.THD vs.VDDA Figure18.THD vs.VDDIO Figure19.THD vs.fCLK Figure20.SNR vs.IRS Figure21.THD vs.IRS Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC10040

SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,ExternalVREF = 1.2V,fCLK = 40 MHz, fIN = 19 MHz, 50% DutyCycle. Figure22.SINAD vs.VDDA Figure23.SINAD vs.VDDIO Figure24.THD vs.Clock Duty Cycle Figure25.SINAD vs.Clock Duty Cycle Figure26.THD vs.Temperature Figure27.SINAD vs.Temperature

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www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 TypicalPerformance Characteristics(continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,ExternalVREF = 1.2V,fCLK = 40 MHz, fIN = 19 MHz, 50% DutyCycle. Figure28.SINAD vs.fCLK Figure29.SFDR vs.VDDIO Figure30.SINAD vs.IRS Figure31.SFDR vs.fCLK Figure32.SFDR vs.VDDA Figure33.SFDR vs.IRS Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC10040

SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) Unlessotherwisespecified,thefollowingspecificationsapply:VSSA = VSSIO = 0V,VDDA = +3.0V,VDDIO = +2.5V,VIN = 2 VP-P, STBY = 0V,ExternalVREF = 1.2V,fCLK = 40 MHz, fIN = 19 MHz, 50% DutyCycle. Figure34.SFDR vs.Clock Duty Cycle Figure35.SpectralResponse @ 11 MHz Input Figure36.SFDR vs.Temperature Figure37.SpectralResponse @ 19 MHz Input

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2.5V Max VCM + 0.5V VCM VCM - 0.5V 0V Min ADC10040 www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The ADC10040 uses a pipelinearchitectureand has errorcorrectioncircuitryto help ensure maximum performance.Differentialanaloginputsignalsare digitizedto 10 bits.In differentialmode , each analoginput signalshouldhave a peak-to-peakvoltageequalto1.0V,0.75V or 0.5V,dependingon thestateoftheIRS pin (pin5),and be centeredaround VCM and be 180° out of phase witheach other.Ifsingleended operationis desired,VIN-may be tiedtotheVCOM pin(pin4).A singleended inputsignalmay thenbe appliedtoVIN+,and shouldhave an averagevalueintherangeofVCM .The signalamplitudeshouldbe 2.0V,1.5V or1.0V peak-to- peak,dependingon thestateortheIRS pin(pin5). APPLICATIONS INFORMATION ANALOG INPUTS The ADC10040 has two analogsignalinputs,VIN+ and VIN−.These two pinsforma differentialinputpair.There isone common mode pinVCOM thatmay be used tosetthecommon mode inputvoltage. REFERENCE PINS The ADC10040 isdesignedtooperatewithan internalorexternal1.2V reference.The internal1.2V referenceis thedefualtcondition.Ifan externalvoltageisappliedtotheVREF pin,thenthatvoltageisused forthereference. The VREF pinshouldbe bypassed togroundwitha 0.1µF capacitorplacedclosetothepin.Do notloadthispin when usingtheinternalreference. The voltagesatVCOM ,VREFT ,and VREFB arederivedfromthereferencevoltage.These pinsaremade available forbypass purposesonly.These pinsshouldeach be bypassed togroundwitha 0.1µF capacitorplacedclose tothepin.Itisveryimportantthatallgroundsassociatedwiththereferencevoltageand theinputsignalmake connectiontotheanalogground planeata singlepointtominimizetheeffectsofnoisecurrentsintheground path.DO NOT LOAD thesepins. VCOM PIN This pin suppliesa voltageforpossibleuse to set the common mode inputvoltage.This pin may alsobe connectedtoVIN-,so thatVIN+ may be used as a singleended input.These pinsshouldbe bypassed withat leasta 0.1uFcapacitor.Do notloadthispin. SIGNAL INPUTS The signalinputsare VIN+ and VIN−. The inputsignalamplitudeisdefinedas VIN+ − VIN− and isrepresented schematicallyinFigure38: Figure38. InputVoltageWaveforms fora 2VP-P differentialInput Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADC10040

2.5V Max VCM + 1V VCM VCM - 1V 0V Min ADC10040 SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com Figure39. InputVoltageWaveform fora 2VP-P SingleEnded Input A singleended inputsignalisshown inFigure39. The internalswitchingactionattheanaloginputscauses energytobe outputfromtheinputpins.As thedriving sourcetriestocompensate forthis,itadds noisetothesignal.To minimizetheeffectsofthis,use 18Ω series resistorsat each of the signalinputswitha 25 pF capacitoracrossthe inputs,as shown inFigure40. These components shouldbe placedclosetotheADC because theinputpinsoftheADC isthemost sensitivepartof the system and thisisthe lastopportunityto filterthe input.The two 16Ω resistorsand the 24 pF capacitor, togetherwiththe4 pF ADC inputcapacitance,forma low-passfilterwitha -3dB frequencyof177 MHz. CLK PIN The CLK signalcontrolsthetimingofthesamplingprocess.Drivetheclockinputwitha stable,low jitterclock signalinthefrequencyrangeindicatedintheAC ElectricalCharacteristicsTablewithriseand falltimesofless than 2 ns.The tracecarryingthe clocksignalshouldbe as shortas possibleand shouldnot crossany other signalline,analogordigital,noteven at90°.The CLK signalalsodrivesan internalstatemachine.IftheCLK is interrupted,or itsfrequencyistoo low,the charge on internalcapacitorscan dissipateto the pointwhere the accuracyoftheoutputdatawilldegrade.Thisiswhat limitsthelowestsample rate.The dutycycleoftheclock signalcan affecttheperformanceofany A/D Converter.Because achievinga precisedutycycleisdifficult,the ADC10040 is designed to maintainperformanceover a range of duty cycles.While itis specifiedand performanceisensuredwitha 50% clockdutycycle,performanceistypicallymaintainedwithminimum clocklow and hightimesindicatedintheAC ElectricalCharacteristicsTable.Bothminimum highand lowtimesmay notbe heldsimultaneously. STBY PIN The STBY pin,when high,holdstheADC10040 ina power-down mode toconservepower when theconverteris not beingused.The power consumptioninthisstateis13.5 mW. The outputdata pinsare undefinedinthis mode. Power consumptionduringpower-down isnotaffectedby theclockfrequency,or by whetherthereisa clocksignalpresent.The datainthepipelineiscorruptedwhileinthepower down. DF PIN The DF (DataFormat)pin,when high,forcestheADC10040 tooutputthe2’s complement dataformat.When DF istiedlow,theoutputformatisoffsetbinary. IRS PIN The IRS (InputRange Select)pindefinesthe inputsignalamplitudethatwillproduce a fullscaleoutput.The tablebelowdescribesthefunctionoftheIRS pin. Table1.IRS Pin Functions IRS Pin Full-ScaleInput VDDA 2.0VP-P VSSA 1.5VP-P Floating 1.0VP-P

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0.1 PF 16: 16: ADC10040 0.1 PF 0.1 PF 0.1 PF VREF VREFT VREFB VIN+ VIN- VCOM CLK 0.1 PF4.7 PF VDDA IRS VDDA VDDA VDDA VSSA VSSA VSSA VSSIO STBY DF VDDA 74ACTQ16244 GND GND GND GND GND GND GND GND CLKIN 0.1 PF 4.7 PF VDDIO VDDIO CLKOUT 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 4Y4 4Y3 4Y2 4Y1 VCC VCC VCC VCC4 OE 4A3 4A2 4A1 3A4 3A3 3A2 3A1 2A4 2A3 2A2 2A1 1A4 1A3 1A2 1A1 3 OE 1 OE 2 OE ADC10040 www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013 OUTPUT PINS The ADC10040 has 10 TTL/CMOS compatibleData Output pins.The offsetbinarydata ispresentat these outputswhiletheDF and STBY pinsare low.Be verycarefulwhen drivinga highcapacitancebus.The more capacitancethe outputdriversmust charge foreach conversion,the more instantaneousdigitalcurrentflows throughVDDIO and VSSIO . These largechargingcurrentspikescan cause on-chipnoiseand coupleintothe analogcircuitry,degradingdynamic performance.Adequate bypassing,limitingoutputcapacitanceand careful attentionto the ground planewillreduce thisproblem.Additionally,bus capacitancebeyond the specified10 pF/pinwillcause tOD toincrease,making itdifficulttoproperlylatchtheADC outputdata.The resultcouldbe an apparentreductionin dynamic performance.To minimizenoise due to outputswitching,minimizethe load currentsat the digitaloutputs.This can be done by minimizingload capacitanceand by connectingbuffers between the ADC outputsand any othercircuitry,which willisolatethe outputsfrom traceand othercircuit capacitancesand limittheoutputcurrents,which couldotherwiseresultinperformancedegradation.Only one driveninputshouldbe connectedtotheADC outputpins. WhilethetOD timeprovidesinformationaboutoutputtiming,a simpleway tocapturea validoutputistolatchthe dataon therisingedge oftheconversionclock. APPLICATION SCHEMATICS The followingfiguresshow simpleexamples of usingthe ADC10040. The ADC10040 performsbest witha differentialinputsignal. Narrow Band A.C.Signals Figure40 shows a typicalcircuitforan AC coupled,differentiallydriveninput.The 16Ω resistorsand 24 pF capacitor,togetherwiththe4 pF inputcapacitanceoftheADC10040, providesa −3dB inputbandwidthof177 MHz, whilethe0.1µF capacitoratVCOM stabilizesthecommon move voltageatthetransformercentertap. Figure40. A Simple ApplicationUsing a DifferentialSignalSource Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ADC10040

0.1 PF 0.1 PF 0.1 PF VREF VREFT VREFB CLK 0.1 PF4.7 PF VDDA IRS VDDA VDDA VDDA VSSA VSSA VSSA VSSIO STBY DF VDDA 74ACTQ16244 GND GND GND GND GND GND GND GND CLKIN 0.1 PF 4.7 PF VDDIO VDDIO CLKOUT 3Y4 3Y3 3Y2 3Y1 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 4Y4 4Y3 4Y2 4Y1 VCC VCC VCC VCC4 OE 4A3 4A2 4A1 3A4 3A3 3A2 3A1 2A4 2A3 2A2 2A1 1A4 1A3 1A2 1A1 3 OE 1 OE 2 OE AIN 51 pF 0.1 PF 16: VIN+ VIN- VCOM LMH6550 R T 16: R T 16: R F R F R G R G 50: 50: ADC Input From ADC VCOM 24 pF VCM ADC10040 SNAS224M –JULY 2003–REVISED APRIL 2013 www.ti.com D.C.Applications For verylow frequencyand DC inputapplications,a d.c.coupledamplifieror buffermay be needed,especially when theinputissingle-endedand theadvantagesofa differentialinputsignalisdesired.Figure41 shows the inputdrivecircuitthatcan be used to replacethe transformerof Figure40. The LMH6550 providesexcellent performanceand iswell-suitedforthisapplication.The common mode outputvoltageof the LMH6550 isthe same as itsVCM input. Figure41. Using theLMH6550 forDC and wideband applications SingleEnded Applications Performanceof the ADC10040 witha single-endedinputisnot as good as itsperformancewitha differential input.However, ifthelowerperformanceisadequate,thecircuitofFigure42 shows an acceptablemethod of drivingtheanaloginput. Figure42. A Simple ApplicationUsing a SingleEnded SignalSource

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www.ti.com SNAS224M –JULY 2003–REVISED APRIL 2013

REVISION HISTORY

Changes from RevisionL (April2013)toRevisionM Page Copyright© 2003–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:ADC10040

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) ADC10040CIMT/NOPB Active Production TSSOP (PW) | 28 48 | TUBE Yes SN Level-3-260C-168 HR -40 to 85 ADC10040 CIMT ADC10040CIMT/NOPB.A Active Production TSSOP (PW) | 28 48 | TUBE Yes SN Level-3-260C-168 HR -40 to 85 ADC10040 CIMT ADC10040CIMTX/NOPB Active Production TSSOP (PW) | 28 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 ADC10040 CIMT ADC10040CIMTX/NOPB.A Active Production TSSOP (PW) | 28 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 ADC10040 CIMT ADC10040QCIMT/NOPB Active Production TSSOP (PW) | 28 48 | TUBE Yes SN Level-3-260C-168 HR -40 to 85 ADC10040 QCIMT ADC10040QCIMT/NOPB.A Active Production TSSOP (PW) | 28 48 | TUBE Yes SN Level-3-260C-168 HR -40 to 85 ADC10040 QCIMT ADC10040QCIMTX/NO.A Active Production TSSOP (PW) | 28 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 ADC10040 QCIMT ADC10040QCIMTX/NOPB Active Production TSSOP (PW) | 28 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 ADC10040 QCIMT (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1

www.ti.com 11-Nov-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADC10040, ADC10040-Q1 :

  • Catalog : ADC10040
  • Automotive : ADC10040-Q1 NOTE: Qualified Version Definitions:
  • Catalog - TI's standard catalog product
  • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC10040CIMTX/NOPB TSSOP PW 28 2500 356.0 356.0 36.0 ADC10040QCIMTX/NOPB TSSOP PW 28 2500 356.0 356.0 36.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) ADC10040CIMT/NOPB PW TSSOP 28 48 495 8 2514.6 4.06 ADC10040CIMT/NOPB.A PW TSSOP 28 48 495 8 2514.6 4.06 ADC10040QCIMT/NOPB PW TSSOP 28 48 495 8 2514.6 4.06 ADC10040QCIMT/NOPB.A PW TSSOP 28 48 495 8 2514.6 4.06 Pack Materials-Page 3

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