AD4001 (Rev. 0)
Document overview
- Manufacturer or author: Provided By digicamel.com
- PDF pages: 33
Technical content
16-Bit, 2 MSPS, Precision SAR, Differential ADC Data Sheet AD4001 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Throughput: 2 MSPS maximum INL: ±0.4 LSB maximum Guaranteed 16-bit no missing codes Low power 9.5 mW at 2 MSPS (VDD only) 80 μW at 10 kSPS 16 mW at 2 MSPS (total) SNR 96.2 dB typical at 1 kHz 95.5 dB typical at 100 kHz THD −123 dB typical at 1 kHz −99 dB typical at 100 kHz Ease of use features reduce system power and complexity Input overvoltage clamp circuit Reduced nonlinear input charge kickback High-Z mode Long acquisition phase Input span compression Fast conversion time allows low SPI clock rates SPI-programmable modes, read/write capability, status word Differential analog input range: ±V REF 0 V to VREF with VREF between 2.4 V to 5.1 V Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface SAR architecture: no latency/pipeline delay Guaranteed operation: −40°C to 125°C Serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible Ability to daisy-chain multiple ADCs and busy indicator 10-lead, 3 mm × 3 mm LFCSP and 10-lead, 3 mm × 4.90 mm MSOP
APPLICATIONS
Precision data acquisition systems GENERAL DESCRIPTION The AD4001 is a low noise, low power, high speed, 16-bit, 2 MSPS, precision successive approximation register (SAR) analog-to- digital converter (ADC). It incorporates ease of use features that lower the signal chain power, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive this ADC directly, while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface (SPI) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. Operating from a 1.8 V supply, the AD4001 has a ±V REF fully differential input range with VREF ranging from 2.4 V to 5.1 V . The AD4001 consumes only 16 mW at 2 MSPS with a minimum SCK rate of 70 MHz in turbo mode and achieves ±0.4 LSB integral nonlinearity error (INL) maximum, guaranteed no missing codes at 16 bits with 96.2 dB typical signal-to-noise ratio (SNR). The reference voltage is applied externally and can be set independently of the supply voltage. The SPI-compatible, versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. The AD4001 is compatible with 1.8 V , 2.5 V , 3 V , and 5 V logic, using the separate VIO supply. The AD4001 is available in a 10-lead MSOP or a 10-lead LFCSP with operation specified from −40°C to +125°C. The device is pin compatible with the AD4003 18-bit, 2 MSPS, precision SAR differential ADC. FUNCTIONAL BLOCK DIAGRAM GND IN+ IN– SDI SCK SDO CNV AD4001 16-BIT SAR ADC SERIAL INTERFACE VIO REF VDD VREF VREF VREF/2 VREF/2 HIGH-Z MODE CLAMP SPAN COMPRESSION TURBO MODE STATUS BITS 2.5V TO 5V 1.8V10µF 1.8V TO 5V 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 15368-001 Figure 1.
Rev. 0 | Page 2 of 33 TABLE OF CONTENTS
REVISION HISTORY
1/2017—Revision 0: Initial Version
Rev. 0 | Page 3 of 33 SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled (fS = 2 MSPS), unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIN+ − VIN− −VREF +VREF V Span compression enabled −VREF × 0.8 +VREF × 0.8 V Operating Input Voltage VIN+, VIN− to GND −0.1 VREF + 0.1 V Span compression enabled 0.1 × VREF 0.9 × VREF V Common-Mode Input Range VREF/2 − 0.125 VREF/2 VREF/2 + 0.125 V Common-Mode Rejection Ratio (CMRR) fIN = 500 kHz 68 dB Analog Input Current Acquisition phase, T = 25°C 0.3 nA High-Z mode enabled, converting dc input at 2 MSPS 1 µA THROUGHPUT Complete Cycle 500 ns Conversion Time 290 320 ns Acquisition Phase1 290 ns Throughput Rate2 0 2 MSPS Transient Response3 250 ns DC ACCURACY No Missing Codes 16 Bits Integral Nonlinearity Error (INL) −0.4 ±0.2 +0.4 LSB Differential Nonlinearity Error (DNL) −0.5 ±0.2 +0.5 LSB Transition Noise 0.35 LSB Zero Error −1.5 ±0.1 +1.5 LSB Zero Error Drift4 −0.28 +0.28 ppm/°C Gain Error −16.5 ±0.4 +16.5 LSB Gain Error Drift4 −0.23 +0.23 ppm/°C Power Supply Sensitivity VDD = 1.8 V ± 5% 0.25 LSB 1/f Noise5 Bandwidth = 0.1 Hz to 10 Hz 6 µV p-p AC ACCURACY Dynamic Range 96.3 dB Total RMS Noise 54 µV rms fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) 95.6 96.2 dB Spurious-Free Dynamic Range (SFDR) 122 dB Total Harmonic Distortion (THD) −123 dB Signal-to-Noise-and-Distortion Ratio (SINAD) 95.5 96 dB Oversampled Dynamic Range Oversampling ratio (OSR) = 256, VREF = 5 V 120 dB fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR 92.1 93.2 dB SFDR 118 dB THD −117 dB SINAD 92 93 dB
Rev. 0 | Page 4 of 33 Parameter Test Conditions/Comments Min Typ Max Unit fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR 95.5 dB THD −99 dB SINAD 93.8 dB fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR 91 dB THD −92 dB SINAD 89 dB −3 dB Input Bandwidth 10 MHz Aperture Delay 1 ns Aperture Jitter 1 ps rms REFERENCE Voltage Range (VREF) 2.4 5.1 V Current 2 MSPS, VREF = 5 V 1.1 mA OVERVOLTAGE CLAMP IIN+/IIN− VREF = 5 V 50 mA VREF = 2.5 V 50 mA VIN+/VIN− at Maximum IIN+/IIN− VREF = 5 V 5.4 V VREF = 2.5 V 3.1 V VIN+/VIN− Clamp On/Off Threshold VREF = 5 V 5.25 5.4 V VREF = 2.5 V 2.68 2.8 V Deactivation Time 360 ns REF Current at Maximum IIN+/IIN− VIN+/VIN− > VREF 100 µA DIGITAL INPUTS Logic Levels Input Low Voltage, VIL VIO > 2.7 V −0.3 +0.3 × VIO V VIO ≤ 2.7 V −0.3 +0.2 × VIO V Input High Voltage, VIH VIO > 2.7 V 0.7 × VIO VIO + 0.3 V VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V Input Low Current, IIL −1 +1 µA Input High Current, IIH −1 +1 µA Input Pin Capacitance 6 pF DIGITAL OUTPUTS Data Format Serial 16 bits, twos complement Pipeline Delay Conversion results available immediately after completed conversion Output Low Voltage, VOL ISINK = 500 µA 0.4 V Output High Voltage, VOH ISOURCE = −500 µA VIO − 0.3 V POWER SUPPLIES VDD 1.71 1.8 1.89 V VIO 1.71 5.5 V Standby Current VDD = 1.8 V, VIO = 1.8 V, T = 25°C 1.6 µA Power Dissipation VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 80 µW
1 MSPS, high-Z mode disabled 8 mW
2 MSPS, high-Z mode disabled 16 18.5 mW
1 MSPS, high-Z mode enabled 10 mW
2 MSPS, high-Z mode enabled 20 24.5 mW VDD Only 2 MSPS, high-Z mode disabled 9.5 mW REF Only 2 MSPS, high-Z mode disabled 5.5 mW VIO Only 2 MSPS, high-Z mode disabled 1.0 mW Energy per Conversion 8 nJ/sample
1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, not production tested. 5 See the 1/f noise plot in Figure 18. disabled, and turbo mode enabled (fS = 2 MSPS), unless otherwise noted. See Figure 2 for the timing voltage levels. Table 2. Digital Interface Timing 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. 4 A 50% duty cycle is assumed for SCK. 5 See Figure 22 for SINAD vs. tQUIET2. Figure 2. Voltage Levels for Timing
Table 3. Register Read/Write Timing 1 For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation
1 See the Analog Inputs section for an explanation of IN+ and IN−. PCB thermal design is required. Table 6. Thermal Resistance
1 Test Condition 1: thermal impedance simulated values are based upon use
of 2S2P JEDEC PCB. See the Ordering Guide.
Figure 3. 10-Lead MSOP Pin Configuration
10 VIO
- CONNECT THE EXPOSED PAD TO GND.
MEET THE SPECIFIED PERFORMANCE. Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions decoupled closely to the GND pin with a 10 μF, X7R ceramic capacitor. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the device is select ed, the conversion result is shifted out by this clock. level on SDI is output on SDO with a delay of 16 SCK cycles. SDI on the rising edge of SCK. 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. 1 AI is analog input, P is power, DI is digital input, and DO is digital output.
Rev. 0 | Page 13 of 33 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 30). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V , from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINAD dB − 1.76)/6.02 ENOB is expressed in bits. Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Noise Free Code Resolution = log 2(2N/Peak-to-Peak Noise) Noise free code resolution is expressed in bits. Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) Effective resolution is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of IN+ and IN− at the frequency, f. CMRR (dB) = 10log(P ADC_IN/PADC_OUT) where: PADC_IN is the common-mode power at the frequency, f, applied to the IN+ and IN− inputs. PADC_OUT is the power at the frequency, f, in the ADC output. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply at the frequency, f. PSRR (dB) = 10 log(P VDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output.
Figure 29. ADC Simplified Schematic 16-bit ADC based on a SAR architecture. first conversion after being powered down for long periods. making it ideal for multiplexed applications. features that result in a lower system power and footprint. device from overvoltage damage on the analog inputs. charge kickback seen from a typical switched capacitor SAR input. load for the amplifier, improving stability and power dissipation. multiplexing, disable high-Z mode. amplifier to access the full range of the ADC. The AD4001 can interface to any 1.8 V to 5 V digital logic family. allows space savings and flexible configurations. 18-bit precision SAR ADCs listed in Table 8. Table 8. MSOP and LFCSP 14-/16-/18-Bit Precision SAR ADCs
181 AD7989-12 AD76912 AD7690,2
161 AD7684 AD7687 AD7688,2
163 AD7680,
143 AD7940 AD7942 2 AD79462 Not applicable
that are connected to the comparator inputs. analog signal on the IN+ and IN− inputs.
frequencies above 100 kHz or multiplexing. Figure 40. Input Current vs. Input Differential Voltage, (THD) performance over a frequency range of up to 100 kHz. switched capacitor SAR ADC inputs. source impedances with high-Z mode disabled and enabled. Figure 41. THD vs. Input Frequency for Various Source Impedance, VREF = 5 V
2 MSPS for high-Z mode enabled and disabled with various RC
lower than using dedicated ADC drivers like the ADA4807-1. Figure 42. SNR vs. RC Filter Bandwidth for Various Precision ADC Drivers,
simultaneous sampling applications. together, daisy-chain mode is always selected. is low when the ADC conversion ends. depending on the states of CNV and SDI, as shown in in Table 11. Table 11. State of SDO on Power-Up register and replaces the busy indicator feature when enabled. turbo mode enabled and a minimum SCK rate of 70 MHz. data if the status bits are enabled in the configuration register. There are six status bits in total, as described in Table 12. of 70 MHz and allows the AD4001 to run at 2 MSPS. Table 14. The overvoltage clamp flag is a read only sticky bit, overvoltage condition when it is set to 0. Table 12. Register Bits or a read. The AD4001 command register is shown in Table 13. Table 13. Command Register mode is enabled, SDO goes low on the rising edge of CNV . Register reads are not allowed in daisy-chain mode. Register write requires three signal lines: SCK, CNV , and SDI. on SDO; however, the register write occurs regardless. register read, write, and daisy-chain mode. Table 14. Register Map
Table 15. The status bits must be enabled in the register setting. including status bits, is shown in Figure 49. Table 15. Status Bits (Default Conditions) Figure 49. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High)
0.50 BSC
1.10 MAX
Figure 66. 10-Lead Mini Small Outline Package [MSOP]
0.20 REF
0.05 MAX
0.02 NOM
0.20 MIN
Figure 67. 10-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the prop erty of their respective owners.