A8905CLB

8905 ALLEGRO

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Technical content

— FOR REFERENCE ONL Y Always order by complete part number, e.g., A8905CLB . The A8905CLB isw a three-phase brushless dc motor controller/ driver for use with CD-ROM or DVD drives. The three half-bridge outputs are low on-resistance n-channel DMOS devices capable of driving up to 1.25 A. The A8905CLB provides complete, reliable, self-contained back-EMF sensing motor startup and running algorithms. A programmable digital frequency-locked loop speed control circuit together with the linear current control circuitry provides precise motor speed regulation. A serial port allows the user to program various features and modes of operation, such as the speed control parameters, startup current limit, sleep mode, diagnostic modes, and others.

APPLICATIONS

FEATURES

I Low rDS(on) I Startup Commutation Circuitry I Back-EMF Commutation Circuitry I Serial Port Interface I Frequency-Locked Loop Speed Control I Tachometer Signal Input I Programmable Start-Up Current I Diagnostics Mode I Sleep Mode I Linear Current Control I Internal Current Sensing I Dynamic Braking Through Serial Port I Power-Down Dynamic Braking I System Diagnostics Data Out I Data Out Ported in Real Time I Internal Thermal Shutdown Circuitry 1312 BRAKE FILTER DATA IN LOGIC SUPPLY GROUND CHIP SELECT CLOCK RESET GROUND GROUND GROUND DDV CST OUT A OUT B OUT C C D1 Dwg. PP-040-1 BBVLOAD SUPPLY C WD C D2 DATA OUT INDEX CENTERTAP OSCILLATOR C RES SERIAL PORT FLL MUX COMMUTATION DELAY BOOST CHARGE PUMP Data Sheet 26301.3 8905 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING ABSOLUTE MAXIMUM RATINGS at TA = +25°C Logic Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Junction Temperature, TJ . . . +150°C† Storage Temperature Range, † Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. Output current rating may be restricted to a value determined by system concerns and factors. These include: system duty cycle and timing, ambient temperature, and use of any heatsinking and/or forced cooling. For reliable operation, the specified maximum junction temperature should not be exceeded.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 50 75 100 125 150 2.5 1.5 1.0 0.5 TEMPERATURE in °C 2.0 Dwg. GP-019B R = 6°C/W θJT R = 55°C/W θJA ALLOWABLE PACKAGE POWER DISSIPATION in WATTS FUNCTIONAL BLOCK DIAGRAM CURRENT CONTROL Dwg. FP-034-1 2221 1720 CENTERTAP 10 C WD 3 OSC 16 INDEX 14 FILTER C ST C RES BRAKE OUT A OUT B OUT C COMMUTATION LOGIC COMMUTATION DELAY C D1 C D2 24 2 WATCHDOG TIMER SEQUENCE LOGIC BLANK FCOM OUT A5 OUT B8 OUT C9

1 LOAD

OSC. BOOST CHARGE PUMPBRAKE 18-19 6-7 GROUND GROUND Copyright © 1998 Allegro MicroSystems, Inc.

ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Logic Supply Voltage V DD Operating 4.5 5.0 5.5 V Logic Supply Current I DD Operating — 7.5 10 mA Sleep Mode — — 1.5 mA Load Supply Voltage V BB Operating 4.5 — 14 V Thermal Shutdown T J — 165 — °C Thermal Shutdown Hys. ∆TJ —2 0— °C Output Drivers Output Leakage Current I DSX VBB = 14 V, VOUT = 14 V — 1.0 300 µA VBB = 14 V, VOUT = 0 V — -1.0 -300 µA Total Output ON Resistance r DS(on) IOUT = 600 MA — 1.1 1.4 Ω Output Sustaining Voltage V DS(sus) VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH 14 — — V Clamp Diode Forward Voltage V F IF = 1.0 A — 1.25 1.5 V Control Logic Logic Input Voltage V IN(0) INDEX, RESET, CLK, -0.3 — 1.5 V VIN(1) CHIP SELECT, OSC, BRAKE 3.5 — 5.3 V Logic Input Current I IN(0) VIN = 0 V — — -0.5 µA IIN(1) VIN = 5.0 V — — 1.0 µA DATA Output Voltage V OUT(0) IOUT = 500 µA — — 1.5 V VOUT(1) IOUT = -500 µA 3.5 — — V CST Current I CST Charging 14 20 28 µA Discharging -14 -20 -28 µA CST Threshold V CSTH 2.1 2.5 2.9 V VCSTL — 500 — mV Filter Current I FILTER Charging 7.0 10 15 µA Discharging -7.0 -10 -15 µA Leakage, VFILTER = 2.5 V — 5.0 — nA CD Current I CD Charging 14 22 28 µA Discharging -26 -35 -66 µA CD Current Matching — I CD(DISCHRG)/ICD(CHRG) 1.7 2.2 2.3 — CD Threshold V CD — 2.5 — V CWD Current I CWD Charging 14 22 28 µA Continued next page …

Worcester, Massachusetts 01615-0036 (508) 853-5000 Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units CWD Threshold Voltage V TL 0.80 0.85 0.95 V VTH 2.4 2.75 3.0 V Max. FLL Oscillator Frequency f OSC VDD = 5.1 V, TA = 25°C2 0 — — MH z VDD = 4.5 V, TA = 70°C— 1 0 — MH z IOUT(MAX) Accuracy — I OUT = 1 A — ±20 — % BRAKE Threshold V BRK 1.4 1.7 2.0 V Transconductance Gain g m 0.26 0.35 0.50 A/V Centertap Resistors R CT 5.0 10 13 k Ω Back-EMF Hysteresis — V BEMF - VCTAP a t 1 52 54 0m V FCOM Transition -15 -25 -40 mV ELECTRICAL CHARACTERISTICS continued DATA CLOCK Dwg. WP-019 A C B D C D CHIP SELECT E SERIAL PORT TIMING CONDITIONS

Term. Terminal Name Function 1 LOAD SUPPLY V BB; the 5 V or 12 V motor supply. 2C D2 One of two capacitors used to generate the ideal commutation points from the back-EMF zero-crossing points. 3C WD Timing capacitor used by the watchdog circuit to disable the back-EMF comparators during commutation transients, and to detect incorrect motor position. 4C ST Startup oscillator timing capacitor. 5 OUT A Power amplifier output A to motor. 6-7 GROUND Power and logic ground and thermal heat sink. 8 OUT B Power amplifier output B to motor. 9 OUT C Power amplifier output C to motor. 10 CENTERTAP Motor centertap connection for back-EMF detection circuitry. 11 BRAKE Active low turns ON all three sink drivers shorting the motor windings to ground. External capacitor and resistor at BRAKE provide brake delay. The brake function can also be controlled via the serial port. 12 C RES External reservoir capacitor used to hold charge to drive the source drivers’ gates. Also provides power for brake circuit. 13 FILTER Analog voltage input to control motor current. Also, compensation node for internal speed control loop. 14 INDEX External tachometer input. 15 LOGIC SUPPLY V DD; the 5 V logic supply. 16 OSCILLATOR Clock input for the speed reference counter. Typical max. frequency is 10 MHz.

17 DATA OUT Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real time,

controlled by 2-bit multiplexer in serial port. 18-19 GROUND Power and logic ground and thermal heat sink. 20 RESET When pulled low forces the chip into sleep mode; clears all serial port bits. 21 CHIP SELECT Strobe input (active low) for data word. 22 CLOCK Clock input for serial port. 23 DATA IN Sequential data input for the serial port. 24 C D1 One of two capacitors used to generate the ideal commutation points from the back-EMF zero-crossing points.

Worcester, Massachusetts 01615-0036 (508) 853-5000 Power Outputs. The power outputs of the A8905CLB are n-channel DMOS transistors with a total source plus sink r DS(on) of typically 1.1 Ω . Internal charge pump boost circuitry provides voltage above supply for driving the high-side DMOS gates. Intrinsic ground clamp and flyback diodes provide protection when switching induc- tive loads and may be used to rectify motor back- EMF in power-down conditions. An external Schottky power diode or pass FET is required in series with the load supply to allow motor back- EMF rectification in power-down conditions. Back-EMF Sensing Motor Startup and Running Algorithm. The A8905CLB provides a complete self-contained back-EMF sensing startup and running commutation scheme. The three half- bridge outputs are controlled by a state machine. There are six possible combinations. In each state, one output is high (sourcing current), one low (sinking current), and one is OFF (high impedance or ‘Z’). Motor back EMF is sensed at the OFF output. The truth table for the output drivers sequencing is: Sequencer State OUT A OUTB OUTC

1 High Low Z

2 Z Low High

3 Low Z High

4 Low High Z

5 Z High Low

6 High Z Low

At startup, the outputs are enabled in one of the sequencer states shown. The back EMF is examined at the OFF output by comparing the output voltage to the motor centertap voltage at CENTERTAP. The motor will then either step forward, step backward, or remain stationary (if in a null-torque position). If the motor moves, the back-EMF detection circuit waits for the correct polarity back-EMF zero crossing (output crossing through centertap). True back-EMF zero cross- ings are used by the adaptive commutation delay circuit to advance the state sequencer (commutate) at the proper time to synchronously run the motor. Back-EMF zero crossings are indicated by FCOM, an internal signal that toggles at every zero crossing. FCOM is available at the DATA OUT terminal via the programmable data out multiplexer. Startup Oscillator. If the motor does not move at the initial startup state, then it is in a null-torque position. In this case, the outputs are commutated automatically by the startup oscillator after a period set by the external capacitor at C ST . where t CST = In the next state, the motor will move, back EMF will be detected, and the motor will accelerate synchronously. Once normal synchronous back-EMF commutation occurs, the startup oscillator is defeated by pulses of pulldown current at C ST at each commutation, which prevents CST from reaching its upper threshold and thus completing a cycle and commutating. Dwg. WP-016-1 FCOM FCOM TOGGLES AT BACK-EMF ZERO CROSSING SOURCE ON SINK ON BACK-EMF VOLTAGE V OUTA V OUTB V OUTC V CTAP 4(VCSTH - VCSTL ) x CST IST(charge) + IST(discharge) VCSTL VCSTH VCWD VCST CST Dwg. WP-020 t FUNCTIONAL DESCRIPTION

Adaptive Commutation Delay. The adaptive commutation delay circuit uses the back-EMF zero-crossing indicator signal (FCOM) to determine an optimal commutation time for efficient synchronous operation. This circuit commutates the outputs, delayed from the last zero crossing, using two external timing capacitors, C D1 and CD2 , to measure the time between crossings. Dwg. WP-016-2 FCOM t FCOM t CD1 VCWD VCD1 VCD2 t CD2 where tCD = tFCOM x C D1 charges up with a fixed current from its 2.5 V reference while FCOM is high. When FCOM goes low at the next zero crossing, C D1 is discharged at approximately twice the charging current. When CD 1 reaches the CD threshold, a commutation occurs. CD2 operates similarly except on the opposite phase of FCOM . Thus the commutations occur approximately halfway between zero crossings. The actual delay is slightly less than halfway to compensate for electrical delays in the motor, which improves efficiency. Because the commutation-delay capacitors are adaptive in nature, the absolute value and tolerance is not critical. In choosing these capacitors, the voltage excursion should be 1.5 V to 2.5 V at rated speed. Solving for C in the equation I = Cdv/dt, where dv = 2.5 V, I = 22 µA, and dt = t FCOM = Use of a capacitor slightly greater than this value will ensure that the commuta- tion delay capacitors never charge to the high rail. Blanking and Watchdog Timing Functions. The blanking and watchdog timing functions are derived from one timing capacitor, CWD . where t BLANK = and t WD = The CWD capacitor begins charging at each commutation, initiating the BLANK signal. BLANK is an internal signal that inhibits the back-EMF comparators during the commutation transients, preventing errors due to inductive recovery and voltage settling transients. t BLANK Dwg. WP-022 BLANK CWDV V TL ICD(charge), [ICD(discharge)] V TL x CWD ICWD V TH x CWD ICWD 20/RPM #motor poles WATCHDOG-TRIGGERED COMMUTATION t BLANK t WD V TL VTH Dwg. WP-021 BLANK CWDV NORMAL COMMUTATION

Worcester, Massachusetts 01615-0036 (508) 853-5000 A once-per-revolution TACH signal can be generated by counting cycles of FCOM (the number of motor poles must be selected via the serial port). TACH is then a jitter-free signal that toggles once per motor revolution. The rising edge of TACH triggers REF, a precision speed reference derived by a programmable counter. The duration of REF is set by programming the counter to count the desired number of OSC cycles desired total count= where the total count (number of oscillator cycles) is equal to the sum of the selected (programmed low) count numbers corresponding to bits D5 through D18. The speed error is detected as the difference in falling edges of TACH and REF. The speed error signals control the error-correcting charge pump on the FILTER terminal, which drive the external loop compensation components to correct the motor current. Index. An external tachometer signal may be used to create the TACH signal, rather than the internally derived once around. To use this mode, the signal is input to the INDEX terminal, and the index mode must be enabled via the serial port. When Switching from the once-around mode to index mode, it is important to monitor the SYNC signal on DATA OUT, and switch modes only when SYNC is low. This ensures making the transition without disturbing the speed control loop. The speed reference counter should be reprogrammed at the same time. Speed Loop Initialization (YANK). To improve the acquire time of the speed control loop, there is an automatic feature controlled by an internal YANK signal. The motor is started at the maximized programmed current by bypassing the FILTER terminal. The FILTER terminal is clamped to two diodes above ground, initializing it near the closed loop operating point. YANK is enabled at startup and stays high until the desired speed is reached. Once the first error-fast occurs, indicating the motor crossed through the desired speed, YANK goes low. This releases the clamp on the FILTER terminal and current control is returned to FILTER. This feature optimizes speed The watchdog timing function allows time to detect correct motor position by checking the back-EMF polarity after each commutation. If the correct polarity is not observed between t BLANK and tWD , then the watchdog timer commutates the outputs to the next state to synchronize the motor. This function is useful in preventing excessive reverse rotation, and helps in resynchronizing (or starting) with a moving spindle. Current Control. The A8905CLB provides linear current control via the FILTER terminal, an analog voltage input. Maximum current limit is also provided, and is controlled in four steps via the serial port. Output current is sensed via an internal sense resistor (R S). The voltage across the sense resistor is compared to one-tenth the voltage at the FILTER terminal less two diode drops, or to the maximum current limit reference, whichever is lower. This transconductance function is I OUT = (VFILTER -2VD ) / 10RS, where RS is nominally 0.3 Ω and VD is approximately 0.7 V. YANK SPEED-CONTROL INITIALIZATION POWER UP ERROR FAST FROM FLL S Q R C R C FILTER Id Ic V DD ERROR SLOW FROM FLL CHARGE ERROR FAST OUT V BB V DD ÷10 SEQUENTIAL LOGIC C RES BOOST CHARGE PUMP MUX LINEAR CURRENT CONTROL FROM SERIAL PORT REGISTER D3 AND D4 V maxI 1.85 V x1 R S Speed Control. The A8905CLB includes a frequency-locked loop speed control system. This system monitors motor speed via internal or external digital tachometer signals, generates a precision speed reference, determines the digital speed error, and corrects the motor current via an internal charge pump and external filtering components on the FILTER terminal. 60 x fOSC desired motor speed (rpm) Dwg. EP-046 Dwg. EP-045 SECTOR FCOM TACH D5 –D18 D19 D20 & D21 OSC REF 4-BIT FIXED COUNTER 14-BIT PROGRAMMABLE COUNTER SERIAL PORT REGISTER COUNT (3 x MOTOR POLES) MUX ÷2 REF TACH ERROR FAST ONCE-AROUND PULSE REF TACH ERROR SLOW

MOTOR CONTROLLER/DRIVER V BRK V FAULT - V D acquire and minimizes settling. The Current Control Block Diagram illustrates the YANK signal and its effects. Braking. A dynamic braking feature of the A8905CLB shorts the three motor windings to ground. This is accomplished by turning the three source drivers OFF and the three sink drivers ON. Activation of the brake can be implemented through the BRAKE input or through the D2 bit in the serial port. The supply voltage for the brake circuitry is the C RES voltage, allowing the brake function to remain active after power failure. Power-down braking with delay can be implemented by using an external RC and other components to control the brake terminal, as shown. Brake delay can be set using the equation below to ensure that voice-coil head retract occurs before the spindle motor brake is activated. Once the brake is activated, due to the inherent capacitive input, the three sink drivers will remain active until the device is reset. t BRK = RB C B 1 – ln BRAKEFAULT VBRK V – V FAULT D BRAKE ACTIVATED Dwg. OP-004 R B C B t BRK Centertap. The A8905CLB internally simulates the centertap voltage of the motor. To obtain reliable start-up performance from motor to motor, the motor centertap should be connected to this terminal. Serial Port. The serial port functions to write various operational and diagnostic modes to the A8905CLB. The serial port DATA IN is enabled/disabled by the CHIP SELECT terminal. When CHIP SELECT is high the serial port is disabled and the chip is not affected by changes in data at the DATA IN or CLOCK terminals. To write data to the serial port, the CLOCK terminal should be low prior to the CHIP SELECT terminal going low. Once CHIP SELECT goes low, information on the DATA IN terminal is read into the shift register on the positive-going transition of the CLOCK. There are 24 bits in the serial input port. Data written into the serial port is latched and becomes active upon the low-to-high transition of the CHIP SELECT terminal at the end of the write cycle. D0 will be the last bit written to the serial port. Reset. The RESET terminal (when pulled low) clears all serial port bits, including the D0 latch, which puts the A8905CLB in the sleep mode. Dwg. EP-036-1 INDEX CHIP SELECT +5 V VRET C WD C D2 C D1 RESET CLOCK DATA IN V BB C ST RESC C F2 R F1 C F1 BYPASS 0.22 µF BYPASS 1312 DDV BBV SERIAL PORT FLL MUX COMMUTATION DELAY BOOST CHARGE PUMP OSC (REF) DATA OUT FAULT R B C B TYPICAL APPLICATION

Worcester, Massachusetts 01615-0036 (508) 853-5000 D0- Sleep/Run Mode; LOW = Sleep, HIGH = Run This bit allows the device to be powered down when not in use. D1- Step Mode; LOW = Normal Operation, HIGH = Step Only When in the step-only mode the back-EMF commutation circuitry is disabled and the power outputs are commutated by the start-up oscillator. This mode is intended for device and system testing. D2- Brake; LOW = Run, HIGH = Brake. D3 and D4-These two bits set the output current limit: D3 D4 Current Limit 0 0 Saturated 01 1 A 1 0 800 mA 1 1 600 mA D5 thru D18-This 14-bit word (active low) programs the REF time to set desired motor speed. Bit Number Count Number D5 16 D6 32 D7 64 D8 128 D9 256 D10 512 D11 1 024 D12 2 048 D13 4 096 D14 8 192 D15 16 384 D16 32 768 D17 65 536 D18 131 072 SERIAL PORT BIT DEFINITIONS D19-Speed-control mode switch; LOW = internal once-around speed signal, HIGH = external index data. D20 and D21-These bits program the number of motor poles for the once-around FCOM counter: D20 D21 Motor Poles 00 8 01 – 10 1 6 11 1 2 D22 and D23-Control the multiplexer for DATA OUT: D22 D23 Data Out 0 0 TACH (once around or index) 0 1 Thermal Shutdown 1 0 SYNC 1 1 FCOM

(for reference only) Dimensions in Millimeters (controlling dimensions) 0° TO 8° 1 2 3 0.2992 0.2914 0.6141 0.5985 0.491 0.394 0.020 0.013 0.0926 0.1043 0.0040 MIN. 0.0125 0.0091 Dwg. MA-008-25 in 0.050 BSC 24 13 NOTE 1 NOTE 3 0.050 0.016 0° TO 8° 1 2 3 7.60 7.40 15.60 15.20 10.65 10.00 0.51 0.33 2.65 2.35 0.10 MIN. 0.32 0.23 Dwg. MA-008-25A mm 1.27 BSC 24 13 NOTE 1 NOTE 3 1.27 0.40 NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor’s option within limits shown.

Worcester, Massachusetts 01615-0036 (508) 853-5000 Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.