A8902

8902A ALLEGRO

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Technical content

Dwg. PP-040B ABSOLUTE MAXIMUM RATINGS at TA = +25°C Logic Input Voltage Range, Package Power Dissipation, PD See Graph Operating Temperature Range, Storage Temperature Range, † Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. Output current rating may be restricted to a value determined by system concerns and factors. These include: system duty cycle and timing, ambient temperature, and use of any heatsinking and/or forced cooling. For reliable operation, the specified maximum junction temperature should not be exceeded. Always order by complete part number, e.g., A8902CLBA . Data Sheet 26301.2 The A8902CLBA is a three-phase brushless dc motor controller/ driver for use in 5 V or 12 V hard-disk drives. The three half-bridge outputs are low on-resistance n-channel DMOS devices capable of driving up to 1.25 A. The A8902CLBA provides complete, reliable, self-contained back-EMF sensing motor startup and running algorithms. A programmable digital frequency-locked loop speed control circuit together with the linear current control circuitry provides precise motor speed regulation. A serial port allows the user to program various features and modes of operation, such as the speed control parameters, startup current limit, sleep mode, diagnostic modes, and others. The A8902CLBA is fabricated in Allegro’s BCD (Bipolar CMOS DMOS) process, an advanced mixed-signal technology that combines bipolar, analog and digital CMOS, and DMOS power devices. The A8902CLBA is provided in a 24-lead wide-body SOIC batwing package. It provides for the smallest possible construction in surface-mount applications.

FEATURES

I Low rDS(on) I Startup Commutation Circuitry I Back-EMF Commutation Circuitry I Serial Port Interface I Frequency-Locked Loop Speed Control I Sector Data Tachometer Signal Input I Programmable Start-Up Current I Diagnostics Mode I Sleep Mode I Linear Current Control I Internal Current Sensing I Dynamic Braking Through Serial Port I Power-Down Dynamic Braking I System Diagnostics Data Out I Data Out Ported in Real Time I Internal Thermal Shutdown Circuitry 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING 1312 BRAKE FILTER DATA IN LOGIC SUPPLY GROUND CHIP SELECT CLOCK RESET GROUND GROUND GROUND DDV CST OUT A OUT B OUT C C D1BBVLOAD SUPPLY C WD C D2 DATA OUT SECTOR DATA CENTERTAP OSCILLATOR C RES SERIAL PORT FLL MUX COMMUTATION DELAY BOOST CHARGE PUMP 8902–A

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM CURRENT CONTROL Dwg. FP-034 2221 1720 CENTERTAP 10 C WD 3 OSC 16 SECTOR DATA 14 FILTER C ST C RES BRAKE OUT A OUT B OUT C COMMUTATION LOGIC COMMUTATION DELAY C D1 C D2 24 2 WATCHDOG TIMER SEQUENCE LOGIC BLANK FCOM OUT A5 OUT B8 OUT C9

1 LOAD

OSC. BOOST CHARGE PUMPBRAKE 18-19 6-7 GROUND GROUND 50 75 100 125 150 2.5 1.5 1.0 0.5 TEMPERATURE in °C 2.0 Dwg. GP-019B R = 6°C/W θJT R = 55°C/W θJA ALLOWABLE PACKAGE POWER DISSIPATION in WATTS Copyright © 1992, 1995 Allegro MicroSystems, Inc.

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Logic Supply Voltage V DD Operating 4.5 5.0 5.5 V Logic Supply Current I DD Operating — 7.5 10 mA Sleep Mode — 250 500 µA Load Supply Voltage V BB Operating 4.0 — 14 V Thermal Shutdown T J — 165 — °C Thermal Shutdown Hysteresis ∆TJ — 20 — °C Output Drivers Output Leakage Current I DSX VBB = 14 V, VOUT = 14 V — 1.0 300 µA VBB = 14 V, VOUT = 0 V — -1.0 -300 µA Total Output ON Resistance r DS(on) IOUT = 600 mA — 1.0 1.4 Ω Output Sustaining Voltage V DS(sus) VBB = 14 V, IOUT = IOUT (MAX), L = 3 mH 14 —— V Clamp Diode Forward Voltage V F IF = 1.0 A — 1.25 1.5 V Control Logic Logic Input Voltage V IN(0) SECTOR DATA, RESET, CLK, -0.3 — 1.5 V VIN(1) CHIP SELECT, OSC 3.5 — 5.3 V Logic Input Current I IN(0) VIN = 0 V —— -0.5 µA IIN(1) VIN = 5.0 V —— 1.0 µA DATA Output Voltage V OUT(0) IOUT = 500 µA —— 1.5 V VOUT(1) IOUT = -500 µA 3.5 —— V C ST Current I CST Charging -9.0 -10 -11 µA Discharging — 500 — µA C ST Threshold V CSTH 2.25 2.5 2.75 V VCSTL 0.85 1.0 1.15 V Filter Current I FILTER Charging -9.0 -10 -11 µA Discharging 9.0 10 11 µA Leakage, VFILTER = 2.5 V —— 5.0 nA Filter Threshold V FILTERTH 1.57 1.85 2.13 V C D Current I CD Charging -18 -20 -22 µA Discharging 32 40 48 µA C D Current Matching — ICD(DISCHRG) /ICD(CHRG) 1.8 2.0 2.2 — C D Threshold V CDTH 2.25 2.5 2.75 V Continued next page … (Source + Sink + RS) (CD1 or CD2 )

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 SERIAL PORT TIMING CONDITIONS Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units C WD Current I CWD Charging -9.0 -10 -11 µA C WD Threshold Voltage V TL 0.22 0.25 0.28 V VTH 2.25 2.5 2.75 V Max. FLL Oscillator Frequency fOSC VDD = 5.0 V, TA = 25°C1 2 —— MHz IOUT (MAX) — D3 = 0, D4 = 0 1.0 1.2 1.4 A D3 = 0, D4 = 1 0.9 1.0 1.1 A D3 = 1, D4 = 0 0.5 0.6 0.7 A D3 = 1, D4 = 1 — 250 — mA BRAKE Threshold V BRK 1.5 1.75 2.0 V BRAKE Hysteresis Current I BRKL VBRK = 750 mV — 20 — µA Transconductance Gain g m 0.42 0.50 0.58 A/V Centertap Resistors R CT 5.0 10 13 k Ω Back-EMF Hysteresis — VBEMF - VCTAP at 5.0 20 37 mV FCOM Transition -5.0 -20 -37 mV ELECTRICAL CHARACTERISTICS continued DATA CLOCK Dwg. WP-019 A C B D C D CHIP SELECT E

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER TERMINAL FUNCTIONS Term. Terminal Name Function 1 LOAD SUPPLY V BB ; the 5 V or 12 V motor supply. 2C D2 One of two capacitors used to generate the ideal commutation points from the back-EMF zero crossing points. 3C WD Timing capacitor used by the watchdog circuit to disable the back-EMF compara- tors during commutation transients, and to detect incorrect motor position. 4C ST Startup oscillator timing capacitor. 5 OUT A Power amplifier A output to motor. 6-7 GROUND Power and logic ground and thermal heat sink. 8 OUT B Power amplifier B output to motor. 9 OUT C Power amplifier C output to motor. 10 CENTERTAP Motor centertap connection for back-EMF detection circuitry. 11 BRAKE Active low turns ON all three sink drivers shorting the motor windings to ground. External capacitor and resistor at B RAKE provide brake delay. The brake function can also be controlled via the serial port.

12 C RES External reservoir capacitor used to hold charge to drive the source drivers’

gates. Also provides power for brake circuit. 13 FILTER Analog voltage input to control motor current. Also, compensation node for internal speed control loop. 14 SECTOR DATA External tachometer input. Can use sector or index pulses from disk to provide precise motor speed feedback to internal frequency-locked loop. 15 LOGIC SUPPLY V DD ; the 5 V logic supply. 16 OSCILLATOR Clock input for the speed reference counter. Typical max. frequency is 10 MHz.

17 DATA OUT Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real

time, controlled by 2-bit multiplexer in serial port. 18-19 GROUND Power and logic ground and thermal heat sink. 20 RESET When pulled low forces the chip into sleep mode; clears all serial port bits. 21 CHIP SELECT Strobe input (active low) for data word. 22 CLOCK Clock input for serial port. 23 DATA IN Sequential data input for the serial port. 24 C D1 One of two capacitors used to generate the ideal commutation points from the back-EMF zero crossing points.

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 backward, or remain stationary (if in a null-torque position). If the motor moves, the back-EMF detection circuit waits for the correct polarity back-EMF zero crossing (output crossing through centertap). True back-EMF zero crossings are used by the adaptive commutation delay circuit to advance the state sequencer (commutate) at the proper time to synchronously run the motor. Back-EMF zero crossings are indi- cated by FCOM, an internal signal that toggles at every zero crossing. FCOM is available at the DATA OUT terminal via the programmable data out multiplexer. Startup Oscillator. If the motor does not move at the initial startup state, then it is in a null-torque position. In this case, the outputs are commutated automatically by the startup oscillator after a period set by the external capacitor at C ST where tCST = In the next state, the motor will move, back EMF will be detected, and the motor will accelerate synchronously. Once normal synchro- nous back-EMF commutation occurs, the startup oscillator is defeated by pulses of pulldown current at C ST at each commutation, which prevents CST from reaching its upper threshold and thus completing a cycle and commutating. Dwg. WP-016-1 FCOM FCOM TOGGLES AT BACK-EMF ZERO CROSSING SOURCE ON SINK ON BACK-EMF VOLTAGE V OUTA V OUTB V OUTC V CTAP 4(VCSTH - VCSTL ) x CST IST(charge) + IST(discharge) Power Outputs. The power outputs of the A8902CLBA are n-channel DMOS transistors with a total source plus sink r DS(on) of typically 1 Ω . Internal charge pump boost circuitry provides voltage above supply for driving the high-side DMOS gates. Intrinsic ground clamp and flyback diodes provide protection when switching inductive loads and may be used to rectify motor back-EMF in power-down conditions. An external Schottky power diode or pass FET is required in series with the load supply to allow motor back-EMF rectification in power down conditions. Back-EMF Sensing Motor Startup and Running Algorithm. The A8902CLBA provides a complete self-contained back-EMF sensing startup and running commutation scheme. The three half-bridge outputs are controlled by a state machine. There are six possible combinations. In each state, one output is high (sourcing current), one low (sinking current), and one is OFF (high impedance or ‘Z’). Motor back EMF is sensed at the OFF output. The truth table for the output drivers sequencing is: Sequencer State OUT A OUT B OUT C

1 High Low Z

2 Z Low High

3 Low Z High

4 Low High Z

5 Z High Low

6 High Z Low

At startup, the outputs are enabled in one of the sequencer states shown. The back EMF is examined at the OFF output by comparing the output voltage to the motor centertap voltage at CENTERTAP. The motor will then either step forward, step FUNCTIONAL DESCRIPTION

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Blanking and Watchdog Timing Functions. The blanking and watchdog timing functions are derived from one timing capacitor, CWD . where t BLANK = and t WD = The CWD capacitor begins charging at each commutation, initiating the BLANK signal. BLANK is an internal signal that inhibits the back- EMF comparators during the commutation transients, preventing errors due to inductive recovery and voltage settling transients. The watchdog timing function allows time to detect correct motor position by checking the back-EMF polarity after each commutation. If the correct polarity is not observed between t BLANK and tWD , then the watchdog timer commutates the outputs to the next state to synchro- nize the motor. This function is useful in preventing excessive reverse rotation, and helps in resynchronizing (or starting) with a moving spindle. Adaptive Commutation Delay. The adaptive commutation delay circuit uses the back-EMF zero-crossing indicator signal (FCOM) to determine an optimal commuta- tion time for efficient synchronous operation. This circuit commutates the outputs, delayed from the last zero crossing, using two external timing capacitors, C D1 and CD2 , to measure the time between crossings. where tCD = tFCOM x C D1 charges up with a fixed current from its 2.5 V reference while FCOM is high. When FCOM goes low at the next zero crossing, C D1 is discharged at approximately twice the charging current. When CD1 reaches the CD threshold, a commutation occurs. C D2 operates similarly except on the opposite phase of FCOM . Thus the com- mutations occur approximately halfway between zero crossings. The actual delay is slightly less than halfway to compensate for electrical delays in the motor, which im- proves efficiency. Dwg. WP-016-2 FCOM t FCOM t CD1 VCWD VCD1 VCD2 t CD2 VTL x CWD ICWD VTH x CWD ICWD WATCHDOG-TRIGGERED COMMUTATION t BLANK Dwg. WP-022 BLANK CWDV V TL NORMAL COMMUTATION t BLANK t WD V TL VTH Dwg. WP-021 BLANK CWDV ICD(charge) ICD(discharge)

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 Dwg. EP-045 SECTOR FCOM TACH D5 –D18 D19 D20 & D21 OSC REF 4-BIT FIXED COUNTER 14-BIT PROGRAMMABLE COUNTER SERIAL PORT REGISTER COUNT (3 x MOTOR POLES) MUX ÷2 REF TACH ERROR FAST ONCE-AROUND PULSE REF TACH ERROR SLOW Speed Control. The A8902CLBA includes a frequency-locked loop speed control system. This system monitors motor speed via internal or external digital tachometer signals, generates a precision speed reference, determines the digital speed error, and corrects the motor current via an internal charge pump and external filtering compo- nents on the FILTER terminal. A once per revolution TACH signal can be generated by counting cycles of FCOM (the number of motor poles must be selected via the serial port). TACH is then a jitter-free signal that toggles once per motor revolution. The rising edge of TACH triggers REF, a precision speed reference derived by a programmable counter. The duration of REF is set by programming the counter to count the desired number of OSC cycles YANK SPEED-CONTROL INITIALIZATION POWER UP ERROR FAST FROM FLL S Q R C R C FILTER Id Ic V DD ERROR SLOW FROM FLL CHARGE PUMP ERROR FAST FROM FLL Dwg. EP-046 OUT V BB V DD ÷10 SEQUENTIAL LOGIC C RES BOOST CHARGE PUMP MUX LINEAR CURRENT CONTROL FROM SERIAL PORT REGISTER D3 AND D4 MAX CURRENT LIMIT V maxI 1.85 V x1 R S Current Control. The A8902CLBA provides linear current control via the FILTER terminal, an analog voltage input. Maximum current limit is also provided, and is controlled in four steps via the serial port. Output current is sensed via an internal sense resistor (R S). The voltage across the sense resistor is compared to one-tenth the voltage at the FILTER terminal less the filter threshold voltage, or to the maxi- mum current limit reference, whichever is lower. This transcon- ductance function is I OUT = (VFILTER -VFILTERTH ) / 10RS, where RS is nominally 0.2 Ω and VFILTERTH is approximately 1.85 V. desired total count= where the total count (number of oscillator cycles) is equal to the sum of the selected (programmed low) count numbers corre- sponding to bits D5 through D18. The speed error is detected as the difference in falling edges of TACH and REF. The speed error signals control the error-correcting charge pump on the FILTER terminal, which drive the external loop com- pensation components to correct the motor current. Sector Mode. An external tachometer signal, such as sector or index pulses, may be used to create the TACH signal, rather than the internally derived once around. To use this mode, the signal is input to the SECTOR terminal, and the sector mode must be enabled via the serial port. When Switch- ing from the once-around mode to sector mode, it is important to monitor the SYNC signal on DATA OUT, and switch modes only when SYNC is low. This ensures making the transition without disturbing the speed control loop. The speed reference counter should be reprogrammed at the same time. Speed Loop Initialization (YANK). To improve the acquire time of the speed control loop, there is an automatic feature controlled by an internal YANK signal. The motor is started at the maximized programmed current by bypassing the FILTER terminal. The FILTER terminal is clamped to an internal reference (the filter threshold voltage), initializing it near the closed loop operating point. YANK is enabled at startup and stays high until the desired speed is reached. Once the first error-fast occurs, indicating the motor crossed through the desired speed, YANK goes low. This releases the clamp on the FILTER terminal and current control is returned to FILTER. This feature optimizes speed acquire and minimizes settling. The Current Control Block Diagram illustrates the YANK signal and its effects. 60 x fOSC desired motor speed (rpm)

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Serial Port. The serial port functions to write various operational and diagnostic modes to the A8902CLBA. The serial port DATA IN is enabled/disabled by the CHIP SELECT terminal. When CHIP SE- LECT is high the serial port is disabled and the chip is not affected by changes in data at the DATA IN or CLOCK terminals. To write data to the serial port, the CLOCK terminal should be low prior to the CHIP SELECT terminal going low. Once CHIP SELECT goes low, information on the DATA IN terminal is read into the shift register on the positive-going transition of the CLOCK. There are 24 bits in the serial input port. Data written into the serial port is latched and becomes active upon the low-to-high transition of the CHIP SELECT terminal at the end of the write cycle. D0 will be the last bit written to the serial port. SERIAL PORT BIT DEFINITIONS D0- Sleep/Run Mode; LOW = Sleep, HIGH = Run This bit allows the device to be powered down when not in use. D1- Step Mode; LOW = Normal Operation, HIGH = Step Only When in the step-only mode the back-EMF commutation circuitry is disabled and the power outputs are commutated by the start- up oscillator. This mode is intended for device and system testing. D2- Brake; LOW = Run, HIGH = Brake. D3 and D4 - These two bits set the output current limit: D3 D4 Current Limit 0 0 1.2 A 0 1 1 A 1 0 600 mA 1 1 250 mA D5 thru D18-This 14-bit word (active low) programs the REF time to set desired motor speed. Bit Number Count Number D5 16 D6 32 D7 64 D8 128 D9 256 D10 512 D11 1 024 D12 2 048 D13 4 096 D14 8 192 D15 16 384 D16 32 768 D17 65 536 D18 131 072 D19-Speed-control mode switch; LOW = internal once-around speed signal, HIGH = external sector data. D20 and D21-These bits program the number of motor poles for the once-around FCOM counter: D20 D21 Motor Poles 00 8 01 – 10 1 6 11 1 2 D22 and D23-Controls the multiplexer for DATA OUT: D22 D23 DATA OUT 0 0 TACH (once around or sector) 0 1 Thermal Shutdown 1 0 SYNC 1 1 FCOM Reset. The RESET terminal when pulled low clears all serial port bits, including the D0 latch, which puts the A8902CLBA in the sleep mode.

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 Dwg. EP-036C SECTOR DATA CHIP SELECT +5 V VRET C WD C D2 C D1 RESET CLOCK DATA IN V BB C ST RESC C F2 R F1 C F1 BYPASS 0.22 µF BYPASS 1312 DDV BBV SERIAL PORT FLL MUX COMMUTATION DELAY BOOST CHARGE PUMP OSC (REF) DATA OUT FAULT R B C B TYPICAL APPLICATION BRAKEFAULT VBRK V – V FAULT D BRAKE ACTIVATED Dwg. OP-004 R B C B t BRK Braking. A dynamic braking feature of the A8902CLBA shorts the three motor windings to ground. This is accomplished by turning the three source drivers OFF and the three sink drivers ON. Activation of the brake can be implemented through the BRAKE input or through the D2 bit in the serial port. The supply voltage for the brake circuitry is the C RES voltage, allowing the brake function to remain active after power failure. Power-down braking with delay can be implemented by using an external RC and other components to control the brake terminal, as shown. Brake delay can be set using the equation below to ensure that voice-coil head retract occurs before the spindle motor VBRK VFAULT - VD brake is activated. Once the brake is acti- vated, due to the inherent capacitive input, the three sink drivers will remain active until the device is reset. t BRK = RBC B 1 – ln Centertap. The A8902CLBA internally simulates the centertap voltage of the motor. To obtain reliable start-up performance from motor to motor, the motor centertap should be connected to this terminal. External Component Selection. Appli- cations information regarding the selection of external component values is available from the factory for external component selection, frequency-locked loop speed control, and commutation delay capacitor selection.

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Dimensions in Inches (for reference only) 0° TO 8° 1 2 3 0.2992 0.2914 0.6141 0.5985 0.491 0.394 0.020 0.013 0.0926 0.1043 0.0040 MIN. 0.0125 0.0091 Dwg. MA-008-25 in 0.050 BSC 24 13 NOTE 1 NOTE 3 0.050 0.016 Dimensions in Millimeters (controlling dimensions) 0° TO 8° 1 2 3 7.60 7.40 15.60 15.20 10.65 10.00 0.51 0.33 2.65 2.35 0.10 MIN. 0.32 0.23 Dwg. MA-008-25A mm 1.27 BSC 24 13 NOTE 1 NOTE 3 1.27 0.40 NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor’s option within limits shown.

8902–A 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Worcester, Massachusetts 01615-0036 (508) 853-5000 Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibil- ity for its use; nor for any infringements of patents or other rights of third parties which may result from its use.