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Figure 1. Typical circuit with separate power supply to transformer Figure 2. Typical circuit with single power supply
Description
The A8835 is a highly integrated IC that charges photoflash capacitors for digital and film cameras. An integrated MOSFET switch drives the transformer in a flyback topology. It also features an integrated IGBT driver that facilitates the flash discharge function and saves board space. The CHARGE pin enables the A8835 and starts the charging of the output capacitor. When the designated output voltage is reached, the A8835 stops the charging until the CHARGE pin is toggled again. The ¯D¯ ¯ ¯O¯¯¯N¯¯E¯ pin is an open-drain indicator of when the designated output voltage is reached. The peak current limit can be adjusted to eight different levels between 550 mA and 1.75 A, by clocking the CHARGE pin. This allows the user to operate the flash even at low battery voltages. The A8835 can be used with two Alkaline/NiMH/NiCAD or one single-cell Li+ battery connected to the transformer primary. Connect the VIN pin to a 3.0 to 5.5 V supply, which can be either the system rail or the Li+ battery, if used. The A8835 is available in a very low profile (0.75 mm) 10-contact 3 mm × 3 mm TDFN package, making it ideal for space-constrained applications. It is lead (Pb) free, with 100% matte-tin leadframe plating and has an exposed pad for enhanced thermal dissipation. Features and Benefits ▪ Eight-level, digitally-programmable current limits from 550 mA to 1.75 A ▪ V oltage sensing feedback before output diode for low leakage ▪ No external pull-down resistors needed ▪ Power with 1 Li+ or 2 Alkaline/NiMH/NiCAD batteries ▪ Low quiescent current draw (1 μA max in shutdown mode) ▪ Zero-voltage switching for lower loss ▪ Adjustable output voltage ▪ Integrated IGBT driver with trigger ▪ Charge complete indication ▪ >75% efficiency ▪ Low-profile (0.75 mm high) 3 mm × 3 mm TDFN 10-contact package Photoflash Capacitor Charger with Programmable Current Limit and IGBT Driver Package: 10-contact TDFN with exposed thermal pad (suffix EJ) Applications: Typical Applications A8835 ▪ Digital camera flash ▪ Film camera flash ▪ Cell phone flash ▪ Emergency strobe light To IGBT Gate VOUT N =10.2 100 k7 150 k7 1.20 k7 150 k7 1%R4 VBATT 1.5 to 5.5 VVBIAS 3.0 to 5.5 V CIN 4.7 μF COUT 100 μF
330 VC1
0.1 μF A8835 CHARGE GND FB SW TRIGGER IGBTDRV DONE VIN
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 2Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Selection Guide Part Number Package Packing* A8835EEJTR-T 10-pin TDFN 1500 pieces/ 7-in. reel *Contact Allegro for additional packing options Absolute Maximum Ratings Characteristic Symbol Notes Rating Units SW pin V SW DC voltage. (VSW is self-clamped by an internal active clamp and is allowed to exceed 40 V dur- ing flyback spike durations. Maximum repetitive energy during flyback spike: 0.5 μJ at frequency ≤ 400 kHz.) –0.3 to 40 V IGBTDRV pin V IGBTDRV –0.3 to VIN + 0.3 V FB pin V FB –0.3 to VIN V All other pins V X –0.3 to 7 V Operating Ambient Temperature T A Range E –40 to 85 ºC Maximum Junction Temperature T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC Package Thermal Characteristics Characteristic Symbol Test Conditions* Rating Units Package Thermal Resistance RθJA On 4-layer PCB, based on JEDEC standard 45 ºC/W *Additional information is available on the Allegro website.
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Functional Block Diagram VIN VIN SW CHARGE GND CMP2 DONE FB Q ILIM Decoder Adjustable Reference IGBTDRV TRIGGER 40 V DMOS Q QSET CLR S R Q Q SET CLR S R CMP1 1.2 V ILIM Comparator H m L Triggered Timer Control Logic Enable 18 μs One-Shot DCM Detector (dV/dt = 0) 100 kΩ 100 kΩ 20 kΩ Terminal List Table NC FB PAD DONE TRIGGER SW NC IGBTDRV VIN GND CHARGE Device Pin-out Diagram Number Name Function 1,10 NC No connection. 2 IGBTDRV IGBT driver gate drive output. 3 VIN Input voltage. Connect to 3 to 5.5 V bias supply. Decouple VIN voltage with 0.1 μF ceramic capacitor placed close to this pin.
4 GND Device ground
5 CHARGE Charge enable and current limit serial programming pin. Set this pin low to shut down the chip. 6S W Drain connection of internal DMOS switch. Connect to trans- former primary winding.
7 TRIGGER Strobe signal input
Open collector output, pulls low when output reaches target value and CHARGE is high. Goes high during charging or when- ever CHARGE is low.
9 FB Output voltage feedback
–P A D Exposed pad for enhanced thermal dissipation. Connect to ground plane.
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com ELECTRICAL CHARACTERISTICS Valid at VIN = 3.3 V, TA = 25°C except indicates specifications guaranteed from −40°C to 85°C ambient, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Units Supply Voltage* V IN 3 – 5.5 V UVLO Enable Threshold V UVLO VIN rising 2.55 2.65 2.75 V UVLO Hysteresis V UVLOHYS – 150 – mV Supply Current I IN Charging – 1.5 – mA Charging done – 1 10 μA Shutdown (VCHARGE = 0 V, VTRIGGER = 0 V) – 0.01 1 μA Primary Side Current Limit (ILIM clock input at CHARGE pin) ISWLIM1 1.58 1.75 1.93 A ISWLIM2 – 1.58 – A ISWLIM3 – 1.4 – A ISWLIM4 – 1.22 – A ISWLIM5 – 1.05 – A ISWLIM6 – 0.86 – A ISWLIM7 – 0.7 – A ISWLIM8 – 0.55 – A SW On Resistance R DS(On)SW VIN = 3.3 V, ID = 800 mA – 0.27 – Ω SW Leakage Current* I SWLKG VSW = 35 V ––1 μA Switch Off Timeout t OFF(Max) –1 8– μs Switch On Timeout t ON(Max) –1 8– μs CHARGE Input Current I CHARGE VCHARGE = VIN –3 3– μA CHARGE Input Voltage* VCHARGE(H) 2––V VCHARGE(L) – – 0.8 V ILIM Clock High Time at CHARGE Pin tILIM1(H) Initial pulse 20 – – μs tILIM(H) Subsequent pulses 0.2 – – μs ILIM Clock Low Time at CHARGE Pin t ILIM(L) 0.2 – – μs Total ILIM Setup Time t ILIM(SU) –5 4– μs ¯D¯ ¯O¯ ¯N¯ ¯E¯ Output Leakage Current* IDONELKG ––1 μA FB Voltage Threshold* V FB 1.187 1.205 1.223 V FB Input Current I FB VFB = 1.205 V – –120 – nA IGBT Driver IGBTDRV On Resistance to VIN R DS(On)I-V VIN = 3.3 V, VIGBTDRV = 1.5 V, VTRIGGER = VIN –5– Ω IGBTDRV On Resistance to GND R DS(On)I-G VIN = 3.3 V, VIGBTDRV = 1.5 V, VTRIGGER = 0 V – 6 – Ω TRIGGER Input Current I TRIGGER VTRIGGER = VIN –3 3– μA TRIGGER Input Voltage* VTRIGGER(H) 2––V VTRIGGER(L) – – 0.8 V Propagation Delay, Rising t Dr Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V – 30 – ns Propagation Delay, Falling t Df Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V – 30 – ns Output Rise Time t r Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V – 70 – ns Output Fall Time t f Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V – 70 – ns dV/dt Threshold for ZVS Comparator dV/dt Measured at SW pin – 20 – V/ μs *Specification over the range TA = –40°C to 85°C guaranteed by design and characterization.
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Operation Timing Diagram Explanation of Events: A. Start charging by pulling CHARGE to high, provided that V IN is above the VUVLO level. B. Charging stops when V OUT reaches the target voltage. ¯D¯ ¯O¯ ¯N¯ ¯E¯ goes low, to signal the completion of the charging process. C. Start a new charging process with a low-to-high transition at the CHARGE pin. D. Pull CHARGE to low, to put the controller in low-power standby mode. E. Charging does not start, because V IN is below VUVLO level when CHARGE goes high. F. After V IN goes above VUVLO, another low-to-high transition at the CHARGE pin is required to start charging. VOUT CHARGE VIN VUVLO Target VOUT TRIGGER IGBTDRV SW AB CD E F DONE IGBTDRV TRIGGER tDr tr tDf tf 50% 10% 90% 50% 10% 90% IGBT Drive Timing Definition
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Rising Signal IGBT Drive Performance Symbol Parameter Units/Division C2 V IGBTDRV 1 V C3 V TRIGGER 1 V t time 50 ns Conditions Parameter Value tDr 22.881 ns tr 63.125 ns CLOAD 6800 pF Rgate 12 Ω t VIGBTDRV VTRIGGER Falling Signal Symbol Parameter Units/Division C2 V IGBTDRV 1 V C3 V TRIGGER 1 V t time 50 ns Conditions Parameter Value tDf 27.427 ns tf 65.529 ns CLOAD 6800 pF Rgate 12 Ω tr VIGBTDRV VTRIGGER t tf Performance Characteristics IGBT Drive waveforms are measured with R-C load (12 Ω, 6800 pF)
OUT, from the secondary winding. CHARGE pin can start a refresh operation. els, from 1.75 A down to 550 mA, by clocking the CHARGE pin. lower current limit at low battery voltages. rent limit pulses during tILIM(SU) (54 μs) period. Figure 4. ILIM Clock Timing Definition Figure 5. Current Limit Programming Example (ISWLIM4 selected).
limit can be set by sending a burst of pulses to the CHARGE pin. pin will stay high afterwards. ing mode and Timer mode, according to those conditions. Fast Charging mode is shown in figure 4. mode interval is shown in figure 5. flowing, and the switch voltage has dropped to a minimum value. charging time. Minimum-voltage switching is shown in figure 6. ZVS interval is shown in figure 7. Figure 7. ZVS voltage switching: VOUT = 120 V, t =0.2 μs/div, Figure 4. Timer mode and Fast Charging mode: t = 200 ms/div; Figure 5. Expanded view of Timer mode: VOUT ≤ 14 V; t = 2 μs/div; Figure 6. Minimum-voltage switching: VOUT ≥ 15 V; t =1 μs/div;
desired VOUT is 320 V , then the turns ratio should be at least 8.9. the worst case condition, N can be determined to be 9.5. example, a minimum turns ratio of N = 10 is recommended. tance, and minimized primary and secondary series resistance. See the table Recommended Components for more information. reduce input ripple current during this period. See figure 13. Figure 12. Typical input section with input inductance inductance due to long wires in test setup) Figure 13. Effects of changing the values of CIN .
10Allegro MicroSystems, Inc. the VIN pin using a 0.1 μF / 6.3 V bypass capacitor. (transformer primary side) and the rectifier loop (secondary side). breakdown failure of the circuit board. ary and diode to minimize parasitic capacitance. Figure 14. Input current waveforms with Li+ battery connected by 5-in. wire VOUT = 100 V/div.; IBAT = 1 A/div. Figure 16. Input current waveforms with Li+ battery connected through VOUT = 100 V/div.; IBAT = 500 mA/div. Figure 15. Input current waveforms with Li+ battery connected through VOUT = 100 V/div.; IBAT = 1 A/div.
11Allegro MicroSystems, Inc. Figure 17. Equivalent circuit with parasitic capacitors across feedback Figure 18. Recommended layout for feedback divider.
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Recommended Layout Xenon+ CHARGE CHARGE PAD COUT X2C4 A8835 NC NC FB VIN VIN IGBTDRV DONEDONE TRIGGERTRIGGER SW GND Xenon Trigger Xenon– Rg1 CIN
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Recommended Components Component Rating Part Number Source Remarks C1, Input Capacitor 0.1 μF, ±10%, 16 V, X5R or X7R ceramic capacitor (0603) GRM188R71C104KA01D Murata 10 V minimum rating can be used CIN, Input Capacitor 4.7 μF, ±10%, 10 V, X5R or X7R ceramic capacitor (0805) LMK212BJ475KG Taiyo Yuden COUT, Photoflash Capacitor 330 V 100 μF (or 19 to 180 μF) EPH-331ELL101B131S Chemi-Con D1, Output Diode 2 x 250 V, 225 mA, 5 pF BAV23S Philips Semiconductor, Fairchild Semiconductor R1, R2, FB Resistors 150 kΩ each 1/4 W, ± 1%; 1206, 0805, or 0603 resistors rated for 150 V Instead of two resistors, a single 300 kΩ resistor with 350 V rating can be used R3, FB Resistor 1.2 kΩ 1/10 W ±1% (0603 or 0402) T1, Transformer LP = 14.2 μH, IP = 2 A, N = 10 T-15-154M Tokyo Coil Suitable for ILIM from 0.55 to 1.75 A LP = 7.4 μH, IP = 2 A, N = 10 T-16-103A Tokyo Coil Suitable for ILIM from 1.2 to 1.75 A only LP = 12.8 μH, IP = 1.5 A, N=10 T-16-024A Tokyo Coil Suitable for ILIM from 0.55 to 1.4 A only
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 14Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Package EJ, 10-Contact TDFN with Exposed Thermal Pad 2.38 A A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) For Reference Only (reference JEDEC MO-229WEED) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C Reference land pattern layout (reference IPC7351 SON50P300X300X80-11WEED3M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) B PCB Layout Reference View 1.65 2.38 0.30 10 0.500.85 3.10 C 1.65 C0.08 11X CSEATING PLANE D 0.25 +0.05 –0.07 0.50 0.75 ±0.05 3.00 ±0.15 3.00 ±0.15 0.40 ±0.10
Photoflash Capacitor Charger with Programmable Current Limit and IGBT DriverA8835 15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Copyright ©2008-2012, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Revision History
Revision Revision Date Description of Revision Rev. 1 April 19, 2012 Miscellaneous format changes