A8739

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The Allegro® A8739 is a Xenon photoflash charger IC designed to provide an ultra-small solution with flexibility to adjust both charging current limit and output voltage target. By using primary-side voltage sensing, the need for a secondary-side resistive voltage divider is eliminated. This has the additional benefit of reducing leakage currents on the secondary side of the transformer. Target output voltage is primarily determined by the transformer turns ratio, but it can be further adjusted (in steps of –5 V each) using an external resistor. This enables better output accuracy, as well as greater flexibility in the selection of transformers. To extend battery life, the A8739 features very low supply current draw (0.5 μA max in shutdown mode and 10 μA in standby mode). The switch current limit can be programmed from 0.45 to 1.5 A in 16 steps with single wire interface, through the CHARGE pin. The IGBT driver also has internal gate resistors for minimum external component count. The charge and trigger voltage logic thresholds are set at 1 V HI(min) to support applications implementing low-voltage control logic. The A8739 is available in an 8-contact 2 mm × 2 mm DFN/MLP package with a 0.60 maximum overall package height, and an exposed pad for enhanced thermal performance. It is lead (Pb) free with 100% matte tin leadframe plating. 8739-DS Features and Benefits ▪ Primary-side output voltage sensing; no resistor divider required ▪ Adjustable switch peak current limit up to 1.5 A with single-wire programming through the CHARGE pin ▪ Option to fine-tune target voltage ▪ Ultra-small 2 × 2 DFN/MLP-8 package ▪ Integrated IGBT driver with internal gate resistors ▪ Low quiescent current draw (0.5 μA max. in shutdown mode) ▪ 1V logic (VHI(min)) compatibility ▪ Zero-voltage switching for lower loss ▪ >75% efficiency ▪ Charge complete indication ▪ Integrated 50 V DMOS switch Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver Package: 8-pin DFN/MLP (suffix EE) Typical Applications Not to scale A8739 2 mm × 2 mm, 0.60 mm height SW VBAT VIN_VDRV Control Block CHARGE VIN_VDRV DONE GND TRIG VPULLUP VOUT Detect ISW sense DONE COUT 100F 315 V 100 kΩ IGBT Gate GATE IGBT Driver Battery Input 2.3 to 5.5 V RBAT SW VBAT VIN_VDRV Control Block CHARGE VIN_VDRV DONE GND TRIG VPULLUP VOUT Detect ISW sense DONE Battery Input 2.0 to 5.5 V 2.3 to 5.5 V COUT 100F 315 V 100 kΩ IGBT Gate GATE IGBT Driver RBAT Figure 1. Typical applications: (A) with single battery supply and (B) with separate bias supply

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 2Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. A8739 Selection Guide Part Number Packing Package A8739EEETR-T 1500 pieces per reel 8-contact DFN/MLP with exposed thermal pad Absolute Maximum Ratings Characteristic Symbol Notes Rating Units SW Pin V SW DC voltage. (VSW is self-clamped by internal active clamp and is allowed to exceed 50 V during flyback spike durations. Maximum repetitive energy during flyback spike: 0.5 μJ at frequency ≤ 400 kHz.) –0.3 to 50 V VIN_DRV, VBAT Pins V IN –0.3 to 6.0 V CHARGE, TRIG, ¯D¯ ¯O¯ ¯N¯ ¯E¯ Pins Care should be taken to limit the current when –0.6 V is applied to these pins. –0.6 to VIN + 0.3 V V Remaining Pins –0.3 to VIN + 0.3 V V Operating Ambient Temperature T A Range E –40 to 85 ºC Maximum Junction T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Functional Block Diagram VBAT SW GND OCP CHARGE VDSref ton(max) toff(max) DONE TRIG VIN_DRV DMOS VSW – VBAT Q QS R Q QS R DCM Detector ILIM Reference H m L Triggered Timer Control Logic 18 μs 18 μs Enable VIN_DRV IGBT Driver GATE Decoder Pin-out Diagram (Top View) DONE TRIG GATE GND CHARGE VIN_DRV VBAT SW PAD Terminal List Number Name Function 1 ¯D¯ ¯O¯ ¯N¯ ¯E¯ Open collector output, pulls low when output reaches target value and CHARGE is high. Goes high during charging or whenever CHARGE is low. 2 TRIG IGBT trigger input. 3 GATE IGBT gate drive output. 4 GND Ground connection. 5 SW Drain connection of internal DMOS switch. Connect to transformer primary winding.

6 VBAT Connect to battery voltage; directly to select the default output voltage, or through a

series resistor to select a lower output voltage step. 7 VIN_DRV Input voltage. Connect to 3 to 5.5 V bias supply. Decouple V IN voltage with 0.1 μF ceramic capacitor placed close to this pin. 8 CHARGE Charge enable and current limit serial programming pin. Set this pin low to shut down the chip. – PAD Exposed pad for enhanced thermal dissipation. Connect to ground plane.

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 ELECTRICAL CHARACTERISTICS Typical values are valid at VIN = VBAT = 3.6 V; TA = 25°C, except indicates specifications guaranteed from −40°C to 85°C ambient, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit VBAT Voltage Range V BAT 2.0 – 5.5 V VIN_DRV Voltage Range V IN 2.3 – 5.5 V UVLO Enable Threshold V INUV V IN rising – 2.05 2.2 V UVLO Hysteresis V INUV(hys) – 150 – mV VIN Supply Current I IN Shutdown (CHARGE = 0 V, TRIG = 0 V) – 0.02 0.5 μA Charging complete – 50 100 μA Charging (CHARGE = VIN, TRIG = 0 V) – 2 – mA VBAT Pin Supply Current I BAT Shutdown (CHARGE = 0 V, TRIG = 0 V) – 0.01 1 μA Charging done (CHARGE = VIN, Charging (CHARGE = VIN, TRIG = 0 V) – 50 – μA Current Limit Primary-Side Current Limit1 I SWLIM 100% setting 1.35 1.50 1.65 A Switch Current Limit (ILIM Programming Input on CHARGE Pin) ISWLIM1 Default setting – 100 – % ISWLIM2 One pulse applied to CHARGE pin – 95 – % ISWLIM3 Two pulses applied to CHARGE pin – 90 – % ISWLIM4 Three pulses applied to CHARGE pin – 86 – % ISWLIM5 Four pulses applied to CHARGE pin – 81 – % ISWLIM6 Five pulses applied to CHARGE pin – 76 – % ISWLIM7 Six pulses applied to CHARGE pin – 71 – % ISWLIM8 Seven pulses applied to CHARGE pin – 67 – % ISWLIM9 Eight pulses applied to CHARGE pin – 62 – % ISWLIM10 Nine pulses applied to CHARGE pin – 57 – % ISWLIM11 Ten pulses applied to CHARGE pin – 52 – % ISWLIM12 Eleven pulses applied to CHARGE pin – 48 – % ISWLIM13 Twelve pulses applied to CHARGE pin – 43 – % ISWLIM14 Thirteen pulses applied to CHARGE pin – 38 – % ISWLIM15 Fourteen pulses applied to CHARGE pin – 33 – % ISWLIM16 Fifteen pulses applied to CHARGE pin – 29 – % Switch On-Resistance R SWDS(on) V IN_DRV = 3.6 V, ID = 800 mA, TA = 25°C – 0.4 – Ω Switch Leakage Current2 I SWLK V SW = 5.5, over full temperature range – – 2 μA CHARGE Pull-down Resistance R CHGPD – 100 – k Ω CHARGE Input Voltage2 V CHARGE High, over input supply range 1.0 – – V Low, over input supply range – – 0.4 V Continued on the next page…

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Charge Pin Programming ILIM Programming High at CHARGE pin 2 tILIM(H)init Initial Pulse 15 – – μs tILIM(H) Subsequent Pulses 0.2 – – μs ILIM Programming Low at CHARGE pin 2 t ILIM(L) 0.2 – – μs Total ILIM Setup Time at CHARGE pin 2 t ILIM(SU) – 200 – μs Switch-Off Timeout t off(max) – 18 – μs Switch-On Timeout t on(max) – 18 – μs Output Comparator Trip Voltage VOUTTRIP1 Measured as VSW – VBAT (RBAT = 0 Ω) 31 31.5 32 V VOUTTRIP2 Measured as VSW – VBAT (RBAT = 845 Ω) – 31.0 – V VOUTTRIP3 Measured as VSW – VBAT (RBAT = 2.32 kΩ) – 30.5 – V VOUTTRIP4 Measured as VSW – VBAT (RBAT = 4.87 kΩ) – 30.0 – V VOUTTRIP5 Measured as VSW – VBAT (RBAT = 9.09 kΩ) – 29.5 – V Output Low Voltage2 V DONEL 32 μA into ¯D¯ ¯O¯ ¯N¯ ¯E¯ pin – – 100 mV Output Voltage Overdrive V OUTOV Pulse width = 200 ns (90% to 90%) – 200 400 mV dV/dt Threshold for ZVS Comparator dV/dt Measured at SW pin – 20 – V/ μs IGBT Driver TRIG Input Voltage2 VTRIG(H) Input = logic high, over input supply range 1 – – V VTRIG(L) Input = logic low, over input supply range – – 0.4 V TRIG Pull-Down Resistor R TRIGPD – 100 – k Ω GATE Resistance to VIN_DRV R SrcDS(on) VGATE = 1.8 V – 21 – Ω GATE Resistance to GND R SnkDS(on) VGATE = 1.8 V – 27 – Ω Propagation Delay (Rising)3 t Dr Measurement taken at GATE pin, CL= 6500 pF – 25 – ns Propagation Delay (Falling)3 t Df – 60 – ns Output Rise Time3 t r – 290 – ns Output Fall Time3 t f – 380 – ns GATE Pull-Down Resistor R GTPD – 20 – k Ω 1Current limit guaranteed by design and correlation to static test. 2Specifications throughout the range TA = –40°C to 85°C guaranteed by design and characterization. 3See IGBT Drive Timing Definition diagram for further information. ELECTRICAL CHARACTERISTICS (Continued) Typical values are valid at VIN = VBAT = 3.6 V; TA = 25°C, except indicates specifications guaranteed from −40°C to 85°C ambient, unless otherwise noted

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 IGBT Drive Timing Definition GATE TRIG tDr tr tDf tf 50% 10% 90% 50% 10% 90% Operation Timing Diagram high transition at the CHARGE pin. VOUT CHARGE DONE VIN TRIG GATE SW AB Explanation of Events A: Start charging by pulling CHARGE to high, provided that VIN is above UVLO level. B: Charging stops when V OUT reaches the target voltage. C: Start a new charging process with a low-to- D: Pull CHARGE to low to put the controller in low-power standby mode. E: Charging does not start, because VIN is below UVLO level when CHARGE goes high. F: After VIN goes above UVLO, another low-to-high transition at the CHARGE pin is required to start the charging. UVLO Target VOUT CD E F T3T1 T2 T1, T2, T3 (Trigger instances): IGBT driver output pulled high whenever the TRIG pin is at logic high. It is recommended to avoid applying any trigger pulses during charging.

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Characteristic Performance IGBT Drive Performance IGBT drive waveforms are measured at pin, with capacitive load of 6800 pF Rising Signal Symbol Parameter Units/Division C1 V TRIGGER 1 V C2 V GATE 1 V C3 V IN 1 V t time 100 ns Conditions Parameter Value tDr 23 ns tr 320 ns CLOAD 6.8 nF Symbol Parameter Units/Division C1 V TRIGGER 1 V C2 V GATE 1 V C3 V IN 1 V t time 100 ns Conditions Parameter Value tDr 58 ns tr 402 ns CLOAD 6.8 nF C2,C3 C2,C3 t VGATE VTRIGGER VIN Falling Signal tr VGATE VIN VTRIGGER t tf

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Characteristic Performance Time (Sec) Battery Voltage (V) ILIM13 (0.65A) ILIM11 (0.79A) ILIM9 (0.93A) ILIM7 (1.07A) ILIM5 (1.22A) ILIM3 (1.36A) ILIM1 (1.50A) 54% 56% 58% 60% 62% 64% 66% 68% 70% 72% 74% 76% 78% 80% 82% 84% 86% Efficiency (%) ILIM13 (0.65A) ILIM11 (0.79A) ILIM9 (0.93A) ILIM7 (1.07A) ILIM5 (1.22A) ILIM3 (1.36A) ILIM1 (1.50A) Efficiency versus Battery Voltage at Various ILIM RBAT = 0 Ω, Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature Charge Time versus Battery Voltage at Various ILIM RBAT = 0 Ω, Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, COUT = 100 μF / 330 V UCC, at room temperature

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 320 321 322 323 324 325 326 327 328 Battery Voltage (V) ILIM15 (0.51A) ILIM13 (0.65A) ILIM11 (0.79A) ILIM9 (0.93A) ILIM7 (1.07A) ILIM5 (1.22A) ILIM3 (1.36A) ILIM1 (1.50A) 320 321 322 323 324 325 326 327 328 150 200 250 300 350 400 450 500 550 600 650 VOUT (V) VOUT (V) toff (ns) 5.0 4.2 3.6 2.2 VBAT (V) Note: Output voltage is sensed from the primary side winding when the switch turns off. This duration, toff , has to be long enough (>200 ns) in order to obtain an accurate measurement. The value of toff depends on ISWlim, primary inductance, LPrimary , and the turns ratio, N, as given by: toff = (ISWlim × LPRIMARY × N) / VOUT . Final Output Voltage versus Battery Voltage at Various ILIM RBAT = 0 Ω, Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature Final Output Voltage versus Secondary Side Conduction Time at Various Battery Voltages RBAT = 0 Ω, Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Current (A) Battery Voltage (V) ILIM1 (1.50A) ILIM3 (1.36A) ILIM5 (1.22A) ILIM7 (1.07A) ILIM9 (0.93A) ILIM11 (0.79A) ILIM13 (0.65A) ILIM15 (0.51A) Note: Peak switch current is limited by the maximum on-time and di/dt of the transformer primary current; therefore, average input current drops at very low battery voltage. Average Input Current versus Battery Voltage at Various ILIM RBAT = 0 Ω, Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Charging Waveforms Output Capacitor Charging at Various Peak Current Limits Test conditions: VIN = 3.0 V, VBAT = 3.7 V, COUT = 100 μF / 330 V UCC, transformer = T-16-024A (LPRIMARY =12.8 μH, N = 10.25), at room temperature Oscilloscope settings: Ch1 = ¯D¯ ¯O¯ ¯N¯ ¯E¯ (5 V / div), Ch2 = Output Voltage (50 V / div), Ch3 = Input Current (100 mA / div), Time scale = 1 sec / div t VOUT IIN VDONEC2,C3 VOUT IIN VDONE C2,C3 VOUT IIN VDONE C2,C3 VOUT IIN VDONE C2,C3 ILIM9 (0.93 A) ILIM5 (1.22 A) ILIM1 (1.5 A) ILIM11 (0.79 A)

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Output Capacitor Charging at Various Battery Voltages Test conditions: VIN = 3.0 V, ILIM3 (1.36 A), COUT = 100 μF / 330 V UCC, transformer = T-16-024A (LPRIMARY =12.8 μH, N = 10.25), at room temperature Oscilloscope settings: Ch1 = ¯D¯ ¯O¯ ¯N¯ ¯E¯ (5 V / div), Ch2 = Battery Voltage (1 V / div), Ch3 = Output Voltage (50 V / div), Ch4 = Input Current (100 mA V / div), Time scale = 1 sec / div t VOUT IIN VDONE VBAT C2,C3,C4 VOUT IIN VDONE VBAT C2,C3,C4 VBAT = 4.2 V VBAT = 3.7 V VBAT = 3.0 V VBAT = 5.0 V VOUT IIN VDONE VBAT C2,C3,C4 VOUT IIN VDONE VBAT C2,C3,C4

13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Programming section for details. OFF(max) (18 μs), whichever occurs first. N is transformer turns ratio. ton = ISWlim × LPRIMARY / VBAT . described in the next section. Fast Charging mode is shown in figure 2. expanded view of a Timer mode interval is shown in figure 3. Figure 2. Timer mode and Fast Charging mode: VOUT = 50 V/div, Figure 3. Expanded view of Timer mode: VOUT ≤ 10 V, VBAT = 5.5 V,

14Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. flowing, and the switch voltage has dropped to a minimum value. charging time. Minimum-voltage switching is shown in figure 4. ZVS interval is shown in figure 5. Figure 4. Minimum-voltage switching: VOUT ≥ 35 V, VBAT = 5.5 V, Figure 5. True zero-voltage switching (ZVS): VOUT = 75 V, VBAT = 5.5 V,

15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. CHARGE pin will stay high afterwards. Figure 6. ILIM programming timing definition Figure 7. Current limit timing example (I SWLIM4 selected)

16Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Typically N = 10, so the output voltage is approximately 315 V . may affect accuracy of target voltage. BAT × C3) is less than 1 μs approximately. Figure 8. Adjustment of VOUT using a series resistor at the VBAT pin Figure 9. Relationship of VOUT and a series resistor at the VBAT pin

17Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A.

1. The transformer turns ratio, N, determines the output voltage:

ward drop of the output diode.

1. The primary inductance, LPRIMARY , determines the on-time of

ing RSWDS(on) and the DC resistance of the transformer). t on = ISWlim × LPRIMARY /VIN .

1. The secondary inductance, LSECONDARY, determines the off-

= ( ISWlim × LPRIMARY × N) /VOUT . relationships are illustrated in figure 10. between transformer size and efficiency. usually compromised by an increase in parasitic capacitance. when the switch turns on, and to reduced efficiency. Figure 10. Transformer Selection Relationships

18Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. IDPeak = IPRIMARY_Peak / N . Figure 11. Typical input section with input inductance (inductance, LIN, may Figure 12. Input current waveforms with Li+ battery connected by Figure 13. Input current waveforms with Li+ battery connected through Figure 14. Input current waveforms with Li+ battery connected through

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 19Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Layout Guidelines Key to a good layout for the photoflash capacitor charger circuit is to keep the parasitics minimized on the power switch loop (transformer primary side) and the rectifier loop (secondary side). Use short, thick traces for connections to the transformer primary and SW pin. It is important that the ¯D¯ N¯ ¯E¯ signal trace and other signal traces be routed away from the transformer and other switching traces, in order to minimize noise pickup. In addition, high voltage isolation rules must be followed carefully to avoid breakdown failure of the circuit board. Avoid placing any ground plane area underneath the transformer secondary and diode, to minimize parasitic capacitance. For low threshold logic (<1.2 V) add 1 nF capacitors across the CHARGE and TRIGGER pins to GND to avoid malfunction due to noise. Connect the EE package PAD to the ground pad for better ther- mal performance. Use ground planes on the top and bottom layers below the IC and connect them through multiple thermal vias. Refer to the figures on page 20 for recommended layout. Recommended Components Component Rating Part Number Source C1, Input Capacitor 10 μF, ±10%, 6.3 V, X5R ceramic capacitor (0805) JMK212BJ106K Taiyo Yuden C2 0.1uF, 6.3V X5R ceramic capacitor COUT, Photoflash Capacitor 100 μF / 330 V EPH-31ELL101B131S Chemi-Con D1, Output Diode 2 x 250 V, 225 mA, 5 pF BAV23S Philips Semiconductor, Fairchild Semiconductor T1, Transformer LPRIMARY = 12.8 μH, N= 10.25, 6.5 × 8 × 4 mm T-16-024A Tokyo Coil Electric

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 20Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Recommended layout: Schematic Top side Bottom side Top components 0.1uF 10uF VBAT TRIGGER CHARGE DONE Cout1 100uF TCE_T-16-024A Rg SW CHARGE GATE DONE VIN_DRV TRIG GND VBAT Vout TP_Gate 20k R10 1 2 BAV23S 1nF C5 1nF A8739

Ultra-Small Mobile Adjustable Xenon Photoflash Capacitor Charger with IGBT Driver 21Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8739 Copyright ©2009-2010, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Package EE 8-Contact DFN/MLP with Exposed Thermal Pad 1.60 A A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) All dimensions nominal, not for tooling use (reference JEDEC MO-229UCCD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C Reference land pattern layout (reference IPC7351 SON50P200X200X100-9M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) B PCB Layout Reference View 0.90 1.60 0.30 8 0.50 0.83 2.13 C 0.90 0.55 +0.05 –0.04 2.00 ±0.15 2.00 ±0.15 0.25 ±0.05 0.325 ±0.050

0.50 BSC

C0.08 D D Coplanarity includes exposed thermal pad and terminals CSEATING PLANE