DATASHEET SEARCH SITE
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Description
The Allegro® A8735 is a Xenon photoflash charger IC designed to meet the needs of ultra low power, small form factor cameras, particularly camera phones. By using primary-side voltage sensing, the need for a secondary-side resistive voltage divider is eliminated. This has the additional benefit of reducing leakage currents on the secondary side of the transformer. To extend battery life, the A8735 features very low supply current draw (0.5 μA max in shutdown mode). The IGBT driver also has internal gate resistors for minimum external component count. The charge and trigger voltage logic thresholds are set at 1 V HI(min) to support applications implementing low-voltage control logic. The A8735 is available in an 8-contact 2 mm × 2 mm DFN/MLP package with a 0.60 maximum overall package height, and an exposed pad for enhanced thermal performance. It is lead (Pb) free with 100% matte tin leadframe plating. 8735-DS Features and Benefits ▪ Ultra small 2 × 2 DFN/MLP-8 package ▪ Low quiescent current draw (0.5 μA max. in shutdown mode) ▪ Primary-side output voltage sensing; no resistor divider required ▪ Fixed 1 A peak current limit ▪ 1V logic (VHI(min)) compatibility ▪ Integrated IGBT driver with internal gate resistors ▪ Optimized for mobile phone, 1-cell Li+ battery applications ▪ Zero-voltage switching for lower loss ▪ >75% efficiency ▪ Charge complete indication ▪ Integrated 50 V DMOS switch with self-clamping protection Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver Package: 8-pin DFN/MLP (suffix EE) Typical Applications Not to scale A8735 2 mm × 2 mm, 0.60 mm height SW VBAT VIN_VDRV Control Block CHARGE VIN_VDRV DONE GND TRIG VPULLUP VOUT Detect ISW sense DONE Battery Input 2.3 to 5.5 V COUT 100F 315 V 100 kΩ IGBT Gate GATE IGBT Driver SW VBAT VIN_VDRV Control Block CHARGE VIN_VDRV DONE GND TRIG VPULLUP VOUT Detect ISW sense DONE Battery Input 1.5 to 5.5 V COUT 100F 315 V 100 kΩ IGBT Gate GATE IGBT Driver Figure 1. Typical applications: (A) with single battery supply and (B) with separate bias supply
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 2Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A. A8735 Selection Guide Part Number Packing Package A8735EEETR-T 3000 pieces per reel 8-contact DFN/MLP with exposed thermal pad Absolute Maximum Ratings Characteristic Symbol Notes Rating Units SW Pin VSW DC voltage. (VSW is self-clamped by internal active clamp and is allowed to exceed 50 V during flyback spike durations. Maximum repetitive energy during flyback spike: 0.5 μJ at frequency ≤ 400 kHz.) –0.3 to 50 V I SW DC current, pulse width = 1 ms 3 A VIN_DRV, VBAT Pins V IN –0.3 to 6.0 V CHARGE, TRIG, ¯D¯ ¯O¯ ¯N¯ ¯E¯ Pins Care should be taken to limit the current when –0.6 V is applied to these pins. –0.6 to VIN + 0.3 V V Remaining Pins –0.3 to VIN + 0.3 V V Operating Ambient Temperature T A Range E –40 to 85 ºC Maximum Junction T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA 4-layer PCB, based on JEDEC standard 49 ºC/W *Additional thermal information available on Allegro Web site.
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 Functional Block Diagram VBAT SW GND OCP CHARGE VDSref ton(max) toff(max) DONE TRIG VIN_DRV DMOS VSW – VBAT Q QS R Q QS R DCM Detector ILIM Reference H m L Triggered Timer Control Logic 18 μs 18 μs Enable VIN_DRV IGBT Driver GATE Pin-out Diagram (Top View) DONE TRIG GATE GND CHARGE VIN_DRV VBAT SW PAD Terminal List Number Name Function 1 ¯D¯ ¯O¯ ¯N¯ ¯E¯ Open collector output, pulls low when output reaches target value and CHARGE is high. Goes high during charging or whenever CHARGE is low. 2 TRIG IGBT trigger input. 3 GATE IGBT gate drive output. 4 GND Ground connection. 5 SW Drain connection of internal DMOS switch. Connect to transformer primary winding. 6 VBAT Battery voltage. 7 VIN_DRV Input voltage. Connect to 3 to 5.5 V bias supply. Decouple V IN voltage with 0.1 μF ceramic capacitor placed close to this pin. 8 CHARGE Charge enable pin. Set this pin low to shut down the chip. – PAD Exposed pad for enhanced thermal dissipation. Connect to ground plane.
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 ELECTRICAL CHARACTERISTICS Typical values are valid at VIN = VBAT = 3.6 V; TA = 25°C, except indicates specifications guaranteed from −40°C to 85°C ambient, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit VBAT Voltage Range1 V BAT 1.5 – 5.5 V VIN_DRV Voltage Range1 V IN 2.3 – 5.5 V UVLO Enable Threshold V INUV V IN rising – 2.05 2.2 V UVLO Hysteresis V INUV(hys) – 150 – mV VIN Supply Current I IN Shutdown (CHARGE = 0 V, TRIG = 0 V) – 0.02 0.5 μA Charging complete – 50 100 μA Charging (CHARGE = VIN, TRIG = 0 V) – 2 – mA VBAT Pin Supply Current I BAT Shutdown (CHARGE = 0 V, TRIG = 0 V) – 0.01 1 μA Charging done (CHARGE = VIN, Charging (CHARGE = VIN, TRIG = 0 V) – – 50 μA Current Limit Primary-Side Current Limit2 I SWLIM 0.9 1.0 1.1 A Switch On-Resistance R SWDS(on) V IN_DRV = 3.6 V, ID = 600 mA, TA = 25°C – 0.4 – Ω Switch Leakage Current1 I SWLK V SW = 5.5, over full temperature range – – 2 μA CHARGE Input Current I CHARGE V CHARGE = VIN – 36 – μA CHARGE Input Voltage1 V CHARGE High, over input supply range 1.0 – – V Low, over input supply range – – 0.4 V CHARGE On/Off Delay t CH Time between CHARGE = 1 and charging enabled – 20 – us Switch-Off Timeout t off(max) – 18 – μs Switch-On Timeout t on(max) – 18 – μs Output Comparator Trip Voltage3 VOUTTRIP Measured as VSW – VBAT 31.0 31.5 32.0 V Output Comparator Voltage Overdrive V OUTOV Pulse width = 200 ns (90% to 90%) – 200 400 mV ¯D¯ ¯O¯ ¯N¯ ¯E¯ Output Leakage Current1 I DONELK 1 μA dV/dt Threshold for ZVS Comparator dV/dt Measured at SW pin – 20 – V/ μs IGBT Driver TRIG Input Voltage1 VTRIG(H) Input = logic high, over input supply range 1 – – V VTRIG(L) Input = logic low, over input supply range – – 0.4 V TRIG Pull-Down Resistor R TRIGPD – 100 – k Ω GATE Resistance to VIN_DRV R SrcDS(on) VGATE = 1.8 V – 21 – Ω GATE Resistance to GND R SnkDS(on) VGATE = 1.8 V – 27 – Ω Propagation Delay (Rising)4,5 t Dr Measurement taken at ¯D¯ ¯O¯ ¯N¯ ¯E¯ pin, CL= 6500 pF – 25 – ns Propagation Delay (Falling)4,5 tDf – 60 – ns Output Rise Time4,5 tr – 290 – ns Output Fall Time4,5 tf – 380 – ns GATE Pull-Down Resistor R GTPD – 20 – k Ω 1Specifications throughout the range TA = –40°C to 85°C guaranteed by design and characterization. 2Current limit guaranteed by design and correlation to static test. 3Specifications throughout the range TA = –20°C to 85°C guaranteed by design and characterization. 4Guaranteed by design and characterization. 5See IGBT Drive Timing Definition diagram for further information.
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 IGBT Drive Timing Definition GATE TRIG tDr tr tDf tf 50% 10% 90% 50% 10% 90% Operation Timing Diagram high transition at the CHARGE pin. VOUT CHARGE DONE VIN VBAT TRIG GATE SW AB Explanation of Events A: Start charging by pulling CHARGE to high, provided that VIN is above UVLO level. B: Charging stops when VOUT reaches the target voltage. C: Start a new charging process with a low-to- D: Pull CHARGE to low to put the controller in low-power standby mode. E: Charging does not start, because V IN is below UVLO level when CHARGE goes high. F: After VIN goes above UVLO, another low-to-high transition at the CHARGE pin is required to start the charging. UVLO Target VOUT CD E F T3T1 T2 T1, T2, T3 (Trigger instances): IGBT driver output pulled high whenever the TRIG pin is at logic high. It is recommended to avoid applying any trigger pulses during charging.
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 Characteristic Performance IGBT Drive Performance IGBT drive waveforms are measured at pin, with capacitive load of 6800 pF Rising Signal Symbol Parameter Units/Division C1 V TRIGGER 1 V C2 V GATE 1 V C3 V IN 1 V t time 100 ns Conditions Parameter Value tDr 23 ns tr 320 ns CLOAD 6.8 nF C2,C3 t VGATE VTRIGGER VIN tr Symbol Parameter Units/Division C1 V TRIGGER 1 V C2 V GATE 1 V C3 V IN 1 V t time 100 ns Conditions Parameter Value tDr 58 ns tr 402 ns CLOAD 6.8 nF C2,C3 Falling Signal VGATE VIN VTRIGGER t tf
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 Characteristic Performance Time (Sec) Battery Voltage (V) 54% 56% 58% 60% 62% 64% 66% 68% 70% 72% 74% 76% 78% 80% 82% 84% 86% Efficiency (%) Efficiency versus Battery Voltage Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature Charge Time versus Battery Voltage Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, COUT = 100 μF / 330 V UCC, at room temperature
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 320 321 322 323 324 325 326 327 328 Battery Voltage (V) VOUT (V) 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Current (A) Battery Voltage (V) Note: Output voltage is sensed from the primary side winding when the switch turns off. This duration, toff , has to be long enough (>200 ns) in order to obtain an accurate measurement. The value of toff depends on ISWlim, primary inductance, LPrimary , and the turns ratio, N, as given by: toff = (ISWlim × LPRIMARY × N) / VOUT . Final Output Voltage versus Battery Voltage Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature Average Input Current versus Battery Voltage Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 Output Capacitor Charging at Various Battery Voltages Test conditions: VIN = 3.6 V, COUT = 100 μF / 330 V UCC, transformer = T-16-024A (LPRIMARY =12.8 μH, N = 10.25), at room temperature Oscilloscope settings: Ch1 = ¯D¯ ¯O¯ ¯N¯ ¯E¯ (5 V / div), Ch2 = Battery Voltage (1 V / div), Ch3 = Output Voltage (50 V / div), Ch4 = Input Current (100 mA V / div), Time scale = 1 sec / div t C2,C3,C4 VOUT IIN VDONE VBAT C2,C3,C4 VOUT IIN VDONE VBAT C2,C3,C4 VOUT IIN VDONE VBAT VOUT IIN VDONE VBAT C2,C3,C4 VBAT = 4.2 V VBAT = 3.7 V VBAT = 3.0 V VBAT = 5.0 V Charging Waveforms
10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. CHARGE is high and target output voltage is reached. time period, tOFF(max) (18 μs), whichever occurs first. N is transformer turns ratio. ton = ISWlim × LPRIMARY / VBAT . described in the next section. Fast Charging mode is shown in figure 2. expanded view of a Timer mode interval is shown in figure 3. Figure 2. Timer mode and Fast Charging mode: t = 1 s/div; Figure 3. Expanded view of Timer mode: VOUT ≤ 10 V, VBAT = 5.5 V,
11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. flowing, and the switch voltage has dropped to a minimum value. charging time. Minimum-voltage switching is shown in figure 4. ZVS interval is shown in figure 5. Figure 4. Minimum-voltage switching: VOUT ≥ 35 V, VBAT = 5.5 V, Figure 5. True zero-voltage switching (ZVS): VOUT = 75 V, VBAT = 5.5 V,
12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A.
- The transformer turns ratio, N, determines the output voltage:
ward drop of the output diode.
- The primary inductance, LPRIMARY , determines the on-time of
ing RSWDS(on) and the DC resistance of the transformer). t on = ISWlim × LPRIMARY /VIN .
- The secondary inductance, LSECONDARY, determines the off-
= ( ISWlim × LPRIMARY × N) /VOUT . relationships are illustrated in figure 6. between transformer size and efficiency. usually compromised by an increase in parasitic capacitance. when the switch turns on, and to reduced efficiency. Figure 6. Transformer Selection Relationships
13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. ple the battery input, VBAT , at the primary of the transformer. IDPeak = IPRIMARY_Peak / N . Figure 7. Typical input section with input inductance (inductance, LIN, may Figure 9. Input current waveforms with Li+ battery connected through Figure 10. Input current waveforms with Li+ battery connected through Figure 8. Input current waveforms with Li+ battery connected by
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 14Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 Recommended Components Component Rating Part Number Source C1, Input Capacitor 10 μF, ±10%, 6.3 V, X5R ceramic capacitor (0805) JMK212BJ106K Taiyo Yuden C2 0.1 μF, 6.3 V X5R ceramic capacitor COUT, Photoflash Capacitor 100 μF / 330 V EPH-31ELL101B131S Chemi-Con D1, Output Diode 2 x 250 V, 225 mA, 5 pF BAV23S Philips Semiconductor, Fairchild Semiconductor T1, Transformer LPRIMARY = 12.8 μH, N= 10.25, 6.5 × 8 × 4 mm T-16-024A Tokyo Coil Electric LPRIMARY = 7.8 μH, N= 9.9, 4.6 × 4.6 × 2.4 mm MTF-S2 Union Layout Guidelines Key to a good layout for the photoflash capacitor charger circuit is to keep the parasitics minimized on the power switch loop (transformer primary side) and the rectifier loop (secondary side). Use short, thick traces for connections to the transformer primary and SW pin. It is important that the ¯D¯ N¯ ¯E¯ signal trace and other signal traces be routed away from the transformer and other switching traces, in order to minimize noise pickup. In addition, high voltage isolation rules must be followed carefully to avoid breakdown failure of the circuit board. Avoid placing any ground plane area underneath the transformer secondary and diode, to minimize parasitic capacitance. For low threshold logic (<1.2 V) add 1 nF capacitors across the CHARGE and TRIGGER pins to GND to avoid malfunction due to noise. Connect the EE package PAD to the ground pad for better ther- mal performance. Use ground planes on the top and bottom layers below the IC and connect them through multiple thermal vias. Refer to the figures on page 18 for recommended layout.
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 Recommended layout: Schematic Top side Bottom side Top components 0.1uF 10uF VBAT TRIGGER CHARGE DONE Cout1 100uF TCE_T-16-024A Rg SW CHARGE GATE DONE VIN_DRV TRIG GND VBAT Vout TP_Gate R10 1 2 BAV23S 1nF C5 1nF A8735
Ultra Small Mobile Phone Xenon Photoflash Capacitor Charger with IGBT Driver 16Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A8735 Copyright ©2010, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Package EE 8-Contact DFN/MLP with Exposed Thermal Pad 1.60 A A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) All dimensions nominal, not for tooling use (reference JEDEC MO-229UCCD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C Reference land pattern layout (reference IPC7351 SON50P200X200X100-9M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) B PCB Layout Reference View 0.90 1.60 0.30 8 0.50 0.83 2.13 C 0.90 0.55 +0.05 –0.04 2.00 ±0.15 2.00 ±0.15 0.25 ±0.05 0.325 ±0.050
0.50 BSC
C0.08 D D Coplanarity includes exposed thermal pad and terminals CSEATING PLANE