A8502

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Technical content

Figure 1. Application with VIN to ground short protection, using optional P-MOSFET sensing

Description

The A8502 is a multi-output white LED driver for small-size LCD backlighting. It integrates a current-mode boost converter with internal power switch and two current sinks. The boost converter can drive up to 24 LEDs, 12 LEDs per string, at 120 mA. The LED sinks can be paralleled together to achieve even higher LED currents, up to 240 mA. The A8502 can operate with a single power supply, from 5 to 40 V , which allows the part to withstand load dump conditions encountered in automotive systems. If required, the A8502 can drive an external P-FET to disconnect the input supply from the system in the event of a fault. The A8502 provides protection against output short and overvoltage, open or shorted diode, open or shorted LED pin, shorted boost switch or inductor, shorted FSET or ISET resistor, and IC overtemperature. A dual level cycle-by-cycle current limit function provides soft start and protects the internal current switch against high current overloads. The A8502 has a synchronization pin that allows PWM switching frequencies to be synchronized in the range of 580 kHz to 2.3 MHz. The high switching frequency allows the A8502 to operate above the AM radio band. A8502-DS, Rev. 3 Features and Benefits

• AEC-Q100 qualified
• Wide input voltage range of 5 to 40 V for start/stop, cold crank and load dump requirements
• Fully integrated LED current sinks and boost converter with 60 V DMOS
• Sync function to synchronize boost converter switching frequency up to 2.3 MHz, allowing operation above the AM band
• Excellent input voltage transient response
• Single resistor primary OVP minimizes V OUT leakage
• Internal secondary OVP for redundant protection
• LED current of 120 mA per channel
• Drives up to 12 series LEDs in 2 parallel strings
• 0.7% to 0.8% LED to LED matching accuracy
• PWM and analog dimming inputs
• 5000:1 PWM dimming at 200 Hz
• Provides driver for optional external PMOS input disconnect switch
• Extensive protection against: ▫ Shorted boost switch or inductor ▫ Shorted FSET or ISET resistor ▫ Shorted output ▫ Open or shorted LED pin ▫ Open boost Schottky ▫ Overtemperature (OTP) Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver Package: 16-pin TSSOP with exposed thermal pad (suffix LP) Applications: LCD backlighting or LED lighting for: ▫ Automotive infotainment ▫ Automotive cluster ▫ Automotive center stack Typical Application Circuit Not to scale A8502 Continued on the next page… GATE SW D1L1 CVDD OVP VOUT ROVP COUT RSC RADJ VSENSE VIN VDD PWM/EN APWM ISET FSET/SYNC AGND PGND COMP CP RZ CZ LED2 LED1 FAULT PAD A8502 120 Ω VC 10 μH 2 A / 60 V 137 kΩ 0.033 Ω 249 Ω 100 kΩ RISET 8.25 kΩ RFSET 10 kΩ 4.7 μF 50 V CIN 4.7 μF 50 V CC 22 nFRC 20 Ω 0.1 μF 0.47 μF 120 pF VIN 10 to 14 V

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 2Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. Absolute Maximum Ratings* Characteristic Symbol Notes Rating Unit LEDx Pins –0.3 to 55 V OVP Pin –0.3 to 60 V VIN, VSENSE, GATE Pins VSENSE and GATE pins should not exceed VIN by more than 0.4 V –0.3 to 40 V SW Pin Continuous –0.6 to 62 V t < 50 ns –1.0 V ISET, FSET, APWM, COMP Pins –0.3 to 5.5 V All Other Pins –0.3 to 7 V Operating Ambient Temperature T A Range K –40 to 125 ºC Maximum Junction Temperature T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC *Stresses beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability. Selection Guide Part Number Packing* A8502KLPTR-T 4000 pieces per 13-in. reel *Contact Allegro® for additional packing options The A8502 is provided in a 16-pin TSSOP package (suffix LP) with an exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin lead frame plating. Description (continued) Table of Contents Specifications 2 Pin-out Diagram and Terminal List 3 Characteristic Performance 8 Functional Description 11 Enabling the IC 11 Powering up: LED pin short-to-ground check 11 Soft start function 13 Frequency selection 13 Sync 14 LED current setting and LED dimming 15 PWM dimming 15 APWM pin 16 Analog dimming 18 LED short detect 18 Overvoltage protection 18 Boost switch overcurrent protection 21 Input overcurrent protection and disconnect switch 22 Setting the current sense resistor 23 Input UVLO 23 VDD 23 Shutdown 24 Fault protection during operation 24 Application Information 26 Design Example for Boost Configuration 26 Design Example for SEPIC Configuration 30 Package Outline Drawing 34

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Pin-out Diagram Terminal List Table Number Name Function 1 VDD Output of internal LDO; connect a 0.1 μF decoupling capacitor between this pin and ground. 2 PGND Power ground for internal DMOS device.

3 OVP Overvoltage Condition (OVP) sense; connect the ROVP resistor from VOUT to this pin to

adjust the overvoltage protection. 4 SW The drain of the internal DMOS switch of the boost converter. 5 GATE Output gate driver pin for external P-channel FET control.

6 VSENSE

Connect this pin to the negative sense side of the current sense resistor R SC. The threshold voltage is measured as VIN – VSENSE . There is also a fixed current sink to allow for trip threshold adjustment. 7 VIN Input power to the A8502 as well as the positive input used for current sense resistor. Indicates a fault condition. Connect a 100 kΩ resistor between this pin and the required logic level voltage. The pin is an open drain type configuration that will be pulled low when a fault occurs. 9 COMP Output of the error amplifier and compensation node. Connect a series R Z-CZ network from this pin to ground for control loop compensation. 10 APWM Analog trimming option for dimming. Applying a digital PWM signal to this pin adjusts the internal ISET current. 11 PWM/EN PWM dimming pin, used to control the LED intensity by using pulse width modulation. Also used to enable the A8502.

12 FSET/SYNC

Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching frequency. This pin can also be used to synchronize two or more A8502s in the system. The maximum synchronization frequency is 2.3 MHz.

13 ISET Connect the R

ISET resistor between this pin and ground to set the 100% LED current. 14 AGND LED signal ground. 15 LED1 Connect the cathode of the LED string to this pin. 16 LED2 Connect the cathode of the LED sring to this pin. –P A D Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad. Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance RθJA On 2-layer PCB, 3 in.2 48.5 ºC/W On 4-layer PCB based on JEDEC standard 34 ºC/W *Additional thermal information available on the Allegro website VDD PGND OVP SW GATE VSENSE VIN FAULT LED2 LED1 AGND ISET FSET/SYNC PWM/EN APWM COMP PAD

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Functional Block Diagram VDD Regulator UVLO Internal Soft Start Enable PWM Thermal Shutdown Open/Short LED Detect ISET Fault LED Driver 1.235 V Ref Driver Circuit Internal VCC Internal VCC VREF Internal VCC VREF VREF ISS ISS IADJ GOFF 100 kΩ AGND Current Sense Input Current Sense Amplifier PMOS Driver Diode Open Sense OVP Sense Oscillator SW VIN FSET/SYNC COMP VSENSE GATE PWM/EN APWM PAD PGND AGND ISET OVP LED2 LED1 FAULT AGND PGND ∑ + Fault Fault Fault

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS1,2 Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit Input Voltage Specifications Operating Input Voltage Range3 VIN 5 – 40 V UVLO Start Threshold V UVLOrise VIN rising − – 4.35 V UVLO Stop Threshold V UVLOfall VIN falling − – 3.90 V UVLO Hysteresis2 VUVLOHYS 300 450 600 mV Input Currents Input Quiescent Current I Q PWM/EN = VIH ; SW = 2 MHz, no load − 5.5 10 mA Input Sleep Supply Current I QSLEEP VIN = 16 V, VPWMEN = VFSETSYNC = 0 V − 2.0 10.0 μA Input Logic Levels (PWM/EN and APWM) Input Logic Level-Low V IL VIN throughout operating input voltage range – – 400 mV Input Logic Level-High V IH VIN throughout operating input voltage range 1.5 – – V PWM/EN Pin Open Drain Pull-down Resistor RPWMEN PWM/EN = 5 V 60 100 140 k Ω APWM Pull-down Resistor R APWM PWM/EN = VIH 60 100 140 k Ω APWM APWM Frequency2 fAPWM VIH = 2 V, VIL = 0 V 20 − 1000 kHz Error Amplifier Open Loop Voltage Gain A VOL 44 48 52 dB Transconductance g m ΔICOMP = ±10 μA 750 990 1220 μA/V Source Current I EA(SRC) VCOMP = 1.5 V − –350 −μ A Sink Current I EA(SINK) VCOMP = 1.5 V − 350 −μ A COMP Pin Pull-down Resistance R COMP ¯F¯ ¯A ¯U ¯¯L¯ ¯T¯ = 0 − 2000 −Ω Overvoltage Protection Overvoltage Threshold V OVP(th) OVP connected to VOUT 7.7 8.1 8.5 V OVP Sense Current I OVPH 188 199 210 μA OVP Leakage Current I OVPLKG ROVP = 40.2 kΩ, VIN = 16 V, PWM/EN = VIL − 0.1 1 μA Secondary Overvoltage Protection V OVP(sec) 53 55 58 V Boost Switch Switch On-Resistance R SW ISW = 0.750 A, VIN = 16 V 75 300 600 m Ω Switch Leakage Current I SWLKG VSW = 16 V, PWM/EN = VIL − 0.1 1 μA Switch Current Limit I SW(LIM) 3.0 3.5 4.2 A Secondary Switch Current Limit2 ISW(LIM2) Higher than ISW(LIM)(max) for all conditions, device latches when detected − 7.00 − A Soft Start Boost Current Limit I SWSS(LIM) Initial soft start current for boost switch − 700 − mA Minimum Switch On-Time t SWONTIME 60 85 111 ns Minimum Switch Off-Time t SWOFFTIME 30 47 68 ns Continued on the next page…

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Oscillator Frequency Oscillator Frequency f SW RFSET = 10 kΩ 1.8 2 2.2 MHz RFSET = 20 kΩ 0.9 1 1.1 MHz RFSET = 35.6 kΩ 520 580 640 kHz FSET/SYNC Pin Voltage V FSET RFSET = 10 kΩ− 1.00 − V FSET Frequency Range f FSET 580 − 2500 kHz Synchronization Synchronized PWM Frequency f SWSYNC 580 − 2300 kHz Synchronization Input Minimum Off-Time tPWSYNCOFF 150 −− ns Synchronization Input Minimum On-Time tPWSYNCON 150 −− ns SYNC Input Logic Voltage VSYNC(H) FSET/SYNC pin, high level −− 0.4 V VSYNC(L) FSET/SYNC pin, low level 2.0 −− V LED Current Sinks LEDx Accuracy Err LED ISET = 120 μA −− 2% LEDx Matching ΔLEDx I SET = 120 μA −− 1% LEDx Regulation Voltage V LED VLED1 = VLED2 , ISET = 120 μA 620 720 820 mV ISET to ILEDx Current Gain A ISET ISET = 120 μA 960 980 1000 A/A ISET Pin Voltage V ISET 0.988 1.003 1.018 V Allowable ISET Current I SET 40 − 120 μA VLED Short Detect V LEDSC While LED sinks are in regulation, sensed from LEDx pin to ground 4.6 5.1 5.6 V Soft Start LEDx Current I LEDSS Current through each enabled LEDx pin during soft start − 3.2 − mA Maximum PWM Dimming Until Off-Time2 tPWML Measured while PWM/EN = low, during dimming control and internal references are powered-on (exceeding t PWML results in shutdown) − 32,750 − fSW cycles Minimum PWM On-Time t PWMH First cycle when powering-up device − 0.75 2 μs PWM High to LED-On Delay t dPWM(on) Time between PWM enable and LED current reaching 90% of maximum − 0.5 1 μs PWM Low to LED-Off Delay t dPWM(off) Time between PWM enable going low and LED current reaching 10% of maximum − 360 500 ns ELECTRICAL CHARACTERISTICS1,2 (continued) Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit Continued on the next page…

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS1,2 (continued) Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit GATE Pin GATE Pin Sink Current I GSINK VGS = VIN −− 104 −μ A Gate Fault Shutdown Greater than 2X Current2 tGFAULT2 −− 3 μs Gate Fault Shutdown Greater than 1–2X Current tGFAULT1 − 10,000 − fSW cycles Gate Voltage V GS Gate to source voltage measured when gate is on − –6.7 − V VSENSE Pin VSENSE Pin Sink Current I ADJ 18.8 20.3 21.8 μA VSENSE Trip Point V SENSEtrip1 Measured between VIN and VSENSE, RADJ = 0 Ω 94 104 114 mV VSENSE 2X Trip2 VSENSEtrip2 2X VSENSEtrip , instantaneous shutdown, RADJ = 0 Ω – 180 – mV ¯F¯ ¯A ¯U ¯¯L¯ ¯T¯ Pull-Down Voltage V FAULT IFAULT = 1 mA −− 0.5 V ¯F¯ ¯A ¯U ¯¯L¯ ¯T¯ Pin Leakage Current I FAULTLKG VFAULT = 5 V −− 1 μA Thermal Protection (TSD) Thermal Shutdown Threshold

2 TSD Temperature rising − 165 − ºC

Thermal Shutdown Hysteresis2 TSDHYS − 20 − ºC 1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). 2Ensured by design and characterization, not production tested. 3Minimum VIN = 5 V is only required at startup. After startup is completed, the IC is able to function down to VIN = 4 V.

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 7.7 7.6 7.8 7.9 8.0 8.1 8.2 8.3 8.4 VOVP(th) (V) 190 192 194 196 198 200 202 204 206 208 210 IOVPH (μA) 3.60 3.61 3.62 3.63 3.64 3.65 3.66 3.67 3.68 3.69 3.70 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 fSW (MHz) Switching Frequency OVP Pin Sense Current OVP Pin Overvoltage Threshold 4.00 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 VUVLOrise (V)VUVLOfall (V) IQSLEEP (μA) VIN Input Sleep Mode Current versus Ambient Temperature VIN UVLO Start Threshold Voltage VIN UVLO Stop Threshold Voltage versus Ambient Temperature versus Ambient Temperature versus Ambient Temperature versus Ambient Temperature versus Ambient Temperature Temperature (°C) Temperature (°C) Temperature (°C) Temperature (°C) Temperature (°C) Temperature (°C) Characteristic Performance TA = TJ

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300 3.0 2.5 2.0 1.5 1.0 0.5 ErrLED (%) LED Current Setpoint Accuracy -6.9 -6.8 -6.7 -6.6 -6.5 -6.4 -6.3 VGS (V) Input Disconnect Switch Voltage Gate to Source 118.2 118.0 117.8 117.6 117.4 117.2 117.0 ILED (mA) ISET = 120 μA ISET = 120 μA -0.5 -0.3 -0.1 0.1 0.3 0.5 $LEDx (%) LED to LED Matching Accuracy 960 965 970 975 980 985 990 995 1000 AISET Temperature (°C) Temperature (°C) Temperature (°C) Temperature (°C) Temperature (°C) ISET to LED Current Gain versus Ambient Temperature versus Ambient Temperature LED Current versus Ambient Temperature versus Ambient Temperature versus Ambient Temperature 20.0 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 IADJ (μA) VSENSE Pin Sink Current Temperature (°C) versus Ambient Temperature

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. 100 Efficiency (%) 100 Efficiency (%) Input Voltage, VIN (V) Efficiency for Various LED Configurations ILED = 80 mA, LED Vf ≈ 3.2 V Efficiency for Various LED Configurations ILED = 100 mA, LED Vf ≈ 3.2 V Input Voltage, VIN (V) 2 strings, 6 series LEDs each 2 strings, 7 series LEDs each 2 strings, 8 series LEDs each 2 strings, 6 series LEDs each 2 strings, 7 series LEDs each 2 strings, 8 series LEDs each

11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. cally 0.72 V at the maximum LED current). Figure 2. Power-up diagram; shows VDD (ch1, 2 V/div.), FSET/SYNC (ch2, Figure 3. Power-up diagram; shows the relationship of an LEDx pin with

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. 4A. An LED detect occurring when both LED pins are selected to be used; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 μs/div. 4B. Example with LED2 pin not being used; the detect voltage is about 150 mV; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 μs/div. 4C. Example with one LED shorted to ground. The IC will not proceed with power-up until the shorted LED pin is released, at which point the LED is checked to see if it is being used; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 1 ms/div. t LED detection period PWM/EN LED2 LED1 ISET t Pin shorted Short removed PWM/EN LED2 LED1 ISET t LED detection period PWM/EN LED2 LED1 ISET frequency, as shown in the following table: Switching Frequency (MHz) Detection Time (ms) 2 1.5 to 2 1 3 to 4 0.800 3.75 to 5 0.600 5 to 6.7 The LED pin detection voltage thresholds are as follows: LED Pin Voltage LED Pin Status Action <70 mV Short-to-ground Power-up is halted 150 mV Not used LED removed from operation 325 mV LED pin in use None All unused pins should be connected with a 1.54 kΩ resistor to ground, as shown in figure 5. The unused pin, with the pull-down resistor, will be taken out of regulation at this point and will not contribute to the boost regulation loop.

13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. trolled amount of current through the LEDs. the inrush current generated by charging the output capacitors. necessary output power to the LEDs. This is shown in figure 6. more details see the Fault Mode table later in this datasheet. Figure 5. Channel select setup: (left) using only channel LED1, (right) using both channels. Figure 6. Startup diagram showing the input current, output voltage, and (ch3, 20 V/div.), and PWM/EN (ch4, 5 V/div.), time = 1 ms/div. Figure 7. Typical Switching Frequency versus value of RFSET resistor.

14Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. detected, will the A8502 try to power-up. to the externally preset switching frequency. at any time after 7 μs, the A8502 will proceed to soft start. Figure 9. Transition of the SW waveform when the SYNC pulse is 2 V/div.), and SW node (ch4, 20 V/div.), time = 5 μs/div. Figure 8. Diagram showing a synchronized FSET/SYNC pin and switch (ch3, 2 V/div.), and SW node (ch4, 20 V/div.), time = 2 μs/div.

2 MHz operation 1 MHz operationFSET/SYNC

Figure 10. SYNC pulse on and off time requirements.

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. LED current setting and LED dimming The maximum LED current can be up to 120 mA per channel, and is set through the ISET pin. To set the I LED current, connect a resistor, RISET, between this pin and ground, according to the following formula: R ISET = (1.003 × 980) / ILED (2) where ILED is in A and RISET is in Ω. This sets the maximum cur- rent through the LEDs, referred to as the 100% current. Standard RISET values, at gain equals 980, are as follows: Standard Closest RISET Resistor Value (kΩ) LED current per LED, ILED (mA) 8.25 120 9.76 100 12.1 80 15.0 65 PWM dimming The LED current can be reduced from the 100% current level by PWM dimming using the PWM/EN pin. When the PWM/EN pin is pulled high, the A8502 turns on and all enabled LEDs sink 100% current. When PWM/EN is pulled low, the boost converter and LED sinks are turned off. The compensation (COMP) pin is floated, and critical internal circuits are kept active. The typical PWM dimming frequencies fall between 200 Hz and 1 kHz. Fig- ures 11A to 11D provide examples of PWM switching behavior. Figure 11A. Typical PWM diagram showing VOUT, ILED, and COMP pin as well as the PWM signal. PWM dimming frequency is 500 Hz at 50% duty cycle; shows V OUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3, 5 V/div.), and ILED (ch4, 50 mA/div.), time = 500 μs/div. t ILED PWM COMP VOUT Figure 11B. Typical PWM diagram showing VOUT, ILED, and COMP pin as well as the PWM signal. PWM dimming frequency is 500 Hz at 1% duty cycle ; shows V OUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3, 5 V/div.), and ILED (ch4, 50 mA/div.), time = 500 μs/div. Figure 11D. Delay from falling edge of PWM signal to LED current turn off; shows PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), time = 200 ns/div. Figure 11C. Delay from rising edge of PWM signal to LED current; shows PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), time = 200 ns/div. t ILED PWM t ILED PWM COMP VOUT t ILED PWM

16Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. current. When this pin is not used it should be tied to ground. The typical input signal frequency is between 20 kHz and 1 MHz. centage of current that is delivered to the LEDs (figure 14). cycles that are between 25% and 50%. Figure 13. Simplified block diagram of the APWM and ISET circuit. Figure 14. Output current versus duty cycle; 200 kHz APWM signal. Figure 15. Percentage Error of the LED current versus PWM duty cycle; Figure 12. Percentage Error of the LED current versus PWM duty cycle

17Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Figure 16. Diagram showing the transition of LED current from 120 mA PWM/EN (ch3, 5 V/div.), time = 500 μs/div. Figure 17. Diagram showing the transition of LED current from 90 mA to 120 mA, when a 25% duty cycle signal is removed from the APWM pin. PWM/EN (ch3, 5 V/div.), time = 500 μs/div. Figure 18. Transition of output current level when a 50% duty cycle signal APWM (ch2, 5 V/div.), and PWM/EN (ch3, 5 V/div.), time = 1 ms/div.

18Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A.

• For a single resistor (panel A of figure 18), the ISET current is controlled by the following formula: ISET = VISET – VDAC RISET (3) where VISET is the ISET pin voltage and VDAC is the DAC output voltage. When the DAC voltage is 0 V the LED current will be at its maximum. To keep the internal gain amplifier stable, the user should not decrease the current through the R ISET resistor to less than 40 μA
• For a dual-resistor configuration (panel B of figure 19), the ISET current is controlled by the following formula: ISET = – VISET RISET VDAC – VISET (4) The advantage of this circuit is that the DAC voltage can be higher or lower, thus adjusting the LED current to a higher or lower value of the preset LED current set by the R ISET resistor: ▫ VDAC = 1.003 V; the output is strictly controlled by RISET ▫ VDAC > 1.003 V; the LED current is reduced ▫ VDAC < 1.003 V; the LED current is increased LED short detect Both LEDx pins are capable of handling the maximum VOUT that the converter can deliver, thus providing protection from the LEDx pin to V OUT in the event of a connector short. An LEDx pin that has a voltage exceeding VLEDSC will be removed from operation (see figure 20). This is to prevent the IC from dissipating too much power by having a large voltage pres- ent on an LEDx pin. While the IC is being PWM-dimmed, the IC rechecks the dis- abled LED every time the PWM signal goes high, to prevent false tripping of an LED short event. This also allows some self-cor- rection if an intermittent LED pin short to V OUT is present. Overvoltage protection The A8502 has overvoltage protection (OVP) and open Schottky diode (D1 in figure 1) protection. The OVP protection has a

Figure 19. Simplified diagrams of voltage control of ILED: typical Figure 20. Example of the disabling of an LED string when the LED pin (ch2, 5 V/div.), and PWM/EN (ch3, 5 V/div.), time = 10 μs/div.

19Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. comparator goes low and the boost stops switching. IOVPH is the current into the OVP pin. are provided in figures 21 and 22. duration until the OVP threshold is hit again. switching, and the open LED string is removed from operation. resume switching and the A8502 will resume normal operation. Figure 21. OVP protection in an output disconnect event; shows VOUT LED (ch4, 200 mA/div.), time = 1 ms/div. Figure 22. OVP protection in an open LED string event; shows VOUT LED (ch4, 200 mA/div.), time = 500 μs/div.

20Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. the UVLO threshold on the VIN pin. Figure 23 illustrates this. above the trip point voltage. Figure 23. OVP protection in an open Schottky diode event, while the IC is OUT (ch3, 20 V/div.), and IOUT (ch4, 200 mA/div.), time = 1 μs/div. Figure 24. OVP protection when the IC is enabled during an open diode

21Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Figure 25. Normal operation of the switch node (SW); inductor current Figure 26. Cycle-by-cycle current limiting; inductor current (yellow trace, IL), Figure 27. Secondary boost switch current limit; when this limit is hit, the

22Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A.

• Drain-source breakdown voltage V (BR)DSS > –40 V
• Gate threshold voltage (make sure it is fully conducting at VGS = -4 V , and cut-off at –1 V)
• RDS(on): Make sure the on-resistance is rated at VGS = -4.5 V or similar, not at -10 V; derate it for higher temperature The input disconnect switch has two modes of operation:
• 1X mode When the input current is between one and two times the preset current limit value, the disconnect switch enters a con- stant-current mode for a maximum duration of 10,000 cycles or 5 ms at 2 MHz. During this time, the Fault flag is set immediately and the disconnect switch goes into a linear mode of operation, in which the input current will be limited to a value approximate to the 1X current trip point level (figure 29). If the fault corrects itself before the expiration of the timer, the Fault flag will be removed and normal operation will resume. The user can also during this time decide whether to shut down the A8502. To immediately shut down the device, pull the FSET/ SYNC pin low for more than 7 μs. After the FSET/SYNC pin has been low for a period longer than 7 μs, the IC will stop switching, the input disconnect switch will open, and the LEDx pins will stop sinking current. The A8502 can be powered-down into low power mode. To do so, disable the IC by keeping the PWM/EN pin low for a period of 32,750 clock cycles. To keep the discon-

Figure 28. Typical circuit showing the implementation of the input Figure 29. Showing typical wave forms for a 3-A, 1X current limit under a div.), GATE (ch3, 5 V/div.), and PWM/EN (ch4, 5 V/div.), time = 5 ms/div. Figure 30. 2X mode, secondary overcurrent fault condition. IIN is the input IN (ch3, 2 A/div.), and PWM/EN (ch4, 5 V/div.), time = 5 μs/div.

23Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. a 22 nF capacitor for CC and a 20 Ω resistor for RC.

• 2X current limit If the input current level goes above 2X of the preset current limit threshold, the A8502 will shut down in less than 3 μs regardless of user input (figure 30). This is a latched condition. The Fault flag is also set to indicate a fault. This feature is meant to prevent catastrophic failure in the system due to inductor short to ground, switch pin short to ground, or output short to ground. Setting the current sense resistor The typical threshold for the current sense circuit is 104 mV , when R ADJ is 0 Ω. This voltage can be trimmed by the RADJ resistor. The typical 1X trip point should be set at about 3 A, which coincides with the cycle-by-cycle current limit minimum threshold. For example, given 3 A of input current, and the calculated maxi- mum value of the sense resistor, R SC = 0.033 Ω. The RSC chosen is 0.03 Ω, a standard. Also: R ADJ = (VSENSETRIP – VADJ ) / IADJ (6) The trip point voltage is calculated as: VADJ = 3.0 A × 0.03 Ω = 0.090 V Input UVLO When VIN and VSENSE rise above the VUVLOrise threshold, the A8502 is enabled. A8502 is disabled when VIN falls below the VUVLOfall threshold for more than 50 μs. This small delay is used to avoid shutting down because of momentary glitches in the input power supply. When V IN falls below 4.35 V , the IC will shut down (see figure 31). VDD The VDD pin provides regulated bias supply for internal circuits. Connect the capacitor C VDD with a value of 0.1 μF or greater to this pin. The internal LDO can deliver no more than 2 mA of cur- rent with a typical V DD of about 3.5 V , enabling this pin to serve as the pull-up voltage for the ¯F¯ ¯A¯ ¯U¯ ¯L¯ ¯T¯ pin.

Figure 31. Shutdown showing a falling input voltage (VIN); shows VIN (ch4, 2 V/div.), time = 5 ms/div. Figure 32. Shutdown using the enable function, showing the 16 ms

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 24Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Shutdown If the PWM/EN pin is pulled low for more than tPWML (32,750 clock cycles), the device enters shutdown mode and clears all internal fault registers. As an example, at a 2 MHz clock fre- quency, it will take approximately 16.3 ms to shut down the IC into the low power mode (figure 32). When the A8502 is shut down, the IC will disable all current sources and wait until the PWM/EN signal goes high to re-enable the IC. If faster shut down is required, the FSET/SYNC pin can be used. Fault protection during operation The A8502 constantly monitors the state of the system to deter- mine if any fault conditions occur during normal operation. The response to a triggered fault condition is summarized in the Fault Mode table. The possible fault conditions that the device can detect are: Open LED pin, LED pin shorted to ground, shorted inductor, V OUT short to ground, SW pin shorted to ground, ISET pin shorted to ground, and input disconnect switch source shorted to ground. Note the following:

• Some of the protection features might not be active during startup, to prevent false triggering of fault conditions.
• Some of these faults will not be protected if the input disconnect switch is not being used. An example of this is V OUT short to ground. Fault Mode Table Fault Name Type Active Fault Flag Set Description Boost Disconnect switch Sink driver Primary switch overcurrent protection (cycle-by-cycle current limit) Auto-restart Always No This fault condition is triggered by the cycle-by- cycle current limit, ISW(LIM). Off for a single cycle On On Secondary switch current limit Latched Always Yes When the current through the boost switch exceeds secondary current SW limit (ISW(LIM2)) the device immediately shuts down the disconnect switch, LED drivers, and boost. The Fault flag is set. To re- enable the device, the PWM/EN pin must be pulled low for 32,750 clock cycles. Off Off Off Input disconnect current limit Latched Always Yes The device is immediately shut off if the voltage across the input sense resistor is 2X the preset current value. The Fault flag is set. If the input current limit is between 1X and 2X, the Fault flag is set but the IC will continue to operate normally for t GFAULT1 or until it is shut down. To re-enable the device the PWM/EN pin must be pulled low for 32,750 clock cycles. Off Off Off Secondary OVP Latched Always Yes Secondary overvoltage protection is used for open diode detection. When diode D1 opens, the SW pin voltage will increase until V OVP(SEC) is reached. This fault latches the IC. The input disconnect switch is disabled as well as the LED drivers, and the Fault flag is set. To re-enable the part the PWM pin must be pulled low for 32,750 clock cycles. Off Off Off Continued on the next page…

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 25Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Fault Mode Table (continued) Fault Name Type Active Fault Flag Set Description Boost Disconnect Switch Sink driver LED Pin Short Protection Auto-restart Startup No This fault prevents the device from starting-up if either of the LEDx pins are shorted. The device stops soft-start from starting while either of the LEDx pins are determined to be shorted. After the short is removed, soft-start is allowed to start. Off On Off LED Pin open Auto-restart Normal Operation No When an LEDx pin is open the device will determine which LED pin is open by increasing the output voltage until OVP is reached. Any LED string not in regulation will be turned off. The device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. On On Off for open pins. On for all others. ISET Short Protection Auto-restart Always No This fault occurs when the ISET current goes above 150% of the maximum current. The boost will stop switching, the disconnect switch will turn off, and the IC will disable the LED sinks until the fault is removed. When the fault is removed the IC will try to to regulate to the preset LED current. Off On Off FSET/SYNC Short Protection Auto-restart Always Yes Fault occurs when the FSET/SYNC current goes above 150% of maximum current, about 180 μA. The boost will stop switching, the disconnect switch will turn off, and the IC will disable the LED sinks until the fault is removed. When the fault is removed the IC will try to restart with soft-start. Off Off Off Overvoltage Protection Auto-restart Always No Fault occurs when OVP pin exceeds V OVP(th) threshold. The A8502 will immediately stop switching to try to reduce the output voltage. If the output voltage decreases then the A8502 will restart switching to regulate the output voltage. Stop during OVP event. On On LED Short Protection Auto-restart Always No Fault occurs when the LED pin voltage exceeds V LEDSC. When the LED short protection is detected the LED string that is above the threshold will be removed from operation. On On Off for shorted pins. On for all others. Overtemperature Protection Auto-restart Always No Fault occurs when the die temperature exceeds the overtemperature threshold, 165°C. Off Off Off VIN UVLO Auto-restart Always No Fault occurs when V IN drops below VUVLO , 3.90 V maximum. This fault resets all latched faults. Off Off Off

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 26Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A.

Application Information

Design Example for Boost Configuration This section provides a method for selecting component values when designing an application using the A8502. The resulting design is diagrammed in figure 33. Assumptions: For the purposes of this example, the following are given as the application requirements:

• V BAT: 10 to 14 V
• Quantity of LED channels, #CHANNELS : 2
• Quantity of series LEDs per channel, #SERIESLEDS : 10
• LED current per channel, ILED : 120 mA
• LED Vf at 120 mA: 3.2 V
• fSW : 2 MHz
• TA(max): 65°C
• PWM dimming frequency: 200 Hz, 1% duty cycle Procedure: The procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. Step 1 Connect LEDs to pins LED1 and LED2. Step 2 Determining the LED current setting resistor RISET: RISET = (VISET × AISET) / ILED (7) Choose a 8.25 kΩ resistor. Step 3 Determining the OVP resistor. The OVP resistor is connected between the OVP pin and the output voltage of the converter. Step 3a The first step is determining the maximum voltage based on the LED requirements. The regulation voltage, VLED , of the A8502 is 720 mV . A constant term, 2 V , is added to give margin to the design due to noise and output voltage ripple. V OUT(OVP) = #SERIESLEDS × Vf + VLED + 2 (V) (8) = 34.72 V Then the OVP resistor is: ROVP = (VOUT(OVP) – VOVP(th) ) / IOVPH (9) = (34.72 V – 8.1 V) / 199 μA = 133.77 kΩ where both I OVPH and VOVP(th) are taken from the Electrical Characteristics table. Chose a value of resistor that is higher value than the calculated ROVP . In this case a value of 137 kΩ was selected. Below is the actual value of the minimum OVP trip level with the selected resistor: V Step 3b At this point a quick check must be done to determine if the conversion ratio is acceptable for the selected frequency. Dmaxofboost = 1 – tSWOFFTIME × fSW (10) where the minimum off-time (tSWOFFTIME) is found in the Electri- cal Characteristics table. The Theoretical Maximum VOUT is then calculated as: VOUT(max) Vd=– 1 – Dmaxofboost VIN(min) 10 (V) (11) where Vd is the diode forward voltage. The Theoretical Maximum VOUT value must be greater than the value VOUT(OVP) . If this is not the case, the switching frequency of the boost converter must be reduced to meet the maximum duty cycle requirements. Step 4 Selecting the inductor. The inductor must be chosen such that it can handle the necessary input current. In most applica- tions, due to stringent EMI requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range.

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 27Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Step 4a Determining the duty cycle, calculated as follows: D(max) Vd VIN(min) VOUT(OVP) 1 – 1 – 10 (V) (12) Step 4b Determining the maximum and minimum input current to the system. The minimum input current will dictate the induc- tor value. The maximum current rating will dictate the current rating of the inductor. First, the maximum input current, given: IOUT = #CHANNELS ILED (13) then: IIN(max) = VIN(min) VOUT(OVP) IOUT H 0.94 A==35.36 (V) 10 (V) 0.90 240 (mA) (14) where η is efficiency. Next, calculate minimum input current, as follows: IIN(min) = VIN(max) VOUT(OVP) IOUT H 0.67 A==35.36 (V) 14 (V) 0.90 240 (mA) (15) A good approximation of efficiency, η , can be taken from the efficiency curves located in the datasheet. A value of 90% is a good starting approximation. Step 4c Determining the inductor value. To ensure that the induc- tor operates in continuous conduction mode, the value of the inductor must be set such that the ½ inductor ripple current is not greater than the average minimum input current. As a first pass assume I ripple to be 40% of the maximum inductor current: ΔIL = IIN(max) × Iripple (16) then: L = VIN(min) D(max)fSWΔIL 2 (MHz) (17) Step 4d Double-check to make sure the ½ current ripple is less than IIN(min): IIN(min) > 1/2 ΔIL (18) 0.67 A > 0.19 A A good inductor value to use would be 10 μH. Step 4e This step is used to verify that there is sufficient slope compensation for the inductor chosen. The slope compensation value is determined by the following formula: 2 10 6Slope Compensation == fSW3.6 3.6 A /μs (19) Next insert the inductor value used in the design: = VIN(min) D(max) fSWLused ΔILused 2.0 (MHz) (20) Calculate the minimum required slope: (1 – D(max)) (1 – 0.72) fSW Required Slope (min) ΔILused 0.36 (A) 10 –6 11 0 –6 == 2.57 A/μs 2.0 (MHz) (21) If the minimum required slope is greater than the calculated slope compensation, the inductor value must be increased. Note: The slope compensation value is in A/μs, and 1×10 –6 is a constant multiplier. Step 4f Determining the inductor current rating. The inductor current rating must be greater than the IIN(max) value plus half of the ripple current ΔIL, calculated as follows: L(min) = IIN(max) + 1/2 ΔILused (22) Step 5 Determining the resistor value for a particular switching frequency. Use the RFSET values shown in figure 7. For example, a 10 kΩ resistor will result in a 2 MHz switching frequency. Step 6 Choosing the proper switching diode. The switching diode must be chosen for three characteristics when it is used in LED lighting circuitry. The most obvious two are: current rating of the diode and reverse voltage rating.

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 28Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. The reverse voltage rating should be such that during operation condition, the voltage rating of the device is larger than the maxi- mum output voltage. In this case it is V OUT(OVP). The peak current through the diode is calculated as: I dp = IIN(max) + 1/2 ΔILused (23) The third major component in deciding the switching diode is the reverse current, I R , characteristic of the diode. This characteristic is especially important when PWM dimming is implemented. During PWM off-time the boost converter is not switching. This results in a slow bleeding off of the output voltage, due to leakage currents. I R can be a large contributor, especially at high tempera- tures. On the diode that was selected in this design, the current varies between 1 and 100 μA. Step 7 Choosing the output capacitors. The output capacitors must be chosen such that they can provide filtering for both the boost converter and for the PWM dimming function. The biggest factors that contribute to the size of the output capacitor are: PWM dimming frequency and PWM duty cycle. Another major contributor is leakage current, I LK . This current is the combina- tion of the OVP leakage current as well as the reverse current of the switching diode. In this design the PWM dimming frequency is 200 Hz and the minimum duty cycle is 1%. Typically, the volt- age variation on the output, V COUT , during PWM dimming must be less than 250 mV , so that no audible hum can be heard. The capacitance can be calculated as follows: COUT = fPWM(dimming) 1 – D(min) 1 – 0.01 200 (Hz) ILK VCOUT (24) A capacitor larger than 3.96 μF should be selected due to degra- dation of capacitance at high voltages on the capacitor. A ceramic 4.7 μF 50 V capacitor is a good choice to fulfill this requirement. Corresponding capacitors include: Vendor Value Part number Murata 4.7 μF 50 V GRM32ER71H475KA88L Murata 2.2 μF 50 V GRM31CR71H225KA88L The rms current through the capacitor is given by: ICOUTrms = 1 – D(max) D(max) + ∆ILused IOUT 0.240 (A) 0.39 A × 12 × 12== IIN(max) 1 – 0.72 0.72 + 0.36 (A) 0.94 (A) (25) The output capacitor must have a current rating of at least 390 mA. The capacitor selected in this design was a 4.7 μF 50 V capacitor with a 3 A current rating. Step 8 Selecting input capacitor. The input capacitor must be selected such that it provides a good filtering of the input voltage waveform. A good estimation rule is to set the input voltage rip- ple, ΔV IN , to be 1% of the minimum input voltage. The minimum input capacitor requirements are as follows: CIN = fSW 0.36 (A) ∆ILused 0.23 μF ∆VIN 2 (MHz) 0.1 (V)8 (26) The rms current through the capacitor is given by: CINrms = (1 – D)× IOUT × ∆ILused 0.095 A = = IIN(max) (1 – 0.72)× 0.94 (A) (27) A good ceramic input capacitor with ratings of 2.2 μF 50 V or 4.7 μF 50 V will suffice for this application. Corresponding capacitors include: Vendor Value Part number Murata 4.7 μF 50 V GRM32ER71H475KA88L Murata 2.2 μF 50 V GRM31CR71H225KA88L

29Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. The RSC chosen is 0.033 Ω, a standard. A value of 249 Ω was chosen for this design.

10 LEDs

Figure 33. The schematic diagram showing calculated values from the design example above.

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 30Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Design Example for SEPIC Configuration This section provides a method for selecting component values when designing an application using the A8502 in SEPIC (Sin- gle-Ended Primary-Inductor Converter) circuit. SEPIC topology has the advantage that it can generate a positive output voltage either higher or lower than the input voltage. The resulting design is diagrammed in figure 34. Assumptions: For the purposes of this example, the following are given as the application requirements:

• V BAT: 6 to 14 V ( VIN(min): 5 V and VIN(max): 16 V )
• Quantity of LED channels, #CHANNELS : 2
• Quantity of series LEDs per channel, #SERIESLEDS : 4
• LED current per channel, ILED : 120 mA
• LED Vf at 120 mA: ≈ 3.3 V
• fSW : 2 MHz
• TA(max): 65°C
• PWM dimming frequency: 200 Hz, 1% duty cycle Procedure: The procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. Step 1 Connect LEDs to pins LED1 and LED2. Note: if only one LED channel is needed, the unused LEDx pin should be pulled to ground using a 1.5 kΩ resistor. Alternatively, short the LED1 and LED2 pins together, and half the LED current, to 60 mA per channel. Step 2 Determining the LED current setting resistor RISET: RISET = (VISET × AISET) / ILED (30) Choose a 8.25 kΩ resistor 1% resistor (or 16.2 kΩ if ILED is 60mA/channel). Step 3 Determining the OVP resistor. The OVP resistor is connected between the OVP pin and the output voltage of the converter. Step 3a The first step is determining the maximum voltage based on the LED requirements. The regulation voltage, VLED , of the A8502 is 720 mV . A constant term, 2 V , is added to give margin to the design due to noise and output voltage ripple. V OUT(OVP) = #SERIESLEDS × Vf + VLED + 2 (V) (31) Then the OVP resistor is: ROVP = (VOUT(OVP) – VOVP(th) ) / IOVPH (32) where both I OVPH and VOVP(th) are taken from the Electrical Characteristics table. In this case a value of 39.2 kΩ was selected. Below is the actual value of the minimum OVP trip level with the selected resistor: Step 3b At this point a quick check must be done to determine if the conversion ratio is acceptable for the selected frequency. Dmax = 1 – tSWOFFTIME × fSW (33) where the minimum off-time (tSWOFFTIME) is found in the Electri- cal Characteristics table. The Theoretical Maximum VOUT is then calculated as: VOUT(max) = Vd– 1 – Dmax Dmax VIN(min) 0.865 (V) (34) where Vd is the diode forward voltage. The Theoretical Maximum VOUT value must be greater than the value VOUT(OVP) . If this is not the case, the switching frequency of the boost converter must be reduced to meet the maximum duty cycle requirements.

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 31Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Step 4 Selecting the inductor. The inductor must be chosen such that it can handle the necessary input current. In most applica- tions, due to stringent EMI requirements, the system must operate in continuous conduction mode throughout the whole input volt- age range. Step 4a Determining the duty cycle, calculated as follows: D(max) Vd Vd+ VOUT(OVP)+VIN(min) VOUT(OVP) + 0.4 (V)15.9 (V) (35) Step 4b Determining the maximum and minimum input current to the system. The minimum input current will dictate the induc- tor value. The maximum current rating will dictate the current rating of the inductor. First, the maximum input current, given: IOUT = #CHANNELS ILED (36) then: IIN(max) = VIN(min) VOUT(OVP) IOUT H 0.848 A== 15.9 (V) 5 (V) 0.90 0.24 (A) (37) where η is efficiency. Next, calculate minimum input current, as follows: IIN(min) = VIN(max) VOUT(OVP) IOUT H 0.265 A==15.9 (V) 16 (V) 0.90 0.24 (A) (38) A good approximation of efficiency, η , can be taken from the efficiency curves located in the datasheet. A value of 90% is a good starting approximation. Step 4c Determining the inductor value. To ensure that the induc- tor operates in continuous conduction mode, the value of the inductor must be set such that the ½ inductor ripple current is not greater than the average minimum input current. As a first pass assume I ripple to be 30% of the maximum inductor current: ΔIL = IIN(max) × Iripple (39) = 0.848 × 0.30 = 0.254 A then: L = VIN(min) D(max)fSWΔIL 2 (MHz) (40) Step 4d Double-check to make sure the ½ current ripple is less than IIN(min): IIN(min) > 1/2 ΔIL (41) 0.265 A > 0.127 A A good inductor value to use would be 10 μH. Step 4e Next insert the inductor value used in the design to deter- mine the actual inductor ripple current: = VIN(min) D(max) fSWLused ΔILused 2.0 (MHz) (42) Step 4f Determining the inductor current rating. The inductor current rating must be greater than the IIN(max) value plus half of the ripple current ΔIL, calculated as follows: L(min) = IIN(max) + 1/2 ΔILused (43) Step 5 Determining the resistor value for a particular switching frequency. Use the RFSET values shown in figure 7. For example, a 10 kΩ resistor will result in a 2 MHz switching frequency. Step 6 Choosing the proper switching diode. The switching diode must be chosen for three characteristics when it is used in LED lighting circuitry. The most obvious two are: current rating of the diode and reverse voltage rating.

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 32Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. The reverse breakdown voltage rating for the output diode in a SEPIC circuit should be: V BD > VOUT(OVP)(max) + VIN(max) (44) because the maximum output voltage in this case is VOUT(OVP). The peak current through the diode is calculated as: I dp = IIN(max) + 1/2 ΔILused (45) The third major component in deciding the switching diode is the reverse current, IR , characteristic of the diode. This characteristic is especially important when PWM dimming is implemented. During PWM off-time the boost converter is not switching. This results in a slow bleeding off of the output voltage, due to leakage currents. I R can be a large contributor, especially at high tempera- tures. On the diode that was selected in this design, the current varies between 1 and 100 μA. It is often advantageous to pick a diode with a much higher breakdown voltage, just to reduce the reverse current. Therefore for this example, pick a diode rated for a V BD of 60 V , instead of just 40 V . Step 7 Choosing the output capacitors. The output capacitors must be chosen such that they can provide filtering for both the boost converter and for the PWM dimming function. The biggest factors that contribute to the size of the output capacitor are: PWM dimming frequency and PWM duty cycle. Another major contributor is leakage current, I LK . This current is the combina- tion of the OVP leakage current as well as the reverse current of the switching diode. In this design the PWM dimming frequency is 200 Hz and the minimum duty cycle is 1%. Typically, the volt- age variation on the output, V COUT , during PWM dimming must be less than 250 mV , so that no audible hum can be heard. The capacitance can be calculated as follows: COUT = fPWM(dimming) 1 – D(min) 1 – 0.01 200 (Hz) ILK VCOUT (46) A capacitor larger than 3.96 μF should be selected due to degra- dation of capacitance at high voltages on the capacitor. Select a 4.7 μF capacitor for this application. The rms current through the capacitor is given by: ICOUTrms = 1 – D(max) D(max)IOUT 0.765 (47) The output capacitor must have a ripple current rating of at least 500 mA. The capacitor selected for this design is a 4.7 μF 50 V capacitor with a 1.5 A current rating. Step 8 Selecting input capacitor. The input capacitor must be selected such that it provides a good filtering of the input voltage waveform. A estimation rule is to set the input voltage ripple, ΔV IN , to be 1% of the minimum input voltage. The minimum input capacitor requirements are as follows: CIN = fSW 0.191 (A) ∆ILused 0.24 μF ∆VIN 2 (MHz) 0.05 (V)8 (48) The rms current through the capacitor is given by: CINrms = ∆ILused 0.055 A = =0.191 (A) (49) A good ceramic input capacitor with a rating of 2.2 μF 25 V will suffice for this application.

33Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Figure 34. Typical application showing SEPIC configuration, designed according to the application example. 2.2 μF 25V will suffice for this application.

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 34Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Package LP, 16-Pin TSSOP with Exposed Thermal Pad A

1.20 MAX

0.15 0.00 0.30 0.19 0.20 0.09 0.60 ±0.15

1.00 REF

C SEATING PLANEC0.10 16X

0.65 BSC

0.25 BSC

5.00±0.10 GAUGE PLANE SEATING PLANE A Terminal #1 mark area B For Reference Only; not for tooling use (reference MO-153 ABT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown B C Exposed thermal pad (bottom surface); dimensions may vary with device 6.10 0.65 0.45 1.70 3.00 3.00 Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) PCB Layout Reference View C Branded Face

3 NOM

Wide Input Voltage Range, High Efficiency Fault Tolerant LED DriverA8502 35Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Copyright ©2011-2012, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com

Revision History

Revision Revision Date Description of Revision Rev. 3 January 16, 2012 Update Features list and g m