A8423

A8423 ALLEGRO

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Subject to Change without Notice February 9, 2004 Datasheet A8423-DS Rev.0 A8423 LIN Bus Transceiver with Integrated Voltage Regulator The A8423 provides the physical interface requirements of the LIN (Local Interconnect Network) serial communications bus plus an inte- grated voltage regulator that is permanently enabled. These allow the development of simple, inexpensive slave nodes in a LIN-Bus system. The LIN transceiver is compatible with LIN-Bus systems that conform to the LIN Protocol Specifi cation, Revision 1.2. It provides all the necessary interface and timing control to convert signals to and from the bidirectional LIN Bus to individual transmit and receive signals at logic-compatible levels. The A8423 provides regulated 5V output with a current limit in excess of 50 mA. This is suffi cient to power a microcontroller handling the LIN slave node protocol. The A8423 is supplied in 8-lead plastic SOIC (part number suffi x L). „ Compatible with LIN Bus, Revision 1.2 systems „ Data rate up to 20 kbaud „ Normal operation from 7 to 30 V „ Handles 40 V transients during load dump „ Handles automotive transients per ISO 7637 „ Unpowered node does not disturb the network „ 4 kV (hbm) ESD protection on LIN and WAKE pins „ Low quiescent current regulator for slave microcontroller supply „ Interface to slave microcontroller „ 8-pin small outline surface mount package Use the following complete part number when ordering: AB SO LUTE MAX I MUM RAT INGS Part Number Package

Description

8-lead, SOIC Continuous voltage regulator Operating Temperature Range

FEATURES

APPLICATIONS

Automotive, industrial, and consumer LIN-Bus systems

Worcester, Massachusetts 01615-0036 (508) 853-5000

115 Northeast Cutoff, Box 15036

www.allegromicro.com Datasheet A8423-DS Rev.0 A8423 LIN Bus Transceiver with Integrated Voltage Regulator Preliminary – Subject to Change Without Notice February 9, 2004 ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150ºC, VSUP = 7 V to 18 V (unless otherwise noted) Characteristics Symbol Test Conditions Min. Typ. Max. Units VSUP Power Supply Operating Voltage Range VSUP Continuous V VSUP Transient; 500 ms V Supply Current ISUP LIN output recessive (High); VWAKE = 0 0.8 mA LIN output dominant (Low); VWAKE= 0 1.5 mA Supply Standby Current ISTBY VWAKE= 0, LIN = N.C. 0.8 mA LIN = Dominant (Low), Wake = N.C. 1.5 mA Supply Sleep Current ISLEEP IREG < 20 µA 100 µA Undervoltage Threshold VSUPUV 4.8 5.0 5.2 V TX and EN Input Low Level Input Voltage VIL 0.8 V High Level Input Voltage VIH V Input Hysteresis VIHYS 300 mV Pull-Down Resistor RPD EN pin 100 200 kΩ Pull-Up Resistor RPU TX pin 100 200 kΩ RX Output Low Level Output Current IOL VRX= 0.4 V 1.5 mA High Level Leakage Current IOH VRX= 5 V µA Wake Input Low Level Input Voltage VIL VSUP –5 V High Level Input Voltage VIH VSUP –1 V Pull-up Current IIL VWAKE= 0 V µA High Level Leakage Current IIH VWAKE= VSUP= 30 V µA VREG Regulated 5V Supply Output Voltage VREG IOUT = 0 to 50 mA 4.5 5.0 5.5 V Output Current Limit IREGLIM VREG = 0 V 180 mA External Decoupling Cap VREG to GND µF Line Regulation IOUT = 30 mA 100 mV Load Regulation VSUP = 13.5 V; IOUT = 1 to 30 mA 100 mV LIN Interface Output Short Circuit Current IOSC 110 mA Output Voltage – Recessive VOR VTX= 5 V; ILIN= 0 mA

0.9 VSUP

V Output Voltage – Dominant VOD VTX= 0 V; ILIN= 40 mA 1.2 V High Level Leakage Current IIH VLIN= VSUP µA Termination Resistance RSLAVE kΩ Input Threshold – Dominant VTHDOM VLIN – Recessive to Dominant

0.4 VSUP

V Input Threshold – Recessive VTHREC VLIN – Dominant to Recessive

0.6 VSUP

V Input Threshold Hysteresis VLINHYS

0.05 VSUP

0.1 VSUP 0.175 VSUP V

1Slew rate is controlled during both transitions and will not exceed specifi ed limits at any point between test limits. Figure 1. Propagation timing defi nition Figure 2. Slew rate defi nition

ance state on the LIN terminal. greater than the undervoltage threshold. connected or becomes disconnected. output as a logic level on the RX pin. This pin is open drain. that the bus has become active. Figure 3. Operating state. Active is true (T) if WAKE is low (L) or if LIN is low (L). Otherwise, Active is false (F). 2Z = High Impedance, * = Don’t Care.

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Datasheet A8423-DS Rev.0 A8423 LIN Bus Transceiver with Integrated Voltage Regulator Preliminary – Subject to Change Without Notice February 9, 2004 or one of the two inactive modes, Standby or Sleep, are entered (EN low). If no other wake-up signals are active, EN low sets the A8423 into low-current Sleep mode. From Sleep mode the A8423 can be put directly into Normal mode by taking EN high. Alternatively, it can be taken into Standby mode by pulling the WAKE input to ground or by a dominant state on the LIN Bus. In Sleep mode, the supply current is at its minimum level, and the LIN and RX pins are high impedance. In this mode, the linear regulator is still active. When the power is fi rst applied, the A8423 enters Sleep mode directly. From Sleep mode, the A8423 may be taken through the Standby mode, in which the RX output goes low to wake up the protocol control device attached to the TX, RX, and EN pins. Once the controller is active, it may then bring the A8423 into Normal mode by taking EN high. If there is no need to wake the controller prior to enabling the A8423, then simply asserting EN high moves the A8423 directly from Sleep mode to Normal mode. The EN input has an internal pull-down resistor to ensure a known safe state when the protocol controller is powered off. The WAKE signal is a high-voltage input, which is designed to allow a node on a sleeping bus to be awaken by a local event. Sleep mode may be entered when WAKE is connected directly to the battery or other similar voltage, such as VSUP. To disable Sleep mode and allow the A8423 to enter Standby mode, the WAKE input should be switched to ground. The A8423 incorporates two protection functions. If the die temperature becomes excessive, a thermal shutdown feature (TSD) disables the LIN output dominant-state drive. Once the temperature falls below the hysteresis level, the LIN out- put resumes the state defi ned by the TX input. During TSD, the output on VREG is maintained. If the supply voltage drops below the UVLO threshold, all outputs are disabled. When the supply voltage rises above the UVLO threshold, the A8423 is reset into the Sleep mode. From that state, it follows the logic shown in fi gure 1. That is, if Active is true (T), the A8423 immediately goes to Standby mode. If EN is high, it goes directly to the normal mode. Linear Regulator. The A8423 provides a linear regulator output with specifi ed line and load regulation up to 30 mA at 5 V. The regulator output is current-limited, at typically 100 mA. Care must be taken, however, when operating above 30 mA, due to power dissipation. This is especially important under fault conditions, such as load dump. This output is active all modes, allowing a low-power microcon- troller to continuously monitor sensor signals. Power Dissipation. Most power will normally be dissi- pated in the linear regulator. Because the output of the regu- lator is fi xed at 5 V, but the input supply can vary between

7 V and 18 V, care must be taken when setting the maximum

current. This is particularly important if the ability of the A8423 to withstand a 40 V load dump is to be used. The fi gures in the charts on the following page show the allowable power dissipation and estimated maximum current for various ambient temperatures and supply volt- ages. The data were taken using a standard FR4 board with minimal copper (RθJA = 140ºC/W), and using a "High K" dielectric board with copper ground plane and thermal vias (RθJA= 80ºC/W).

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Datasheet A8423-DS Rev.0 A8423 LIN Bus Transceiver with Integrated Voltage Regulator Preliminary – Subject to Change Without Notice February 9, 2004 0.0 0.2 0.4 0.6 0.8 1.0 1.2 100 125 150 Allowable Package Power Dissipation, PD Ambient Temperature (ºC) Power (W) "High K" RθJA = 80ºC/W FR4 RθJA = 140ºC/W 0.0 10.0 20.0 30.0 40.0 50.0 60.0 100 125 Available Current Ambient Temperature (ºC) Current (mA) 24 V 40 V FR4 RθJA = 140ºC/W 7 V 12 V 18 V 0.0 10.0 20.0 30.0 40.0 50.0 60.0 100 125 Available Current Ambient Temperature (ºC) Current (mA) 12 V 24 V "High K" RθJA = 80ºC/W 7 V 18 V 40 V

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Datasheet A8423-DS Rev.0 A8423 LIN Bus Transceiver with Integrated Voltage Regulator Preliminary – Subject to Change Without Notice February 9, 2004 Terminal List Table Name Receive open drain logic output EN Enable; logic input with internal pull-down WAKE High-voltage input controlling modes: active (Standby and Normal) and inactive (Sleep); with pull-up to VSUP TX Transmit logic input with internal pull-up GND Ground; connected to battery negative terminal LIN LIN bus connection VSUP Positive supply, 12 V nominal; external diode fi tted between the battery and this pin VREG Output providing regulated 5 V at 30 mA A8420L and A8421L 8-Pin SOIC .196 .189 4.98 4.80 .157 .150 3.99 3.81 .244 .229 6.20 5.82 .022 REF 0.55 .050 BSC 1.27 .010 .004 0.25 0.10 .068 .053 1.73 1.35 .034 .016 0.86 0.41 .009 .007 0.23 0.18 .004 BSC 0.10 .018 0.46 0.36 .014 Dimensions in inches Metric dimensions (mm) in brackets, for reference only Gauge Plane Seating Plane

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Datasheet A8423-DS Rev.0 A8423 LIN Bus Transceiver with Integrated Voltage Regulator Preliminary – Subject to Change Without Notice February 9, 2004 The products described here are manufactured under one or Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2004 AllegroMicrosystems, Inc.