A8303SESTR-T

A8303 ALLEGRO

Document overview

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Technical content

NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. Recommended Substitutions: Generation 4 and 5 devices For existing customer transition, and for new customers or new appli- cations, contact Allegro Sales. Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Date of status change: December 5, 2018 This device is in production, however, it has been deemed Pre-End of Life. The product is approaching end of life. Within a minimum of 6 months, the device will enter its final, Last Time Buy, order phase. Pre-End-of-Life

DESCRIPTION

Intended for analog and digital satellite receivers, these single low noise block converter regulator (LNBR) are monolithic linear and switching voltage regulators, specifically designed to provide the power and the interface signals to an LNB down converter via coaxial cable. The A8303 and A8303-1 require few external components, with the boost switch and compensation circuitry integrated inside of the devices. A high switching frequency is chosen to minimize the size of the passive filtering components, further assisting in cost reduction. The high levels of component integration ensure extremely low noise and ripple figures. The A8303 and A8303-1 have been designed for high efficiency, using the Allegro ™ advanced BCD process. The integrated boost switch has been optimized to minimize both switching and static losses. To further enhance efficiency, the voltage drop across the tracking regulator has been minimized. For DiSEqC™ communications, a tone control pin is provided to gate the internally generated 22 kHz tone on-and-off. A comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, and power not good. Furthermore, design methodology and structure ensure the highest level of robustness against transients and component failures. The devices use a 2-wire bidirectional serial interface, compatible with the I2C™ standard, that operates up to 400 kHz. The A8303 and A8303-1 are supplied in a lead (Pb) free package. 8303-DS, Rev. 9 MCO-0000367 FEATURES AND BENEFITS

• Integrated boost MOSFET, current sensing, and compensation
• Stable with low-profile ceramic boost capacitors
• Configurable output settings to meet global requirements
• A8303-1 includes 11.667 V setting to meet Japanese market requirements
• Adjustable LNB output current limit from 250 to 950 mA □ Covers wide array of application requirements □ Minimizes component sizing to fit each application □ For startup, reconfiguration, and continuous output (maximum value depends on PCB thermal design)
• Boost peak current limit scales with LNB current limit setting
• 8 programmable LNB output voltage (DAC) levels
• LNB overcurrent limiter with shutdown timer
• Static LNB current limit reliably starts a wide range of loads
• Tracking boost converter minimizes power dissipation
• LNB transition times configurable by external capacitor Single LNB Supply and Control Voltage Regulator Functional Block Diagram A8303 and A8303-1 I2C Interface Linear Regulator Boost Regulator Slew Rate Limiter IC Power 352 kHz Osc 0.8 V Latched Faults UVLO, OCP, TSD Unlatched Status PNG, CPOK TSD DAC Read RST SET LNBREF BOOSTREF OC BOOSTLXGNDLX VIN GND TCAP TONECTRL SDA SCL ADD Timer 45 ms VREG Ref VSEL2 / 1 / 0 VIN CLK Tone Detector TDO IRQ Fault VCP Charge Pump On / Off 22 kHz Tone Generator LNB ISET TDI ADJ TDET ILIM VFB VIN PACKAGE: 20-contact MLP/QFN (suffix ES) 4 mm × 4 mm × 0.75 mm Continued on the next page… February 8, 2019

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A. www.allegromicro.com SELECTION GUIDE Part Number Output Voltage Settings Packing [1] Description A8303SESTR-T Refer to Table 3a 7 in. reel, 1500 pieces/reel 12 mm carrier tape ES package [2], MLP/QFN surface mount 4 mm × 4 mm × 0.75 mm nominal heightA8303SESTR-T-1 Refer to Table 3b [1] Contact Allegro for additional packing options. [2] Leadframe plating 100% matte tin. ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Conditions Rating Unit Load Supply Voltage, VIN pin VIN 30 V Output Current [3] IOUT Internally Limited A Output Voltage: BOOST pin –0.3 to 43 V Output Voltage: LNB pin Surge [4] –1.0 to 43 V Output Voltage: LX pin –0.3 to 30 V Output Voltage: VCP pin –0.3 to 48 V Logic Input Voltage –0.3 to 5.5 V Logic Output Voltage –0.3 to 5.5 V Operating Ambient Temperature TA Range S –20 to 85 °C Junction Temperature TJ(max) 150 °C Storage Temperature Tstg –55 to 150 °C [3] Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150°C. [4] See application schematics 3 and 4 on pages 24 and 25.

• Push-pull LNB output stage maintains 13→18 V and 18→13 V transition times, even with highly capacitive loads
• Built-in 22 kHz tone oscillator facilitates DiSEqC™ tone encoding, even at no-load
• Tone generation does not require additional external components
• Diagnostic features: PNG, TDET
• Dynamic tone detect amplitude and frequency transmit/ receive thresholds
• Extensive protection features: UVLO, OCP, TSD, CPOK
• 2-wire I2C-compatible interface FEATURES AND BENEFITS ( continued) THERMAL CHARACTERISTICS Characteristic Symbol Test Conditions [5] Value Unit Package Thermal Resistance RθJA 4-layer PCB based on JEDEC standard 37 °C/W [5] Additional thermal information available on the Allegro website.

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Table of Contents

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com PAD BOOST NC NC GNDLX LX IRQ SCL SDA ADD TONECTRL VIN GND VREG ISET TCAP VCP LNB NC TDI TDO Pinout Diagram Terminal List Table Name Number Function ADD 9 Address select BOOST 20 Tracking supply voltage to linear regulator GND 14 Signal ground GNDLX 17 Boost switch ground IRQ 6 Interrupt request ISET 12 Output current limit set via external resistor LNB 2 Output voltage to satellite dish LX 16 Inductor drive point NC 3,18,19 No connection PAD Pad Exposed pad; connect to the ground plane, for thermal dissipation SCL 7 I2C™-compatible clock input SDA 8 I2C™-compatible data input/output TCAP 11 Capacitor for setting the rise and fall time of the LNB output TDI 4 Connect to output for 22 kHz tone verification function TDO 5 Open-drain logic output that transitions low when a 22 kHz tone is present at TDI TONECTRL 10 Gates the 22 kHz tone on-and-off VCP 1 Gate supply voltage VIN 15 Supply input voltage VREG 13 Analog supply

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ELECTRICAL CHARACTERISTICS [1]: Valid at TA = 25°C, VIN = 10 to 16 V, as noted [2], unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit GENERAL Output Voltage Accuracy VOUT VIN = 12 V, IOUT = 50 mA, see tables 3a and 3b for DAC settings –2 – 2 % Load Regulation ΔVOUT(Load) VIN = 12 V, VOUT = 13.667 V, ΔIOUT = 50 to 700 mA – 75 120 mV VIN = 12 V, VOUT = 19.000 V, ΔIOUT = 50 to 700 mA – 85 150 mV Line Regulation ΔVOUT(Line) VIN = 10 to 16 V, VOUT = 13.667 V, IOUT = 50 mA –10 0 10 mV VIN = 10 to 16 V, VOUT = 19.000 V, IOUT = 50 mA –10 0 10 mV Supply Current IIN(OFF) ENB = 0, VIN = 12 V – 4 – mA IIN(ON) ENB = 1, VIN = 12 V, VOUT = 19 V, ILOAD = 0 mA, TONECTRL = 0 – 11 – mA ENB = 1, VIN = 12 V, VOUT = 19 V, ILOAD = 0 mA, TONECTRL = 1 – 17 – mA Boost Switch On Resistance RDS(on) BOOST ISW = 450 mA – 300 – mΩ Switching Frequency fSW 320 352 384 kHz Linear Regulator Voltage Drop ∆VREG VBOOST – VLNB, no tone signal, ILOAD = 700 mA 600 800 1000 mV TCAP Pin Current ITCAP TCAP capacitor (C12) charging –13 –10 –7 µA TCAP capacitor (C12) discharging 7 10 13 µA Output Voltage Rise Time [3] tr(VLNB) For VLNB 13.667 to 19.667 V; C12 = 100 nF, ILOAD = 700 mA – 10 – ms Output Voltage Pull-Down Time [3] tf(VLNB) For VLNB 19.667 to 13.667 V; CLOAD = 100 µF, ILOAD = 0 mA – 25 – ms LNB Sink Current [3] IRLNB ENB = 0, VLNB = 21 V, Boost capacitor fully charged – 2 4 mA ENB = 1, VSEL2,1,0 = 001 (13.667 V), VLNB = 21 V, TONECTRL = 0 or 1 – 9 15 mA ENB = 1, VSEL2,1,0 = 101 (19.000 V), VLNB = 21 V, TONECTRL = 0 or 1 – 9 15 mA ENB = 1, VSEL2,1,0 = 110 (19.667 V),

18.5 V < VLNB <21 V, TONECTRL = 0 – 30 40 mA

LNB Off Current ILNB(Off) VIN = 16 V – – 10 µA Continued on the next page…

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TA = 25°C, VIN = 10 to 16 V, as noted [2], unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit GENERAL (continued) Ripple and Noise on LNB Output [4] Vrip,n(pp)

20 MHz BWL; reference circuit shown in

Application Information section; contact Allegro for additional information on application circuit board design – 15 – mVPP VREG Voltage VVREG VIN = 10 V 4.97 5.25 5.53 V ISET Voltage VISET VIN = 10 V 3.4 3.5 3.6 V TCAP Voltage VTCAP VIN = 10 V, VOUT = 13.667 V – 2.28 – V VIN = 10 V, VOUT = 19.000 V – 3.17 – V PROTECTION CIRCUITRY Output Overcurrent Limit [5] IOUT(MAX) RSET = 100 kΩ 250 300 350 mA RSET = 37.4 kΩ 720 800 880 mA Overcurrent Disable Time tDIS – 45 – ms VIN Undervoltage Lockout Threshold VUVLO VIN falling 8.05 8.35 8.65 V VIN Turn On Threshold VIN(th) VIN rising 8.40 8.70 9.00 V Undervoltage Hysteresis VUVLOHYS – 350 – mV Boost MOSFET Current Limit IBOOST(MAX) RSET = 100 kΩ – 1680 – mA RSET = 37.4 kΩ – 4030 – mA Thermal Shutdown Threshold [3] TJ – 165 – °C Thermal Shutdown Hysteresis [3] ∆TJ – 20 – °C Power Not Good (Low) PNGLOSET With respect to VLNB setting; VLNB low, PNG set to 1 88 91 94 % PNGLORESET With respect to VLNB setting; VLNB low, PNG reset to 0 92 95 98 % Power Not Good (Low) Hysteresis PNGLOHYS With respect to VLNB setting – 4 – % Power Not Good (High) PNGHISET With respect to VLNB setting; VLNB high, PNG set to 1 106 109 112 % PNGHIRESET With respect to VLNB setting; VLNB high, PNG reset to 0 102 105 108 % Power Not Good (High) Hysteresis PNGHIHYS With respect to VLNB setting – 4 – % TONE Amplitude (A8303) VTONE(PP) ILNB = 0 to 700 mA, CLNB = 750 nF 400 650 900 mVPP Amplitude (A8303-1) VTONE(PP) ILNB = 0 to 700 mA, CLNB = 330 nF 400 650 800 mVPP Frequency fTONE ILNB = 0 to 700 mA, CLNB = 750 nF or 330 nF 20 22 24 kHz Duty Cycle DCTONE 40 50 60 % Rise Time tR(TONE) 5 10 15 μs Fall Time tF(TONE) 5 10 15 μs Continued on the next page…

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com TONE DETECTION Amplitude VTDX(PP) TONECTRL = 1 400 650 900 mVPP VTDR(PP) TONECTRL = 0; 22 kHz sine wave 250 650 900 mVPP Reject Amplitude, Low VTD(XMT)L TONECTRL = 1 – – 250 mVPP VTD(RCV)L TONECTRL = 0; 22 kHz sine wave – – 100 mVPP Reject Amplitude, High VTD(XMT)H TONECTRL = 1 – – 1100 mVPP VTD(RCV)H TONECTRL = 0; 22 kHz sine wave – – 1100 mVPP Frequency Capture fTD(RCV) TONECTRL = 0; 650 mVPP sine wave 17 22 27 kHz fTD(XMT) TONECTRL = 1; 650 mVPP sine wave 20 22 24 kHz Frequency Reject, Low fTD(RCV)L TONECTRL = 0; 650 mVPP sine wave 12 14 – kHz fTD(XMT)L TONECTRL = 1; 650 mVPP sine wave 15 17 – kHz Frequency Reject, High fTD(RCV)H TONECTRL = 0; 650 mVPP sine wave – 34 37 kHz fTD(XMT)H TONECTRL = 1; 650 mVPP sine wave – 30 33 kHz Detection Delay tDET 650 mVPP , 22 kHz sine wave – 1.5 3 cycle TDI Input Impedance ZTDI – 8.6 – kΩ TDO Output Voltage VTDO(L) Tone present, ILOAD = 3 mA − − 0.4 V TDO Output Leakage ITDO Tone absent, 0 V < VTDO < 5 V − − 10 µA TONE CONTROL (TONECTRL) Logic Input VH 2.0 – – V VL – – 0.8 V Input Leakage –1 – 1 μA I2C™-COMPATIBLE INTERFACE Logic Input (SDA,SCL) Low Level VSCL(L) – – 0.8 V Logic Input (SDA,SCL) High Level VSCL(H) 2.0 – – V Logic Input Hysteresis VI2CIHYS – 150 – mV Logic Input Current II2CI VI2CI = 0 to 5 V –1 <±1.0 1 µA Logic Output Voltage SDA and IRQ VOUT(L) ILOAD = 3 mA – – 0.4 V Logic Output Leakage SDA and IRQ VLKG VOUT = 0 to 5 V – – 10 µA SCL Clock Frequency fCLK – – 400 kHz I2C™ ADDRESS SETTING ADD Voltage for Address 0001,000 Address1 0 – 0.7 V ADD Voltage for Address 0001,001 Address2 1.3 – 1.7 V ADD Voltage for Address 0001,010 Address3 2.3 – 2.7 V ADD Voltage for Address 0001,011 Address4 3.3 – 5.0 V [1] Operation at 16 V may be limited by power loss in the linear regulator. [2] Indicates specifications guaranteed from 0 ≤ TJ ≤ 125°CMIN. [3] Guaranteed by worst case process simulations and system characterization. Not production tested. [4] LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layout recommendations. Not production tested. [5] Current from the LNB output may be limited by the choice of Boost components. ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TA = 25°C, VIN = 10 to 16 V, as noted [2], unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Protection The A8303 and A8303-1 have a wide range of protection features and fault diagnostics which are detailed in the Status Register section. Boost Converter/Linear Regulator The A8303 and A8303-1 solution contains a tracking current- mode boost converter and linear regulator. The boost converter tracks the requested LNB voltage to within 800 mV , to minimize power dissipation. Under conditions where the input voltage, VBOOST , is greater than the output voltage, VLNB, the linear regu- lator must drop the differential voltage. When operating in these conditions, care must be taken to ensure that the safe operating temperature range of the A8303 and A8303-1 is not exceeded. The boost converter operates at 352 kHz typical: 16 times the internal 22 kHz tone frequency. All the loop compensation, current sensing, and slope compensation functions are provided internally. The A8303 and A8303-1 have internal pulse-by-pulse current limiting on the boost converter and DC current limiting on the LNB output to protect the IC against short circuits. When the LNB output is shorted, the LNB output current is limited, and if the overcurrent condition lasts for more than 45 ms, the LNB output will be disabled. If this occurs, the A8303 and A8303-1 output must be reenabled for normal operation. The system should provide sufficient time between successive restarts to limit internal power dissipation; 1 to 2 seconds is recommended At extremely light load or no load, if the BOOST voltage tries to exceed the BOOST target voltage, the boost converter oper- ates with minimum on time. BOOST settling voltage depends on supply voltage, boost inductance, minimum on time, switching frequency, output power and power loss in boost inductor, capaci- tor and A8303 and A8303-1. If the BOOST voltage settles below pulse skipping threshold (23.7 V), the boost converter continues to operate with minimum on time. If BOOST voltage tries to exceed 23.7 V , pulse skipping occurs, and pulse skipping stops when the BOOST voltage drops to 23.4 V . In the case that two or more set top box LNB outputs are con- nected together by the customer (e.g., with a splitter), it is pos- sible that one output could be programmed at a higher voltage than the other. This would cause a voltage on one output that is higher than its programmed voltage (e.g., 19 V on the output of a 13 V programmed voltage). The output with the highest voltage will effectively turn off the other outputs. As soon as this voltage is reduced below the value of the other outputs, the A8303 and A8303-1 output will auto-recover to their programmed levels. Charge Pump. Generates a supply voltage above the internal tracking regulator output to drive the linear regulator control. LNB and BOOST Current Limits. The LNB output current limit, IOUT(MAX) can be set by connecting a resistor (RSET) from the ISET pin to GND as shown in the applications schematic. The LNB current limit can be set from 300 to 800 mA, correspond- ing to an RSET value of 100 to 37.4 kΩ, respectively. If the LNB current limit is exceeded for more than the Overcurrent Disable Time (tDIS) then the A8303 and A8303-1 will be shut down and the OCP bit set, as shown in figure 1. The LNB output current limit can be set as high as 950 mA (RSET = 31.6 kΩ) but care should be taken not to exceed the thermal limit of the package or thermal shutdown (TSD) will occur. The typical LNB output cur- rent limit can be set according to the following equation: IOUT(MAX) = 29,925 / RSET , where IOUT(MAX) is in mA and RSET is in kΩ. If the voltage at the ISET pin is 0 V (that is, shorted to GND), IOUT(MAX) will be clamped to a moderately high value (approximately 1.5 A). Care should be taken to ensure that ISET is not inadvertently grounded. If no resistor is connected to the ISET pin (that is, if ISET is open-circuit), IOUT(MAX) will be set to approximately 0 A and the A8303 and A8303-1 will not support any load (OCP will occur prematurely). The BOOST pulse-by-pulse current limit, IBOOST(MAX), is auto- matically scaled along with the LNB output current limit. The typical BOOST current limit is set according to the following equation: IBOOST(MAX) = 4.7 × IOUT(MAX) + 270 mA , where both IBOOST(MAX) and IOUT(MAX) are in mA. Automatically scaling the BOOST current limit allows the designer to choose the lowest possible saturation current of the boost inductor, reducing its physical size and PCB area, thus minimizing cost. FUNCTIONAL DESCRIPTION

Manchester, NH 03103-3353 U.S.A. Figure 1. Startup, Reconfiguration, and Short Circuit operation using RSET = 37.4 kΩ, and from the TCAP pin to GND (C12 in the Applications Schematic). rate control for the BOOST pin occurs from this voltage. should provide satisfactory operation for most applications. tion is unaffected by the value of C12 . specifications, even with no load on the on the LNB output. and the OCP bit will be set. should allow 1 to 2 seconds of delay between restarts.

Manchester, NH 03103-3353 U.S.A. require the use of an external DiSEqC filter. A 22 kHz tone detector is provided in the A8303 and A8303-1. pin and provides it as an open-drain logic output at the TDO pin. tion delay is typically shorter than 1.5 cycles. TONECTRL is a logic high (transmit) and a logic low (receive). Figure 2. Internal tone, gated by TONECTRL pin

Manchester, NH 03103-3353 U.S.A. gin is 32° and with 33 µH the phase margin is only 10°. Figure 6. Gain and Phase Margin of the boost loop at various inductance levels Figure 4. Boost inductor peak current versus ILNB

Manchester, NH 03103-3353 U.S.A. Figure 5. Boost capacitor rms current versus ILNB current rating of the boost capacitor given the LNB load current. The nominal boost capacitance should total 18.8 to 30 µF. inductance and 20, 15, 10, 7.5, and 5 µF of boost capacitance. margin is only 6° and at 5 µF this system is unstable. LNB output noise will be too high.

Manchester, NH 03103-3353 U.S.A. Table 1. Recommended Boost Capacitor Characteristics Figure 7. Gain and Phase Margin of the boost loop at various capacitance values

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com BOOST FILTERING AND LNB NOISE The LNB output noise depends on the amount of high-frequency noise at the BOOST pin. To minimize the high-frequency noise at the BOOST pin, the ceramic capacitors should be placed as close as possible to the BOOST pin. SURGE COMPONENTS The circuit shown in schematic 1 includes external diodes for surge protection. The Applications Information section includes D2, D3, and D4 component recommendations in table 6. This configuration and these components have successfully passed surge tests up to ±1000 V/500 A, with a 1.2/50 µs − 8/20 µs combination wave. Recently, set-top box suppliers have increased their surge speci- fications to require “surge to failure of the TVS” or ±4000 V , whichever occurs first. These increased surge voltages produce significantly more current in the both the external circuitry and the A8303 and A8303-1. Allegro surge testing has shown that the SMDJ20A and LNBTVS6-221 usually fail at approximately

43 V , so all the LNBR output components (ceramic capacitors,

diodes, etc.) should support at least 50 V . To protect at these higher voltage/current levels three modifica- tions must be made:

• For increased positive surge, the shunting diode from the LNB pin to the BOOST pin (D3, 3 A/40 V) will no longer be able to protect the body diode of the output stage. This diode must be increased to a 3 A/50 V device and be located so that it is in series with the BOOST pin as shown in schematics 3 and 4. In this position D3 will block surge current to the majority of the boost capacitance, but the 1 µF ceramic capacitor will still filter the high frequency switching noise.
• For increased negative surge, the relatively small clamping diode (D2) from LNB to ground will no longer be sufficient. This diode must be increased from a 1 A/40 V , SOD123 to a 3 A/50 V , SMA device.
• For a DiSEqC 1.0 application, a 0.47 Ω/1%/0.25 W series resistor also must be added as shown in the application drawings. The 0.47 Ω resistor could be reduced if there is enough equivalent resistance in any series output components such as jumpers, inductors, or PCB traces. Every application will have its own surge requirements and the surge solution can be changed. However, Allegro strongly recommends incorporating a form of surge protection to prevent any pin of the A8303 and A8303-1 from exceeding its Absolute Maximum voltage ratings shown in this datasheet.

Manchester, NH 03103-3353 U.S.A. Figure 8. I2C™ Interface Read and Write Sequences. (A) for the I2C™ Write cycle and (B) for the I2C™ Read cycle instances where AK bits are toggled by the A8303 and A8303-1. bits of control data. This protocol is shown in figure 8(A). and A8303-1. This protocol is shown in figure 8(B).

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com I2C™ Communications I2C™ Start and Stop Conditions. The I2C™ Start condi- tion is defined by a negative edge on the SDA line while SCL is highConversely, the Stop condition is defined by a positive edge on the SDA line while SCL is high. The Start and Stop conditions are shown in figure 8. It is possible for the Start or Stop condition to occur at any time during a data transfer. If either a Start or Stop condition is encountered during a data transfer, the A8303 and A8303-1 will respond by resetting the data transfer sequence. I2C™ Write Cycle Description. Writing to the A8303 and A8303-1 Control register requires transmission of a total of 27 bits–three 8-bit bytes of data plus an Acknowledge bit after each byte. Writing to the A8303 and A8303-1 Control register is shown in figure 8(A). Writing to the A8303 and A8303-1 Control register requires a chip address with R/W = 0, a Control register address, and the control data, as follows:

• The Chip Address cycle consists of a total of nine bits— seven bits of chip address (A6 to A0) plus one read/write bit (R/W = 0) to indicate a write from the master followed by an Acknowledge bit (AK = 0 for reception of a valid chip address) from the slave. The chip address must be transmitted MSB (A6) first. The first five bits of the A8303 and A8303-1 chip address (A6 to A2) are fixed as 00010. The remaining two bits (A1 and A0) are used to select one of four possible A8303 and A8303-1 chip addresses. The DC voltage on the ADD pin programs the chip address. See the Electrical Characteristics table for the ADD pin voltages and the corresponding chip addresses.
• The Control Register Address cycle consists of a total of nine bits—eight bits of control register address (RC7 to RC0) from the master followed by an Acknowledge bit from the slave. The Control register address must be transmitted MSB (RC7) first. The A8303 and A8303-1 only have one Control register each, so the Control register address is fixed as 00000000.
• The Control Data cycle consists of a total of nine bits—eight bits of control data (D7 to D0) from the master followed by an Acknowledge bit from the slave. The control data must be transmitted MSB first (D7). The Control register bits are identified in the Control Registers section of this datasheet. I2C™ Read Cycle Description. Reading from the A8303 and A8303-1 Status register requires transmission of a total of 36 bits–four 8-bit bytes of data plus an Acknowledge bit after each byte. Reading the A8303 and A8303-1 Status register requires a chip address with R/W = 0, a Status register address, an I2C™ Stop condition, an I2C™ Start condition, a “repeated” chip address with R/W=1, and finally the status data from the A8303 and A8303-1. Reading from the A8303 and A8303-1 Status regis- ter is shown in figure 8(B).
• This 9-bit Chip Address cycle is identical to the Chip Address cycle previously described for the Write Control register sequence. It consists of A6 to A0, plus one read/write bit (R/W = 0) from the master, followed by an Acknowledge bit from the slave and finally an I2C™ Stop condition.
• The Status Register Address cycle consists of a total of nine bits–eight bits of Status register address (RS7 to RS0) from the master, followed by an Acknowledge bit from the slave. The Status register address must be transmitted MSB (RS7) first. The A8303 and A8303-1 only have one Status register, so the Status register address is fixed at 00000000.
• The “Repeated” Chip Address cycle begins with an I2C™ Start condition followed by a 9-bit cycle identical to the Chip Address cycle previously described for the Write Control Register sequence. It consists of A6 to A0, plus one read/write bit (R/W = 1) from the master, followed by an Acknowledge bit from the slave.
• The Status Data cycle consists of a total of nine bits–eight bits of status data (RD7 to RD0) from the slave, followed by an Acknowledge bit from the master. The status data is transmitted MSB (RD7) first. The Status register bits are identified in the Status Register section of this data sheet.

Manchester, NH 03103-3353 U.S.A. request attention from the master controller. Status Register section and figure 9 for further details.

• The first method uses the I2C address setting (Address 2, Address 3, or Address 4). In this method while VIN is below

8.70 V (typ), the A8303 and A8303-1 are disabled and the

• The second method uses I2C address setting (Address 1). In this method the I2C port is active when VIN is above the I2C UVLO (6 V when VIN is rising). IRQ transitions low when VIN goes above I2C UVLO (6 V , VIN rising), and the I2C Read cycle resets IRQ to logic high even if VIN is below UVLO. Even though IRQ is cleared below UVLO, one more Read cycle is required after VIN goes above UVLO, to re-enable the A8303 and A8303-1. While VIN is falling, IRQ transitions low when VIN goes below UVLO, and the I2C Read cycle resets IRQ to logic high. A detailed timing diagram is shown in figure 10(B). When the master device receives an interrupt, it should address all slaves connected to the interrupt line in sequence and read the status register of each to determine which device is requesting attention. As shown in figure 9, the A8303 and A8303-1 latch all conditions in the Status register and set the IRQ to logic low when a UVLO, OCP, or TSD event occurs. The IRQ bit is reset to logic high and the Status register is unlatched when the master acknowledges the status data from the A8303 and A8303-1 (an AK bit must be received from the master). The disable (DIS) and Power Not Good (PNG) conditions do not cause an interrupt and are not latched in the Status register. Stop 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A0 0 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK AK Status Register Address Chip Address Start W SDA IRQ FAULT event, IRQ set low, Status register latched SCL acknowledge from LNBR (slave) acknowledge from LNBR (slave) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A0 1 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK AK Status Data Chip Address Start R acknowledge from LNBR (slave) acknowledge from master Stop IRQ reset STATUS register unlatched

Figure 9. Fault, IRQ, and Status Register Timing. When a UVLO, OCP, or TSD event occurs, the IRQ bit is set low

Manchester, NH 03103-3353 U.S.A. I2C Read cycle resets IRQ to logic high. 10(A). IRQ and Fault Clearing in Response to Undervoltage at VIN (UVLO), with I2C address set to (Address 2, Address 3, or Address 4). brown-out had occurred. An I2C Read cycle is required to report and clear the UVLO fault before the A8303 and A8303-1 can be re-enabled. Figure 10. IRQ and Fault Clearing in Response to Undervoltage at VIN (UVLO), showing the alternate methods, set by selection of I2C address

Manchester, NH 03103-3353 U.S.A. Figure 11. IRQ and Fault Clearing in Response to Overcurrent (OCP). If the LNB output is grounded for more than 45 ms, the LNB output is no longer grounded. Figure 12. IRQ and Fault Clearing in Response to Thermal Shutdown (TSD). If the LNB junction temperature rises above 165°C enabled, provided the junction temperature is below 145°C (typ).

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com I2C™-Compatible Interface Timing Diagram tSU:STA tHD:STA tSU:DAT tHD:DAT tBUF tSU:STO tHIGH tLOW SDA SCL I2C™-Compatible Timing Requirements Characteristics Symbol Min. Typ. Max. Unit Bus Free Time Between Stop/Start tBUF 1.3 – – µs Hold Time Start Condition tHD:STA 0.6 – – µs Setup Time for Start Condition tSU:STA 0.6 – – µs SCL Low Time tLOW 1.3 – – µs SCL High Time tHIGH 0.6 – – µs Data Setup Time tSU:DAT 100 – – ns Data Hold Time* tHD:DAT 0 – 900 ns Setup Time for Stop Condition tSU:STO 0.6 – – µs Output Fall Time (VfI2COut(H) to VfI2COut(L)) tfI2COut – – 250 ns *For tHD:DAT(min) , the master device must provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the SCL signal falling edge.

Manchester, NH 03103-3353 U.S.A. Table 2. Control Register Definition

0 VSEL0 LNB output voltage control

standards plus the ability to add line compensation.

1 VSEL1

2 VSEL2

3 ENB

Turns the LNB output on or off.

Manchester, NH 03103-3353 U.S.A. A8303 and A8303-1, assuming the fault has been resolved. be cleared by performing an I2C™ READ cycle. The Disable bit (DIS) indicates the status of the LNB output. turned back on using the Enable (ENB) bit via the I2C™ interface. CPOK, and TDET bits are continuously updated. Table 4. Status Register Description and IRQ Operation

0 DIS LNB output disabled Yes LNB enabled and no faults None

1 CPOK Charge pump OK No VCP > VBOOST + 5V None

2 OCP Overcurrent Yes I2C™ READ and ILOAD < ISET IRQ set low

3 TRIMS Trim bits locked Yes None None

4 PNG Power Not Good No LNB voltage within range None

5 TDET Tone detect No Tone removed from LNB pin None

6 TSD Thermal shutdown Yes I2C™ READ and TJ < 145°C IRQ set low

Table 5. Status Register Bit Descriptions 0 DIS The DIS bit is set to 1 when the A8303 and A8303-1 are disabled, (ENB = 0) or there is a fault: UVLO, OCP, CPOK, or TSD. output is disabled and the DIS bit is set. disable time (tDIS). If the OCP bit is set to 1, then the DIS bit is also set to 1. range (nominally ±5% from the LNB DAC setting). threshold is determined by VTD(RCV)L. the DIS bit is also set to 1. 1, then the DIS bit is also set to 1.

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com

APPLICATION INFORMATION

Schematic 1. DiSEqC 2.0 Applications, 12 VIN ±10%, 700 mA IOUT , surge of ±1000 V, 2 Ω, 1.2/50 μs – 8/20 μs combination wave 15uH 100nF 1A/40V 220nF GND C12 100nF GND 3.3V 3A/40V 100nF GND RSET 37.4K GND SDA SCL IRQ TONECTRL VIN 3.3V TDO SDA8 ADD9 SCL7 GND14 TONECTRL10 VIN15 IRQ6 TDI 4 NC 18 LNB 2 BOOST VCP 1 TCAP11 NC 19 GNDLX VREG13 LX TDO5 PAD 0 ISET 12 NC 3 TONE XMIT GND 10nF 100nF C10 220nF 100 C11 10nF 1A/40V LNBout 220uH 10K 2.0 10K > 40V 100mA 10K 10K GNDGND 3000W 32V/500A < 0.5ohm > 40V or 3X10uF C5 to C7 4X4.7uFor 1X10uF 2X4.7uF A8303 A8303-1 See next page for bill of materials

Manchester, NH 03103-3353 U.S.A. Table 6. Component Selection Table

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15uH 100nF 3A/40V 220nF GND C12 100nF GND 3.3V 3A/40V 100nF GND RSET 37.4K GND SDA SCL IRQ TONECTRL VIN 3.3V TDO SDA8 ADD9 SCL7 GND14 TONECTRL10 VIN15 IRQ6 TDI 4 NC 18 LNB 2 BOOST VCP 1 TCAP11 NC 19 GNDLX VREG13 LX TDO5 PAD 0 ISET 12 NC 3 GND 10nF 100nF C10 220nF 100 C11 10nF 1A/40V LNBout 3000W 32V/500A or 3X10uF C5 to C7 4X4.7uFor 1X10uF 2X4.7uF A8303 A8303-1 Schematic 2. DiSEqC 1.0 Applications, 12 VIN ±10%, 700 mA IOUT , surge of ±1000 V, 2 Ω, 1.2/50 μs – 8/20 μs combination wave

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15uH 100nF 3A/50V 220nF GND 10nF C12 100nF GND 100nFR2 3.3V 3A/50V C10 220nF 100nF GND GND 100 C11 10nF RSET 37.4K GND SDA SCL IRQ TONECTRL VIN 3A/50VR1 3.3V TDO LNBout SDA8 ADD9 SCL7 GND14 TONECTRL10 VIN15 IRQ6 TDI 4 NC 18 LNB 2 BOOST VCP 1 TCAP11 NC 19 GNDLX VREG13 LX TDO5 PAD 0 ISET 12 NC 3 U1 L2 220uH 10K < 0.5ohm 50V 2.0 10K 50V 100mA 10K 10K GNDGND TONE XMIT C13 1uF 3000W 32V/500A or 3X10uF C5 to C7 4X4.7uFor 1X10uF 2X4.7uF A8303 A8303-1 Schematic 3. DiSEqC 2.0 Applications for increased surge requirements ±1000 V, 2 Ω, 1.2/50 µs – 8/20 µs combination wave, and “stress to TVS failure” (or ±4000 V) test

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Schematic 4. DiSEqC 1.0 Applications for increased surge requirements ±1000 V, 2 Ω, 1.2/50 µs – 8/20 µs combination wave, and “stress to TVS failure” (or ±4000 V) test 10uH 100nF 3A/50V 220nF GND GND C12 100nF 3.3V 3A/50V 100nF GND Rset 37.4K GND SDA SCL IRQ TONECNTL VIN 3.3V TDO C13 1uF GND 10nF 100nF C10 220nF 100 C11 10nF 3A/50V LNBout 3000W 32V/500A R10 0.47, 1/4W SDA8 ADD9 SCL7 GND14 TONECTRL10 VIN15 IRQ6 TDI NC LNB 2 BOOST VCP 1 TCAP11 NC 19 GND LX VREG13 LX TDO5 PAD 0 ISET 12 NC or 2X10uF C5 to C7 3X4.7uF 1X10uF A8303 A8303-1 or 2X4.7uF

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Package ES 20-Pin MLP/QFN 0.95 CSEATING PLANEC0.08 21X A Terminal #1 mark area Coplanarity includes exposed thermal pad and terminals B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) For Reference Only (reference JEDEC MO-220WGGD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C D D C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 4.10 0.30 0.50 4.10 0.50 0.75 ±0.05 0.40 ±0.10 2.45 2.45 0.25 +0.05 –0.07 4.00 ±0.10 4.00 ±0.10 2.45 2.45 B PCB Layout Reference View PACKAGE OUTLINE DRAWING

Single LNB Supply and Control Voltage Regulator A8303 and A8303-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com I2C™ is a trademark of Philips Semiconductors. DiSEqC™ is a trademark of Eutelsat S.A. Copyright ©2011-2019, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents.

Revision History

5 January 11, 2016 Corrected Terminal List Table (page 3)

6 July 22, 2016 Updated Component Selection Table (page 22)

7 January 11, 2018 Minor editorial updates

8 January 22, 2019 Minor editorial updates

9 February 8, 2019 Product status changed to Pre-End-of-Life

For the latest version of this document, visit our website: www.allegromicro.com