A8302

A8302 ALLEGRO

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Technical content

Description

The A8302 is a dual channel low noise block converter regulator (LNBR). The A8302 consists of a monolithic linear and switching voltage regulator, specifically designed to provide the power and the interface signals to an LNB down converter via coaxial cable in satellite TV receivers systems. The A8302 requires few external components, with the boost switch and compensation circuitry integrated inside of the device. The boost converter switching frequency and user-controlled current limit minimize the size of the passive filtering components. User controlled current limit and two switching frequency settings allow to optimize size of passive filtering components. A sleep pin is available to maximize power savings and to quickly shut down the device if needed, without using I 2C™ control. The A8302 has integrated tone detection capability and the internal driver allows full two-way DiSEqC™ communications. For DiSEqC™ communication, the IC provides an internal 22-kHz tone that is gated with the TONECTRLx pin or accepts an external 22-kHz tone through the TONECTRLx pin. 8302-DS Features and Benefits ▪ Integrated boost MOSFET, current sensing, and compensation ▪ Configurable boost capacitor option through I2C™ control register: ceramic or electrolytic ▪ Two switching frequency settings programmable through I2C™ control register (563 kHz and 939 kHz) ▪ Adjustable LNB output current limit from 250 to 950 mA ▫ Covers a wide array of application requirements ▫ Minimizes component sizing to fit each application ▫ For startup, reconfiguration, and continuous output ▫ Optional temporary increased current limit (+25%) ▫ Internal gate drive output BFGATEx for bypass FET used in DiSEqC™ applications Dual LNB Supply and Control Voltage Regulators Functional Block Diagram A8302 Package: 32-contact MLP/QFN with exposed thermal pad (suffix ET) 5 mm × 5 mm × 0.90 mm Continued on the next page… Continued on the next page… IC Interface Linear Regulator Boost Regulator Slew Rate Limiter IC Power kHz Osc 0.8 V Latched Faults: UVLO RS MODE LNBx 10 kΩ 10 kΩ 100 kΩ Unlatched Status PNG, CPOK EPF & TDET TSD DAC Read RST SET LNBREF BOOSTREF OC BOOSTxLXxGNDLXx VIN GND TCAPx TONECTRLx SDA SCL ADD Latched or Auto- restart Faults: OCP and TSD OC Timer 45/28 ms VREG Ref VSEL3-0 VIN CLK Tone Detector TDOx BFGATEx IRQ Fault VCPx Charge Pump Tone Generator LNBx ISETx TDIx EPF EPF_TH TDIS_T TMODE ADJ TDET ILIM VFB VINSLEEP (One of two channels shown, x in pin name indicates channel: 1 or 2)

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. Selection Guide Part Number Packing1 Description A8302SETTR-T2 7 in. reel, 1500 pieces/reel 12 mm carrier tape ET package, QFN surface mount 5 mm × 5 mm × 0.90 mm nominal height 1Contact Allegro for additional packing options. 2Leadframe plating 100% matte tin. Absolute Maximum Ratings Characteristic Symbol Conditions Rating Unit Load Supply Voltage, VIN Pin VIN 25 V Output Current1 IOUT Internally Limited A Output Voltage; BOOSTx and BFGATEx Pins –0.3 to 43 V LNBx Pin2 Surge –1.0 to 43 V LXx Pin –0.3 to 30 V VCPx Pin –0.3 to 48 V Logic Input Voltage –0.3 to 5.5 V Logic Output Voltage –0.3 to 5.5 V EPF and VREG Pins –0.3 to 6 V Operating Ambient Temperature TA Range S; TA(max) depends on thermal design; overriding factor is TJ(max) –20 to 85 °C Junction Temperature TJ(max) 150 °C Storage Temperature Tstg –55 to 150 °C 1Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150°C. 2See application schematics 3 and 4 on pages 38 and 40. ▪ Boost peak current limit scales with LNB current limit setting ▪ Early Power Failure (EPF) warning ▪ SINK_DIS bit to control maximum output reverse current ▪ 8 programmable LNB output voltage (DAC) levels ▪ LNB overcurrent limit protection and TSD with auto- restart or latched ▪ LNB transition times configurable by external capacitor ▪ Built-in 22-kHz tone oscillator facilitates DiSEqC™ tone encoding ▫ Tone generation does not require additional external components ▪ Diagnostic features: PNGx,TDETx, BOOSTxH and EPF ▪ Dynamic tone detect amplitude and frequency transmit/receive thresholds ▪ Extensive protection features: UVLO, TSD, OCPx, and CPOKx ▪ Sleep mode with shutdown current < 15 µA (typ) Features and Benefits (continued) Description (continued) The A8302 offers Early Power Failure (EPF) warning, which helps to initiate shutdown routines. The A8302 maximum output reverse current can be set using the SINK_DIS bit. A comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, and power not good. The device uses a 2-wire bidirectional serial interface, compatible with the I 2C™ standard, that operates up to 400 kHz. The A8302 is supplied in a 5 mm × 5 mm, 32-contact, lead (Pb) free QFN package (suffix ET), with 100% matte tin plated leadframe.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Thermal Characteristics may require derating at maximum conditions Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance RθJA 4-layer PCB based on JEDEC standard 30 ºC/W *Additional thermal information available on the Allegro website Table of Contents Specifications 2 Absolute Maximum Ratings 2 Thermal Characteristics 3 Pin-Out and Terminal List 4 Electrical Characteristics 5 Functional Description 9 Boost Converter/Linear Regulator 9 Boost Converter Operation Under Light Load 9 Multiple Outputs 10 Charge Pump 10 LNBx and BOOSTx Current Limits Setting 10 Protection 10 Undervoltage Lockout (UVLO) 10 Overload and Short Circuit Handling 10 Switching Frequency Selection 13 Compensation Network Selection 13 Pull-Down Rate 13 Thermal Shutdown (TSD) 15 SINK_DIS Mode Selection 15 Sleep Mode 15 In-Rush Current 15 Tone Generation 15 Tone Detection 15 Early Power Failure Warning (EPF) 16 Component Selection 17 Boost Ceramic Capacitor Option 17 Boost Electrolytic Capacitor Option 18 BOOSTx Filtering and LNBx Noise 18 Surge Components 18 I2C™-Compatible Interface 19 SDA and SCL Signals 19 Acknowledge (AK) Bit 19 Acknowledge Bit During a Write Sequence 19 Acknowledge Bit During a Read Sequence 19 I2C™ Communications 19 I2C™ Start and Stop Conditions 19 I2C™ Write Sequence Description 20 I2C™ Read Sequence Description 20 Interrupt Request (¯I¯ ¯¯R¯ ¯Q¯ ) Pin 20 UVLO Timing Diagrams 22 I2C Timing 26 Control Registers (I2C™-Compatible Write Register) 29 Status Registers (I2C™-Compatible Read Register) 31 Application Information 34 Application Schematics 34 Package Outline Diagram 42

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Pin-out Diagram Terminal List Table Number Name Function

1 VCP1 Channel 1 gate supply voltage

2 LNB1 Channel 1 output voltage to LNB

3 BFGATE1 Channel 1 gate driver point for the external P-channel bypass MOSFET

4 TDI1 Channel 1 Tone Detect input

5 TDI2 Channel 2 Tone Detect input

6 BFGATE2 Channel 2 gate driver point for the external P-channel bypass MOSFET

7 LNB2 Channel 2 output voltage to LNB

8 VCP2 Channel 2 gate supply voltage

9 BOOST2 Tracking supply voltage to channel 2 linear regulator

10 GNDLX2 Channel 2 boost switch ground

11 LX2 Channel 2 internal boost switch drain node

12 NC No connect

13 SCL I2C-compatible clock input

14 SDA I2C-compatible data input/output

15 ADD Address select

16 ¯I¯ ¯¯R¯ ¯Q¯ Interrupt request output

17 TONECONTRL1 Apply a 22-kHz tone or tone on-and-off signal to enable/disable internal tone of channel1

18 TONECONTRL2 Apply a 22-kHz tone or tone on-and-off signal to enable/disable internal tone of channel2

19 ISET1 Terminal for external resistor that sets the LNB1 current limit

20 ISET2 Terminal for external resistor that sets the LNB2 current limit

21 TCAP1 Capacitor for setting the rise and fall time of the LNB1 output

22 TCAP2 Capacitor for setting the rise and fall time of the LNB2 output

23 ¯S¯ ¯L¯ ¯E¯ ¯E¯ ¯P¯ Disables LNB output, boost, I2C communication, and charge pump, to reduce input quiescent current to <15 µA

24 VREG Analog supply

25 TDO2 Open-drain logic output that transitions high when a 22-kHz tone is present at the TDI2 pin

26 TDO1 Open-drain logic output that transitions high when a 22-kHz tone is present at the TDI1 pin

27 EPF Early Power Failure warning comparator output

28 GND Signal ground

29 VIN Input supply voltage

30 LX1 Channel 1 internal boost switch drain node

31 GNDLX1 Channel 1 boost switch ground

32 BOOST1 Tracking supply voltage to channel 1 linear regulator

– PAD Exposed pad for thermal dissipation; connect to the ground plane PAD BOOST1 GNDLX1 LX1 VIN GND EPF TDO1 TDO2 BOOST2 GNDLX2 LX2 NC SCL SDA ADD IRQ VREG SLEEP TCAP2 TCAP1 ISET2 ISET1 TONECTRL2 TONECTRL1 VCP1 LNB1 BFGATE1 TDI1 TDI2 BFGATE2 LNB2 VCP2

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Continued on the next page… ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VIN = 10 to 16 V, as noted2; unless noted otherwise Characteristic Symbol Test Conditions Min. Typ. Max. Unit General Output Voltage Accuracy VOUTx VIN = 12 V, IOUTx = 10 mA, see table 3a for DAC settings –2 – 2 % Load Regulation ΔVOUTx(Load) VIN = 12 V, VOUTx = 13.667 V, ΔIOUTx = 10 to 700 mA – 75 120 mV VIN = 12 V, VOUTx = 19.000 V, ΔIOUTx = 10 to 700 mA – 85 150 mV Line Regulation ΔVOUTx(Line) VIN = 10 to 16 V, VOUTx = 13.667 V, IOUTx = 10 mA –10 0 10 mV VIN = 10 to 16 V, VOUTx = 19.000 V, IOUTx = 10 mA –10 0 10 mV Supply Current IIN(OFF) ENB1 and ENB2 bits = 0, VIN = 12 V – 7 – mA IIN(ON) ENB1 and ENB2 bits = 1, VIN = 12 V, VOUTx = 19 V, ILOAD = 10 mA, TONECTRLx = 0 – 65 – mA ENB1 and ENB2 bits = 1, VIN = 12 V, VOUTx = 19 V, ILOAD = 10 mA, TONECTRLx = 1 – 85 – mA ¯S¯ ¯L¯ ¯E¯ ¯E¯ ¯P¯ = 0 V, VIN = 12 V, TONECTRLx = 0 – – 15 µA Boost Switch On Resistance RDS(on)BOOST ILOAD = 450 mA – 300 – mΩ Switching Frequency fSW FSW bit = 0 507 563 619 kHz FSW bit = 1 845 939 1032 kHz Minimum COntrollable On-Time tON(min) – 85 – ns Linear Regulator Voltage Drop ∆VREGx VBOOSTx – VLNBx, no tone signal, ILOAD = 700 mA 600 800 1000 mV TCAPx Pin Current ICHGx TCAP capacitor (CTCAP in application drawings) charging –13 –10 –7 µA IDISCHGx TCAP capacitor (CTCAP in application drawings) discharging 7 10 13 µA Output Voltage Rise Time 3 tr(VLNB) For VLNBx 13 → 19 V; CTCAP (see application drawings) = 100 nF, ILOADx = 700 mA – 10 – ms Output Voltage Pull-Down Time3 tf(VLNB) For VLNBx 19 → 13 V; CLOAD = 100 µF, ILOADx = 0 mA, SINK_DIS bit = 0 – 20 – ms

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS1 (continued) at TA = 25°C, VIN = 10 to 16 V, as noted2; unless noted otherwise Characteristic Symbol Test Conditions Min. Typ. Max. Unit Continued on the next page… Output Reverse Current IRLNBx ENBx bit = 0 – 2 4 mA SINK_DIS bit = 1, ENBx bit = 1, TONECTRLx = 0 – 7 10 mA SINK_DIS bit = 0, ENBx bit = 1, TONECTRLx = 0, LNBx - VSELx| < 1.5 V – 25 40 mA SINK_DIS bit = 0, ENBx bit = 1, TONECTRLx = 1, |VLNBx - VSELx| <1.5 V – 60 85 mA SINK_DIS bit = 0, ENBx bit = 1, TONECTRLx = 0 or 1, |VLNBx - VSELx| > 1.5 V – 7 10 mA LNBx Off Current ILNBx(OFF) VIN = 16 V – – 10 µA General (continued) Ripple and Noise on LNBx Output4 Vripn(pp)

20 MHz BWL; reference circuit shown in

Functional Block diagram; contact Allegro for additional information on application circuit board design – 30 – mV PP VREG Voltage VVREG VIN = 10 V 4.97 5.25 5.53 V ISETx Voltage VISETx VIN = 10 V 3.4 3.5 3.6 V TCAPx Voltage VTCAPx VIN = 10 V, VOUTx = 13.667 V – 2.28 – V VIN = 10 V, VOUTx = 19.000 V – 3.17 – V Protection Circuitry Output Overcurrent Limit5 IOUTx(MAX) RSETx = 100 kΩ 220 300 380 mA RSETx = 37.4 kΩ 720 800 880 mA Overcurrent Disable Time tDIS TDIS_T bit = 1 – 45 – ms TDIS_T bit = 0 – 28 – ms Overcurrent Re-Enable Time tREN RSMODE bit = 1 – 1 – s Boost MOSFET Current Limit IBOOSTx(MAX) RSETx = 100 kΩ 1300 1800 2300 mA RSETx = 37.4 kΩ 2800 3300 3800 mA VIN Undervoltage Lockout Threshold VUVLO VIN falling 8.05 8.35 8.65 V VIN Turn-On Threshold VIN(th) VIN rising 8.40 8.70 9.00 V I2C™ Undervoltage Lockout Threshold VUVLO_ I2C VIN falling – 5.5 – V I2C™ Turn-On Threshold VIN(th)_I2C VIN rising – 5.7 – V Undervoltage Hysteresis VUVLOHYS – 350 – mV Thermal Shutdown Threshold3 TJ – 165 – °C

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS1 (continued) at TA = 25°C, VIN = 10 to 16 V, as noted2; unless noted otherwise Characteristic Symbol Test Conditions Min. Typ. Max. Unit Continued on the next page… Thermal Shutdown Hysteresis3 ∆TJ – 20 – °C Power Not Good (Low) PNGxLOSET With respect to VLNBx setting; VLNBx low, PNGx bit set to 1 88 91 94 % PNGxLORESET With respect to VLNBx setting; VLNBx low, PNGx bit reset to 0 92 95 98 % Power Not Good (Low) Hysteresis PNGxLOHYS With respect to VLNBx setting – 4 – % Power Not Good (High) PNGxHISET With respect to VLNBx setting; VLNBx high, PNGx bit set to 1 106 109 112 % PNGxHIRESET With respect to VLNBx setting; VLNBx high, PNGx bit reset to 0 102 105 108 % Power Not Good (High) Hysteresis PNGxHIHYS With respect to VLNBx setting – 4 – % Tone Amplitude VTONE(PP)x ILNBx = 0 to 700 mA, CLNBx = 750 nF 500 700 900 mVPP Frequency fTONEx 20 22 24 kHz Duty Cycle DTONEx 40 50 60 % Rise Time tr(TONE)x 5 10 15 μs Fall Time tf(TONE)x 5 10 15 μs Tone Detection Amplitude VTDX(PP)x Tone transmit 500 700 900 mVPP VTDR(PP)x Tone receive, 22 kHz sine wave 250 650 900 mVPP Reject Amplitude, Low VTD(XMT)Lx Tone transmit – – 250 mVPP VTD(RCV)Lx Tone receive, 22 kHz sine wave – – 100 mVPP Reject Amplitude, High VTD(XMT)Hx Tone transmit – – 1.1 VPP VTD(RCV)Hx Tone receive, 22 kHz sine wave – – 1.1 VPP Frequency Capture fTD(RCV)x Tone receive, 650 mVPP sine wave 17 22 27 kHz fTD(XMT)x Tone transmit, 650 mVPP sine wave 20 22 24 kHz Frequency Reject, Low fTD(RCV)Lx Tone receive, 650 mVPP sine wave 12 14 – kHz fTD(XMT)Lx Tone transmit, 650 mVPP sine wave 15 17 – kHz Frequency Reject, High fTD(RCV)Hx Tone receive, 650 mVPP sine wave – 34 37 kHz fTD(XMT)Hx Tone transmit, 650 mVPP sine wave – 30 33 kHz Detection Delay tDETx Tone receive, 650 mVPP , 22 kHz sine wave – 1.5 3 cycle TDI Input Impedance ZTDIx – 8.6 – kΩ TDO Output Voltage VTDO(L)x Tone present, ILOAD = 3 mA − − 0.4 V

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS1 (continued) at TA = 25°C, VIN = 10 to 16 V, as noted2; unless noted otherwise Characteristic Symbol Test Conditions Min. Typ. Max. Unit TDO Output Leakage ITDOx Tone absent, 0 V < VTDO < 5 V − − 10 µA EPF Pin Threshold VEPF_TH VIN voltage falling − 3.325 − V EPF Threshold Hysteresis VEPF_TH_hys − 175 − mV BFGATE/LNB Voltage VBFG_ON TONECTRLx = high − 50 − % VBFG_OFF TONECTRLx = low − 99 − % Tone Control (TONECTRL pin) Logic Input VTNCTL(H)x 2.0 – – V VTNCTL(L)x – – 0.8 V Input Leakage Current ITNCTL(lkg)x −1 – 1 μA Logic Input VSLP(H) 2.0 – – V VSLP(L) – – 0.8 V Input Leakage Current ISLP(lkg) – 50 – μA I2C™- Compatible Interface Logic Input (SDA and SCL pins) VSCL(L) – – 0.8 V VSCL(H) 2.0 – – V Logic Input Hysteresis VI2CIHYS – 150 – mV Logic Input Current II2CI VI2CI = 0 to 5 V –10 <±1.0 10 µA Logic Output Voltage (SDA and ¯I¯ ¯¯R¯ ¯Q¯ pins) VI2COUT(L) ILOAD = 3 mA – – 0.4 V Logic Output Leakage Current (SDA and ¯I¯ ¯¯R¯ ¯Q¯ pins) II2CLKG VI2COUT(L) = 0 to 5 V – – 10 µA SCL Clock Frequency fCLK – – 400 kHz I2C™ Address Setting ADD Pin Voltage for Address 0001 000 Address1 0 – 0.7 V ADD Pin Voltage for Address 0001 001 Address2 1.3 – 1.7 V ADD Pin Voltage for Address 0001 010 Address3 2.3 – 2.7 V ADD Pin Voltage for Address 0001 011 Address4 3.0 – 5.0 V 1Operation at 16 V may be limited by power loss in the linear regulator. 2Indicates specifications guaranteed from 0 ≤ TJ ≤ 125°C (min), design goal is 0 ≤ TJ ≤ 150°C. 3Guaranteed by worst case process simulations and system characterization. Not production tested. 4LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the application schematic drawings and the PCB layout recommendations. Not production tested. 5Current from the LNB output may be limited by the choice of BOOST components.

Worcester, Massachusetts 01615-0036 U.S.A. range of the A8302 is not exceeded. protect the IC against output short to GND faults. the A8302 enters into pulse skipping with 350 mV hysteresis. when BOOSTx stops switching. to 0, the internal sink on BOOSTx is disabled. Figure 1. Startup, reconfiguration, and short circuit operation using RSETx = 37.4 kΩ, and a capacitive load (OCPx_25P bit = 0)

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Multiple Outputs In the case that two or more set top box LNB outputs are con- nected together by the customer (such as with a splitter), it is possible that one output could be programmed at a higher voltage than the other. This would cause a voltage on one output that is higher than its programmed voltage (for example, 19 V on the output of a 13 V programmed voltage). The output with the highest voltage will effectively turn off the other outputs. As soon as this voltage is reduced below the value of the other outputs, the A8302 output will auto-recover to its programmed levels. Charge Pump Generates a supply voltage above the internal tracking regulator output to drive the linear regulator control. LNBx and BOOSTx Current Limits Setting The LNB output current limit, I OUTx(MAX) can be set by connect- ing a resistor (RSETx) from the ISETx pin to GND as shown in the applications schematics. The LNBx current limit can be set from 300 to 1000 mA, corresponding to an R SETx value of 100 to 30 kΩ, respectively. See figure 1 for a typical circuit tim- ing example. The LNBx output current limit can be set as high as 1000 mA (by selecting an RSETx of 30 kΩ), but care should be taken not to exceed the thermal limit of the package, or thermal shutdown (TSD) will occur. The typical LNB output current limit can be set according to the following equation: I OUTx(MAX) = 29,925 / RSETx , where IOUTx(MAX) is in mA and RSETx is in kΩ. If the voltage at the ISETx pin is 0 V (that is, shorted to GND), IOUTx(MAX) will be clamped to a moderately high value, 1.2 A. Care should be taken to ensure that ISETx is not inadvertently grounded. If no resistor is connected to the ISETx pin (that is, if ISETx is open-circuit), I OUT(MAX) will be set to approximately

0 A and the A8302 will not support any load (OCP will occur

prematurely). The BOOSTx pulse-by-pulse current limit, IBOOSTx(MAX), is automatically scaled along with the LNBx output current limit. The typical BOOSTx current limit is set according to the follow- ing equation: IBOOSTx(MAX) = 3.0 × IOUTx(MAX) + 900 (mA) , where both IBOOSTx(MAX) and IOUTx(MAX) are in mA. Automatically scaling the BOOSTx current limit allows the designer to choose the lowest possible saturation current of the boost inductor, reducing its physical size and PCB area, thus minimizing cost. Protection The A8302 has a wide range of protection features and fault diag- nostics which are detailed in the Status Register section. Undervoltage Lockout (UVLO) The Undervoltage Lockout (UVLO) comparator monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage is below the lockout threshold, V IN(th) . The UVLO com- parator incorporates enough hysteresis, VUVLOHYS , to prevent on-off cycling of the regulator due to IR drops in the VIN path during heavy loading or during startup. Overload and Short Circuit Handling The A8302 protects the IC against output overload and short cir- cuit. The short circuit disable timer is controlled with the TDIS_T bit. If this bit is set to 1, the IC allows an overcurrent condition to persist up to 45 ms and if this bit is set to 0, the maximum overcurrent time allowed is 28 ms. The A8302 provides the option either to latch or to auto-restart on fault. If the RSMODE bit is set to 1, with an overcurrent condition that exceeds typically 45 ms (TDIS_T set to 1) or 28 ms (TDIS_T set to 0), the IC turns off output for 1 s and then auto-restarts with the previous settings. This hiccup mode continues as long as output current is greater than the OCP level. The device returns to normal operation when the fault is removed. If RSMODE is set to 0, the IC turns off after t DIS time expires, and remains latched. Figures 2a and 2b explain overcurrent protection operation with RSMODE at 1 and at 0. The A8302 has an optional 25% bump up on the current limit for tdis /4 period. This feature is enabled / disabled by setting or reset- ting Control Register 2 bits 0 and 1 for channel 1 and channel 2 respectively. When this bit is enabled, the output current limit is 25% more than the set current limit, or 1000 mA (max), for both limits a minimum of t dis /4 period. After the tdis / 4 period, the out- put current limit comes down to the set limit and the OCPx_25P bit is reset to zero, The user must set this bit again to enable the 25% bump up at the next current limit event. If the OCPx_25P bit is zero when LNBx output is shorted to ground, the LNBx output current will be clamped to I OUTx(MAX). If the short circuit condi- tion lasts for more than 45 ms, the A8302 will be disabled and the OCPx bit will be set. Refer to figures 16a and 16b.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Figure 2a. ¯I¯ ¯¯R¯ ¯Q¯ and Fault Clearing in Response to Overcurrent (OCP) with auto-retry enabled (RSMODE = 1) and an OCP delay of 45 (or 28) ms (TDIS_T = 1 (or 0)). ¯I¯ ¯¯R¯ ¯Q¯ transitions to low at an OCP fault and is reset by an I2C Read sequence. The OCP bit clears automatically after 1 s, and the device restarts with the previous settings. This hiccup mode continues as long as the output current is greater than the OCP level. The device returns to normal operation when the fault is removed. ENBx bit 1.4 ms Short circuit causes IOUTx to exceed IOCP for longer than 45 (or 28) ms IC shutdown, then restart V OUTx and tone settings restored as before short circuit occurred I OUTx(MAX) 1 s IOUTx VLNBx VBOOSTx OCPx bit I2C Read PNGx bit IRQ 1.4 ms 1 s VIN Short circuit removed

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Figure 2b. ¯I¯ ¯¯R¯ ¯Q¯ and Fault Clearing in Response to Overcurrent (OCP) with latch mode (RSMODE = 0) and an OCP delay of 45 (or 28) ms (TDIS_T = 1(or 0)). ¯I¯ ¯¯R¯ ¯Q¯ transitions low at an overcurrent fault, and an I2C Read sequence clears the OCP bit and ¯I¯ ¯¯R¯ ¯Q¯ . An I2C Write sequence is required to reenable the part. The retry wait time should be longer than 1 s, to prevent TSD. ENBx bit 1.4 ms Short circuit causes IOUT to exceed IOCP for longer than 45 (or 28) ms IC shutdown, then restart Short circuit removed I OUTx VLNBx VBOOSTx OCPx bit I2C Read PNGx bit IRQ VIN VOUTx and tone settings restored as set in most recent Write cycle User-controlled tOFF > 1 s IOUTx(MAX)

Worcester, Massachusetts 01615-0036 U.S.A. which the hardware is designed. network setting based on the boost capacitor selection. current disable delay bits must not be changed during operation. the BOOSTx pin occurs from this voltage. See figure 3. ably cause the voltage transition specification to be exceeded. Tone generation is unaffected by the value of CTCAPx . Figure 3. TCAPx timing at startup, transition, and OCP faults. In latch mode (RSMODE = 0).

13 V setting 13 V setting

18 V setting Overcurrent applied

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Figure 4a. ¯I¯ ¯¯R¯ ¯Q¯ and Fault Clearing in Response to Overtemperature (TSD) with auto-retry (RSMODE = 1). If for any reason the junction temperature exceeds 165°C (typ), the device LNBx output and the boost converter are disabled. The IC attempts to restart at 1-second intervals, but the LNBx output restarts only when TJ cools below 145°C. The ¯I¯ ¯¯R¯ ¯Q¯ pin resets on an I2C Read sequence, and the TSD bit resets along with an LNBx output restart. ENBx bit IC attempts to restart at 1-second intervals; restart is successfull if T J < 145°C VOUTx and tone settings restored as before TSD circuit operated VLNBx IC TJ VBOOSTx TSD bit I2C Read PNGx bit IRQ VIN TJ > 165°C TJ < 145°C Figure 4b. ¯I¯ ¯¯R¯ ¯Q¯ and Fault Clearing in Response to Overtemperature (TSD) with latch mode (RSMODE = 0). ¯I¯ ¯¯R¯ ¯Q¯ transitions low after TSD fault, and an I2C Read sequence immediately resets the ¯I¯ ¯¯R¯ ¯Q¯ pin. The TSD bit is cleared by an I2C Read sequence only after the device has cooled to a TJ below 145°C. An I2C Write sequence is required to reenable the device. Fault removed IC shutdown and latched IC TJ VLNBx TSD bit I2C Read PNGx bit IRQ VOUTx and tone settings restored as set in most recent Write cycle TJ > 165°C TJ < 145°C

Worcester, Massachusetts 01615-0036 U.S.A. stage provides approximately 25 mA of pull-down capability. cations, even with no load on the on the LNBx output. device returns to normal operation when the fault is removed. If RSMODE is set to 0, the IC turns off, and remains latched. IN(OFF) less than 15 µA from the input supply. tions and does not require an external DiSEqC™ filter. after TONECTRLx has been low for longer than 42 µs. delay is typically shorter than 1.5 cycles. Figure 5. Options for tone generation

Worcester, Massachusetts 01615-0036 U.S.A. TONECTRLx is a logic high (transmit) and a logic low (receive). LNBR) and begin its shutdown routines. pin voltage goes above VEPF_TH + VEPF_TH_hys . EPF0 and EPF1 bits. See table 3b for description. EPF_TH1 ( VIN corresponding to setting EPF bit) = 10.5 V. EPF_TH1 ( VIN corresponding to setting EPF bit) = 7 V. Figure 7. Example circuit for Early Power Failure feature

Worcester, Massachusetts 01615-0036 U.S.A. EPF_TH2 (VIN corresponding to resetting EPF bit) = 7.35 V. used for cable disconnect detection . ler can decode these bits t for the cable disconnect detection. the EPF bit to 0; other wise the EPF bit is set to 1. reset, the cable is disconnected, otherwise the cable is connected. Figure 8. Cable Disconnect Detection

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Component Selection Boost Inductor The A8302 is designed to operate with a boost inductor value of either 10 μH ±30% ( Set Fsw bit =0 ) or 4.7 μH ±30% ( Set Fsw bit =1 ) with a DCR less than 75 mΩ. The error amplifier loop compensation, current sense gain, and PWM slope compensa- tion were chosen for this value of inductor. The boost inductor must be able to support the peak currents required to maintain the maximum LNBx output current without saturating. Figure 9a can be used to determine the peak current in the induc tor tor given the LNBx load current. The curve labeled Typical uses VIN = 12 V, VBOOST = 20 V, L = 10 μH, and f = 563 kHz, while the curve labeled Maximum assumes VIN = 10.8 V, VBOOST = 21 V, L = 7 μH, and f = 507 kHz. Figure 9b can be used to determine the peak current in the induc- tor tor given the LNBx load current. The curve labeled Typical uses VIN = 12 V, VBOOST = 20 V, L = 4.7 μH, and f = 939 kHz, while the curve labeled Maximum assumes VIN = 10.8 V, VBOOST = 21 V, L = 3.3 μH, and f = 845 kHz Boost Ceramic Capacitor Option The A8302 can be configured to operate with two or three, high- quality ceramic capacitors on the boost node. Allegro recom- mends capacitors that are rated at least 35 V, ±10%, X7R, 1210 Figure 9a. Boost inductor peak current versus ILNB for the A8302 (L= 10uH, Fsw bit =0) 4000 3500 3000 2500 2000 1500 1000 500 300 400 500 600 700 800 900 1000 I vs IBOOST LNB Current Limit Setting, I (mA)LNB Maximum Typical I (mA BOOST PEAK Figure 9b. Boost inductor peak current versus ILNB for the A8302 (L= 4.7uH, Fsw bit =1) 4000 3500 3000 2500 2000 1500 1000 500 300 400 500 600 700 800 900 1000 I vs IBOOST LNB Current Limit Setting, I (mA)LNB Maximum Typical I (mA BOOST PEAK

Worcester, Massachusetts 01615-0036 U.S.A. characteristics shown in table 1. LNB output noise will be too high. boost capacitor given the LNBx load current. Figure 10. Boost capacitor rms current versus ILNB close as possible to the BOOSTx pin.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. occurs first. These increased surge voltages produce significantly more current in both the external circuitry and the A8302. Allegro surge testing has shown that the SMDJ20A and LNBTVS6-221 usually fail at approximately 43 V , so all of the LNBR output components (ceramic capacitors, diodes, and so forth) should support at least 50 V . To protect at these higher voltage/current levels three modifica- tions must be made:

• For increased positive surge, the shunting diode from the LNBx pin to the BOOSTx pin (D3, 3 A/40 V) is no longer adequate to protect the body diode of the output stage. This diode must be increased to a 3 A/50 V device and be located so that it is in series with the BOOSTx pin as shown in application schematics 3 and 4. In this position D3 will block surge current to the majority of the boost capacitance, but the 1 µF ceramic capacitor will still filter the high frequency switching noise.
• For increased negative surge, the relatively small clamping diode (D2) from the LNBx pin to ground is no longer adequate. This diode must be increased from a 1 A / 40 V, SOD123 device to a 3 A / 50 V, SMA.
• For a DiSEqC 1.0 application, a 0.47 Ω / 1% / 0.25 W series resistor must be added as shown in the application schematics. The 0.47 Ω rating could be reduced if there is enough equiva- lent resistance in any series output components such as jumpers, inductors, or PCB traces. Every application will have its own surge requirements and the surge solution can be changed. How- ever, Allegro strongly recommends incorporating a form of surge protection to prevent any pin of the A8302 from exceeding its Absolute Maximum voltage ratings shown in this datasheet.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Figure 11b. I2C™ Interface Read from Status register sequence I2C™-Compatible Interface The I2C™ interface is used to access the internal Control and Status registers of the A8302. This is a serial interface that uses two lines, serial clock (SCL) and serial data (SDA), connected to a positive supply voltage via a current source or a pull-up resis- tor. Data is exchanged between a microcontroller (master) and the A8302 (slave). The master always generates the SCL signal. Either the master or the slave can generate the SDA signal. The SDA and SCL lines from the A8302 are open-drain signals, so multiple devices may be connected to the I 2C™ bus. When the bus is free, both the SDA and the SCL lines are high. SDA and SCL Signals SDA can only be changed while SCL is low. SDA must be stable while SCL is high. However, an exception is made when an I 2C™ Start or Stop condition is encountered. See the I2C™ Com- munications section for further details. Acknowledge (AK) Bit The Acknowledge (AK) bit indicates a valid transmission and can be used in two ways. First, if the slave successfully receives eight bits of either an address or control data, it pulls the SDA line low (AK set to 0) for the ninth SCL pulse to signal a valid transmission to the master. Second, if the master successfully receives eight bits of status data from the A8302, it pulls the SDA line low for the ninth SCL pulse to signal a valid transmission to the slave. The recipient (either the master or the slave) should set the AK bit high (AK set to 1, also referred to as NAK) for the ninth SCL pulse if eight bits of data were not received successfully. Acknowledge Bit During a Write Sequence When the master sends control data (writes) to the A8302 there are three cases where AK bits are sent by the A8302. First, the A8302 uses the AK bit to indicate reception of a valid seven- bit chip address plus a Read/Write bit (with R/W set to 0 for a Write). Second, the A8302 uses the AK bit to indicate reception of a valid eight-bit Control register address. Third, the A8302 uses the AK bit to indicate reception of eight bits of control data. This protocol is shown in figure 11a. Acknowledge Bit During a Read Sequence When the master reads status data from the A8302 there are four cases where AK bits are sent: three are sent by the A8302 and one is sent by the master. First, the A8302 uses the AK bit to indicate reception of a valid seven-bit chip address plus a Read/ Write bit (with R/W set to 0 for a Write). Second, the A8302 uses the AK bit to indicate reception of a valid eight-bit Status register address. Third, the A8302 uses the AK bit to indicate reception of a valid seven-bit chip address plus a Read/Write bit (with R/W set to 1 for a Read). Finally, the master uses the AK bit to indicate receiving eight bits of status data from the A8302. This protocol is shown in figure 11b. I 2C™ Communications I2C™ Start and Stop Conditions The I2C™ Start condition is defined by a negative edge on the SDA line while SCL is high. Conversely, the Stop condi- tion is defined by a positive edge on the SDA line while SCL is high. The Start and Stop conditions are shown in figures 10a and 10b. It is possible for a Start or Stop condition to occur at Figure 11a. I2C™ Interface Write to Control registers sequence 0 0 0 1 0 0 0/1 0/1 0/10/1 0/1 R/W R/W R/W 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/10 0 0 0 0 0/10 0 0 0 0 1 0 0 0/1 0/10/1 0/1 0 0 0 1 10 0/10/1 0/1 0/10/1 0/1 0/1 0/1 0/1 0/1 0/1 0/10 0 0 0 0 00 0 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A0 W RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0AK/ NAK AK/ NAK Control Register Address Chip Address Start SDA SCL AK/ NAK Stop Stop acknowledge from A8302 (slave) acknowledge from A8302 (slave) acknowledge from A8302 (slave) 1 2 3 4 5 6 7 8 9 Control Data D6 D5 D4 D3 D2 D1 D0 D7 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A0 W RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK/ NAK Status Register Address Chip Address Start SDA SCL acknowledge from A8302 (slave) acknowledge from A8302 (slave) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A0 R RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK/ NAK AK/ NAK Status Data Chip Address Start acknowledge from A8302 (slave) acknowledge from master Stop AK/ NAK

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. any time during a data transfer. If either a Start or Stop condition is encountered during a data transfer, the A8302 will respond by resetting the data transfer sequence. I 2C™ Write Sequence Description Writing to the A8302 Control register requires transmission of a total of 27 bits: three 8-bit bytes of data plus an AK bit after each byte. The Write sequence to the A8302 Control registers is shown in figure 10a. Writing to the A8302 Control registers requires: an I 2C™ Start condition, a chip address with the R/W bit set to 0, the Control register address, the control data, and an I2C™ Stop condition as follows:

• The Chip Address cycle consists of a total of nine bits: seven bits of chip address (A6 to A0) plus one R/W bit (set to 0 to indicate a Write) from the master, followed by an AK bit (set to 0 to indicate reception of a valid chip address) from the slave. The cycle begins with a Start condition. The chip address must be transmitted MSB (A6) first. The first five bits of the A8302 chip address (A6 to A2) are fixed as 00010. The remaining two bits (A1 and A0) are used to select one of four possible A8302 chip addresses. The DC voltage on the ADD pin programs the chip address. See the Electrical Characteristics table for the ADD pin voltages and the corresponding chip addresses.
• The Control Register Address cycle consists of a total of nine bits: eight bits of Control register address (RC7 to RC0) from the master followed by an AK bit (set to 0 to indicate reception of a valid register address) from the slave. The Control register address must be transmitted MSB (RC7) first. The A8302 has two Control registers, with register addresses of 0000 0000 and 0000 0001.
• The Control Data cycle consists of a total of nine bits: eight bits of control data (D7 to D0) from the master, followed by an AK bit (set to 0 to indicate reception of eight valid bits) from the slave. The control data must be transmitted MSB (D7) first. The Control registers bits are identified in the Control Registers sec- tion of this datasheet. The cycle concludes with a Stop condition. I 2C™ Read Sequence Description Reading from the A8302 Status register requires transmission of a total of 36 bits: four 8-bit bytes of data, plus an AK bit after each byte. The Read sequence from the A8302 Status register is shown in figure 10b. Reading the A8302 Status register requires: an I2C™ Start condition, a chip address with the R/W bit set to 0, the Status register address, an I2C™ Stop condition, an I2C™ Start condition, a repeat of the chip address with the R/W bit set to 1, the status data, and an I2C™ Stop condition, as follows:
• The Chip Address cycle is identical to the Chip Address cycle previously described for the Write sequence.
• The Status Register Address cycle consists of a total of nine bits: eight bits of Status register address (RS7 to RS0) from the master, followed by an AK bit from the slave. The Status register address must be transmitted MSB (RS7) first. The A8302 has only one Status register, so the Status register address is fixed at 0000 0000. The cycle concludes with a Stop condition.
• The Repeat Chip Address cycle is identical to the Chip Address cycle previously described for the Write sequence.
• The Status Data cycle consists of a total of nine bits: eight bits of status data (RD7 to RD0) from the slave, followed by an AK bit from the master. The status data is transmitted MSB (RD7) first. The Status register bits are identified in the Status Registers section of this datasheet. The cycle concludes with a Stop condition. Interrupt Request ( The A8302 provides an interrupt request pin, ¯I¯ , which is an open-drain, active low output. This output may be connected to a common IRQ line with a suitable external pull-up resistor and can be used with other I 2C™ compatible devices to request atten- tion from the master controller. The ¯I¯ output becomes active (logic low) when the A8302 recognizes a fault condition. The fault conditions that will force ¯I¯ active include Early Power Failure (EPF), undervoltage lockout (UVLO), overcurrent protection (OCP), and thermal

Worcester, Massachusetts 01615-0036 U.S.A. Register section and figure 12 for further details. Good (PNGx bit set to 1) conditions do not cause an interrupt. and are not latched in the Status register. REF , VIN , and EPF conditions. Figure 12. I2C™ Interface Read from Status register sequence. The ¯I¯ ¯¯R¯ ¯Q¯ pin is reset to high when the A8302

Worcester, Massachusetts 01615-0036 U.S.A. Figure 13. Startup and Shutdown Cases. ¯I¯ ¯¯R¯ ¯Q¯ and Fault Clearing in Response to Undervoltage at VIN (UVLO). If ¯I¯ ¯¯R¯ ¯Q¯ transitions low fault and reset the ¯I¯ ¯¯R¯ ¯Q¯ to logic high. An I2C™ Read is required after a UVLO fault.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Figure 14b. ¯I¯ ¯¯R¯ ¯Q¯ is cleared when VIN is already above VIN(th) . As the ENBx bit is already set high, LNBx starts rising immediately after an I2C Read sequence. 8.70 V 5.7 V IRQ LNBx pin Output 5.5 V VIN I2C Read Cycle Enable (ENBx bit via I 2C) I2C Inactive I2C Inactive (with Hys) 8.35 V SLEEP (External) READ between VREG and VUVLO is optional, to clear IRQ early. This is also helpful when the EPF threshold is set between VREG and VUVLO READ when VIN > VIN(Th) is required to clear the UVLO bit B B A A 8.70 V 5.7 V IRQ LNBx pin Output 5.5 V VIN I2C Read Cycle Enable (ENBx bit via I2C) I2C Inactive I2C Inactive (with Hys) 8.35 V SLEEP (External) Figure 14a. I2C and ¯I¯ ¯¯R¯ ¯Q¯ operate down to VIN > VREG (VREG is 5.25 V typical), LNBx and BOOSTx operate from VIN(th) . When VIN exceeds VREG (5.25 V typical), ¯I¯ ¯¯R¯ ¯Q¯ transitions low because of the UVLO fault, and an I2C Read sequence will clear the ¯I¯ ¯¯R¯ ¯Q¯ fault. While powering down, when VIN falls below VUVLO , ¯I¯ ¯¯R¯ ¯Q¯ becomes low, LNBx and BOOSTx turn off, and I2C becomes inactive when VIN falls below VREG .

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Figure 15b. EPF pin threshold greater than VUVLO . When VIN falls below EPF_TH2. ¯I¯ ¯¯R¯ ¯Q¯ transitions low and the EPF bit is set high. The I2C Read sequence releases ¯I¯ ¯¯R¯ ¯Q¯ . When VIN falls below VUVLO , ¯I¯ ¯¯R¯ ¯Q¯ transitions low, LNBx voltage goes down, and once again the I2C Read sequence clears ¯I¯ ¯¯R¯ ¯Q¯ . VIN IRQ EPF bit I2C Read ENBx bit LNBx pin Output 6 V (I2C UVLO) 8.3 V (VIN UVLO) 10.5 V (EPF _TH2) I2C Inactive VIN IRQ EPF bit I2C Read ENBx bit LNBx pin Output I2C 5.7 V (I2C UVLO) 8.7 V (VIN UVLO) 11 V (EPF _TH1) 12 V Inactive 23 ms delay setting Figure 15a. EPF pin threshold greater than VUVLO . When VIN is rising. ¯I¯ ¯¯R¯ ¯Q¯ transitions low immediately after VIN goes above VREG (typical), and ¯I¯ ¯¯R¯ ¯Q¯ is cleared immediately by an I2C Read sequence. After VIN goes above VIN(th) and is followed by an I2C Read sequence, the UVLO bit is cleared and the LNB voltage goes up. After VIN goes above EPF_TH1, the EPF bit is cleared, after the delay specified by the EPF0 and EPF1 bits.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Figure 16b. EPF pin threshold greater than VREG and less than VUVLO . When VIN falls below VUVLO , ¯I¯ ¯¯R¯ ¯Q¯ transitions low and an I2C Read sequence releases ¯I¯ ¯¯R¯ ¯Q¯ . When VIN falls below EPF_TH , ¯I¯ ¯¯R¯ ¯Q¯ will not go low. VIN IRQ EPF bit I2C Read ENBx bit LNBx pin Output 5.2 V 8.3 V (VIN UVLO) 7 V (EPF _TH2) I2C Inactive I VIN IRQ EPF bit I2C Read ENBx bit LNBx pin output I2C 5.5 V 8.7 V (VIN Th) 7.35 V (EPF _TH1) 12 V Inactive EPF delay setting Figure 16a. EPF pin threshold greater than VREG and less than VUVLO . When VIN is rising, ¯I¯ ¯¯R¯ ¯Q¯ transitions low immediately after VIN goes above VREG , and ¯I¯ ¯¯R¯ ¯Q¯ is cleared immediately by an I2C Read sequence. After VIN goes above EPF_TH1, the EPF bit is cleared after the delay specified by the EPF0 and EPF1 bits. When VIN goes above VIN(th) and is followed by an I2C Read sequence, the UVLO bit is cleared and LNBx voltage goes up.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. I2C™-Compatible Interface Timing Diagram tSU:STA tHD:STA tSU:DAT tHD:DAT tBUF tSU:STO tHIGH tLOW SDA SCL I2C™-Compatible Timing Requirements Characteristic Symbol Min. Typ. Max. Unit Bus Free Time Between Stop/Start tBUF 1.3 – – µs Hold Time Start Condition tHD:STA 0.6 – – µs Setup Time for Start Condition tSU:STA 0.6 – – µs SCL Low Time tLOW 1.3 – – µs SCL High Time tHIGH 0.6 – – µs Data Setup Time tSU:DAT 100 – – ns Data Hold Time* tHD:DAT 0 – 900 ns Setup Time for Stop Condition tSU:STO 0.6 – – µs Output Fall Time (VfI2COut(H) to VfI2COut(L)) tfI2COut – – 250 ns *For tHD:DAT(min) , the master device must provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the SCL signal falling edge. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. t/ 4dis tdis tdis tdis IOUTx OCPx_25P Bit IC Read IC Write OCPx_25P bit cleared LNBx O/P LNBx O/P Shorted to GND LNBx O/P Shorted to GND LNBx O/P Shorted to GND LNBx O/P Shorted to GND removed LNBx O/P Shorted to GND removed 1.25 × I (or) < 1AOUTx(MAX) IOUTx(MAX) t/ 4dis Figure 17a. Initial 25% current limit bump up with OCPx_25P bit enabled, disabled, and changed during current limit condition with OCP period > tdis .

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. t/ 4dis <tdis <tdis <tdis IOUTx OCPx_25P Bit IC Read IC Write LNBx O/P LNB O/P Shorted to GND LNB O/P Shorted to GND LNB O/P Shorted to GND LNB O/P Shorted to GND removed LNB O/P Shorted to GND removed LNB O/P Shorted to GND LNB O/P Shorted to GND removed 1.25 × I (or) < 1AOUTx(MAX) IOUTx(MAX) LNB O/P Shorted to GND removed t/ 4dis<t /4dis Figure 17b. Initial 25% current limit bump up with OCPx_25P bit enabled, disabled, and changed during current limit condition with OCP period < tdis .

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Control Registers (I2C™-Compatible Write Register) All main functions of the A8302 are controlled through the I2C™ compatible interface via the 8-bit Control registers. Tables 2a, 2b, and 2c show the functionality and bit definitions of the Con- trol registers. At power-up, the Control registers are initialized to all 0s. Table 2a. Control Register 0 Definition Control (Write) Register Address [RC7:RC0] = 0000 0000 Bit Name Function Description

0 TMODE Controls tone mode 0: Internal tone, gated with TONECTRLx pin

1: External 22 kHz logic pulse, on TONECTRLx pin

1 TDIS_T Controls overcurrent disable delay* 0: Set overcurrent disable timeout to 28 ms

1: Set overcurrent disable timeout to 45 ms

2 EPF0 When VIN is rising, these two bits determine the EPF

bit setting delay. (See table 3b for EPF bit delay setting options.)3 EPF1

4 FSW Switching frequency setting* 0: 563 kHz

1: 939 kHz

5 COMP Switching between compensation networks* 0: Ceramic

1: Electrolytic

6 RSMODE Fault restart mode

0: Latch mode. IC latches after tDIS period on OCP or TSD; user enable required to restart 1: Auto restart mode if OCP or TSD cleared

7 SINK_NL Turn on/off internal adjustable sink on BOOSTx 0: Disable sink on BOOSTx

1: Enable sink on BOOSTx *Ensure the selected bit setting matches the hardware design. Table 2b. Control Register 1 Definition Control (Write) Register Address [RC7:RC0] = 0000 0001 Bit Name Function Description

0 VSEL01

LNB1 output voltage control (see table 3a for available output voltage selections) The available voltages provide levels for all the common standards plus the ability to add line compensation; VSEL01 is the LSB and VSEL31 is the MSB to the internal DAC

1 VSEL11

2 VSEL21

3 VSEL31

4 ENB1 Turns the LNB1 output on or off 0: Disable LNB1 output

1: Enable LNB1 output

5 OCP1_25P 25% bump up over current limit for channel 1, for t

period; bit resets automatically after tdis/4 period 0 : Bump up off 1 : Bump up on

6 SINK_DIS 1 SINK_DIS mode setting for channel 1 0: Maximum Output Reverse Current, I

RLNBx , is 70 mA 1: Maximum Output Reverse Current, IRLNBx , is 10 mA

7 Tone Delay 1

In the External Tone Generation option (TMODE = 1), LNB1 voltage can be reset back to the target value with a 42 µs delay, or can be set to ≈350 mV below the target value without a delay, by using this bit. 0: (Default) LNB1 voltage will be reset back to the target after a delay of 42 µs from the last TONECONTRL1 falling edge. 1: Tone will turn off with out a delay and the LNB1 voltage will stay at ≈350 mV below the target.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Table 2c. Control Register 2 Definition Control (Write) Register Address [RC7:RC0] = 0000 0010 Bit Name Function Description

0 VSEL02

LNB2 output voltage control (see table 3a for available output voltage selections) The available voltages provide levels for all the common standards plus the ability to add line compensation; VSEL02 is the LSB and VSEL32 is the MSB to the internal DAC

1 VSEL12

2 VSEL22

3 VSEL32

4 ENB2 Turns the LNB2 output on or off 0: Disable LNB2 output

1: Enable LNB2 output

5 OCP2_25P 25% bump up over current limit for channel 2, for tdis/4

period; bit resets automatically after tdis/4 period 0 : Bump up off 1 : Bump up on

6 SINK_DIS 2 SINK_DIS mode setting for channel 2 0: Maximum Output Reverse Current, I

RLNBx , is 70 mA 1: Maximum Output Reverse Current, IRLNBx , is 10 mA

7 Tone Delay 2

In the External Tone Generation option (TMODE = 1), LNB2 voltage can be reset back to the target value with a 42 µs delay, or can be set to ≈350 mV below the target value without a delay, by using this bit. 0: (Default) LNB2 voltage will be reset back to the target after a delay of 42 µs from the last TONECONTRL2 falling edge. 1: Tone will turn off with out a delay and the LNB2 voltage will stay at ≈350 mV below the target.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Table 3a. Output Voltage Amplitude Selection VSEL3 VSEL2 VSEL1 VSEL0 LNB (V) 0 0 1 0 13.333 0 0 1 1 13.667 0 1 0 1 14.333 0 1 1 1 15.667 1 0 1 1 18.667 1 1 0 0 19.000 1 1 0 1 19.333 1 1 1 0 19.667 Table 3b. EPF Delay Selection EPF1 EPF0 Delay (ms) 0 0 0 0 1 11.5 1 0 46 1 1 92 Status Registers (I2C™-Compatible Read Register) The Status registers bits are described in tables 5a and 5b. The main fault conditions: Early Power Failure (EPF), undervoltage (UVLO), overcurrent (OCP), and thermal shutdown (TSD) are all indicated by setting the relevant bits in the Status register. For these fault cases (for OCP and TSD, only if the RSMODE bit is set to 0), after the bit is set, it remains latched until the I 2C™ master has successfully read the A8302, assuming the fault has been resolved. The undervoltage lockout (UVLO) bit indicates either V IN is below VUVLO , or VREG is out of regulation. UVLO disables the LNBx output and forces ¯I¯ low. UVLO is a latched fault, and can only be cleared by performing an I 2C™ Read sequence. The Disable bit (DISx) indicates the status of the LNBx output. The DISx bit is set when either a fault occurs (UVLO, OCP, TSD, or CPOK) or when the LNBx output is turned off using the Enable bit (ENBx) via the I 2C™ interface. The DISx bit is latched and is only reset when there are no faults and the A8302 output is turned back on using the Enable (ENBx) bit via the I 2C™ interface. The Power Not Good (PNGx), Charge Pump OK (CPOKx), and Tone Detect (TDETx) bits are set based on the conditions sensed at the LNBx output, VCPx, and Tone Detect Input (TDIx) pins, respectively. These bits are not latched and, unlike the other fault bits, may become reset without an I 2C™ read sequence. The PNGx, CPOKx, and TDETx bits are continuously updated. The BOOSTxH bit is set when the BOOSTx voltage exceeds 23.7 V . This bit can be used to detect cable disconnect, provided at the lowest supply voltage BOOSTx voltage should exceed 23.7 V . There are three methods to detect when the Status register changes: responding to the interrupt request ( ¯I¯ ) pin going low, continuously polling the Status register via the I 2C™ interface, or detecting a fault condition external to the A8302 and performing a diagnostic poll of the A8302. In any case, the master should read and re-read the Status register until the status changes.

Worcester, Massachusetts 01615-0036 U.S.A. Table 4. Status Registers Bit Descriptions charge pump voltage is too low, the LNBx output is disabled and the DISx bit is set to 1. the LNBx voltage is within the acceptable range (nominally ±5% from the LNBx DAC setting). received from an external source, and the tone detect low threshold is determined by VTD(RCV)L. set to 1,then the DISx bit is also set to 1. low. If the UVLO bit is set to 1, then the DISx bit is also set to 1. the delay selected by the EPF0 and EPF1 bits in the Control registers.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Table 5b. Status Register 1 Definition and IRQ Operation Status (Read) Register Address [RS7:RS0] = 0000 0001 Bit Name Function Latched? Reset Condition Effect on ¯I¯ ¯¯R¯ ¯Q¯ Pin

0 CPOK1 LNB1 charge pump OK No VCP1 > VBOOST1 + 5 V None

1 CPOK2 LNB2 charge pump OK No VCP2 > VBOOST2 + 5 V None

2 TDET1 LNB1 tone detect No Tone removed from LNB1 pin None

3 TDET2 LNB2 tone detect No Tone removed from LNB2 pin None

4 EPF Early Power Failure warning

(VIN < EPF threshold) No VIN > EPF_TH1 ¯I¯ ¯¯R¯ ¯Q¯ set low; I2C Read sequence resets to high

5 TRIMS Trim bits locked Yes None None

6 BOOST1H Boost1 Voltage Monitor No VBOOST1 < 23.6 V None 7 BOOST2H Boost2 Voltage Monitor No VBOOST2 < 23.6 V None Table 5a. Status Register 0 Definition and IRQ Operation Status (Read) Register Address [RS7:RS0] = 0000 0000 Bit Name Function Latched? Reset Condition Effect on ¯I¯ ¯¯R¯ ¯Q¯ Pin

0 DIS1 LNB1 output disabled Yes LNB1 enabled and no faults None

1 DIS2 LNB2 output disabled Yes LNB2 enabled and no faults None

2 OCP1 LNB1 overcurrent

Auto-retry (RSMODE = 1) OCP reset after every 1 s; IC enabled if fault is removed ¯I¯ ¯¯R¯ ¯Q¯ set low; I2C Read sequence resets to high Latch (RSMODE = 0) I2C Read sequence required after removing the fault

3 OCP2 LNB2 overcurrent

Auto-retry (RSMODE = 1) OCP reset after every 1 s; IC enabled if fault is removed ¯I¯ ¯¯R¯ ¯Q¯ set low; I2C Read sequence resets to high Latch (RSMODE = 0) I2C Read sequence required after removing the fault

4 PNG1 LNB1 Power Not Good No LNB1 voltage within range None

5 PNG2 LNB2 Power Not Good No LNB2 voltage within range None

6 UVLO VIN or VREG undervoltage Yes I2C Read sequence and

VIN > 9.0 V sequence resets to high

7 TSD Thermal shutdown

Auto-retry (RSMODE = 1) TSD reset after every 1 s; reset happens only if fault is ¯Q¯ set low; I2C Read sequence resets to high Latch (RSMODE = 0) I2C Read sequence required after removing the fault

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A.

Application Information

Schematic 1. A8302 application circuit using electrolytic capacitors on BOOST and 563 kHz switching frequency. IOUT(max) = 800 mA. See table 6 for bill of materials pads pads 10uH C3 100nF C12 220nF CTC A P1 100nF GND GND B340A 100nF 100 10nF RSET1 37.4K SDA SCL IRQ GND PGND and GND form a single point ground at U 1 VIN CTCAP2 100nF GND R9 100 C11 10nF LNB1 LNB2 D3a B350A LNB out2 LNB out1 C18 1uF 1206 50V TCTRL 2 TCTRL 1 LNB out1 GND 10uH C16 100nF B340A VIN D3b B350A C10 1uF 1206 50V GND GND RSET2 37.4K GND RT1 10k RT2 10k SDA14 ADD15 SCL13 GND28 TCTRL 117 VIN29 IRQ16 TDI1 4 BO OST2 LNB1 2 BOOST1 VCP1 TCAP 1 21 LX2 GND LX1 VREG24 LX PAD0 ISET119 LNB2 7 TCTRL 218 GND LX2 TDI2 5 VCP2 TCAP 2 22 NC 12 SLEEP23 ISET220 TDO126 TDO225 EPF BFGATE1 3 BFGATE2 6 A 8302 R11a 205k R12a 102k GND EPF EPF C10a 100nF Jumper Vin Jumper Vreg B350A C7 100nF DR1040-221-R 220uH LNB1 0805 220nF 10nF LNBTVS6-221S 2 3 4 COAX-F GND LNB1 GND R18 R25 2.0 >40V <0.5ohms LNB B350A C19 100nF DR1040-221-R L3220uH LNB1 0805 C20 220nF C21 10nF LNBTVS6-221S 2 3 4 COAX-F GND LNB1 GND 2.0 >40V <0.5ohms LNB LNB out2 BFGATE1 BFGATE1 SW2 SLEEP\\ GND 10k 1206:25V C22 1.0uC1 100u C2 100u 1uH C17 100u 1uH A8302

Worcester, Massachusetts 01615-0036 U.S.A. Table 6. Component Selection Table for Schematic 1

3 Panasonic EEE-FP1V101AP PCE4442CT-ND

D2,D3,D3a,D3b Schottky diode, 50 V, 3 A SMA 6 Diodes, Inc.

2 Cooper Bussman DR1040-100-R 513-1399-1-ND

2 Cooper Bussman DR1040-221-R 513-1408-1-ND

1 Allegro

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Schematic 2. A8302 application circuit using ceramic capacitors on BOOST and 563 kHz switching frequency. IOUT(max) = 800 mA. See table 7 for bill of materials pads pads 10uH C3 100nF C12 220nF CTCA P1 100nF GND GND B340A 100nF 100 10nF RSET1 37.4K SDA SCL IRQ GND PGND and GND form a single point ground at U 1 VIN CTCAP2 100nF GND R9 100 C11 10nF LNB1 LNB2 D3a B350A LNB out2 LNB out1 C18 1uF 1206 50V TCTRL 2 TCTRL 1 LNB out1 GND 10uH C16 100nF B340A VIN D3b B350A C10 1uF 1206 50V GND GND RSET2 37.4K GND RT1 10k RT2 10k SDA14 ADD15 SCL13 GND28 TCTRL 117 A8302 N29 IRQ16 TDI1 4 BO OST2 LNB1 2 BOOST1 VCP1 TCAP1 21 LX2 GND LX1 VREG24 LX PAD0 ISET119 LNB2 7 TCTRL 218 GND LX2 TDI2 5 VCP2 TCAP2 22 NC 12 SLEEP23 ISET220 TDO126 TDO225 EPF BFGATE1 3 BFGATE2 6 A 8302 R11a 205k R12a 102k GND EPF EPF C10a 100nF Jumper Vin Jumper Vreg B350A C7100nF DR1040-221-R 220uH LNB1 0805 220nF C9 10nF LNBTVS6-221S 2 3 4 COAX-F GND LNB1 GND R18 R252.0 >40V <0.5ohms LNB B350A C19 100nF DR1040-221-R 220uH LNB1 0805 C20 220nF C21 10nF LNBTVS6-221S 2 3 4 COAX-F GND LNB1 GND 2.0 >40V <0.5ohms LNB LNB out2 BFGATE1 BFGATE1 2*4.7uF 2*10uF or 3*4.7uF C17 2*10uF or 3*4.7uF SW2 SLEEP\\ GND 10k

Worcester, Massachusetts 01615-0036 U.S.A. Table 7. Component Selection Table for Schematic 2 D2,D3,D3a,D3b Schottky diode, 50 V, 3 A SMA 6 Diodes, Inc.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Schematic 3. A8302 application circuit using electrolytic capacitors on BOOST and 939 kHz switching frequency. Iout(max) = 500 mA. See table 8 for bill of materials pads pads 4.7uH C3 100nF C12 220nF CTCAP1 100nF GND GND B140 100nF 100 10nF RSET1 60K SDA SCL IRQ GND PGND and GND form a single point ground at U 1 VIN CTCAP2 100nF GND R9 100 C11 10nF LNB1 LNB2 D3a B350A LNB out2 LNB out1 C18 1uF 1206 50V TCTRL 2 TCTRL 1 LNB out1 GND 4.7uH C16 100nF B140 VIN D3b B350A C10 1uF 1206 50V GND GND RSET2 60K GND RT1 10k RT2 10k A8302 SDA14 ADD15 SCL13 GND28 TCTRL 117 VIN29 IRQ16 TDI1 4 BO OST2 LNB1 2 BOOST1 VCP1 TCAP 1 21 LX2 GND LX1 VREG24 LX PAD0 ISET119 LNB2 7 TCTRL 218 GND LX2 TDI2 5 VCP2 TCAP2 22 NC 12 SLEEP23 ISET220 TDO126 TDO225 EPF BFGATE1 3 BFGATE2 6 A 8302 R11a 205k R12a 102k GND EPF EPF C10a 100nF Jumper Vin Jumper Vreg B350A 100nF DR1040-221-R 220uH LNB1 0805 220nF C9 10nF LNBTVS6-221S 2 3 4 COAX-F GND LNB1 GND R18 R25 2.0 >40V <0.5ohms LNB B350A C19 100nF DR1040-221-R 220uH LNB1 0805 C20 220nF C21 10nF LNBTVS6-221S 2 3 4 COAX-F GND LNB1 GND 2.0 >40V <0.5ohms LNB LNB out2 BFGATE1 BFGATE1 SW2 SLEEP\\ GND 10k 1206:25V C22 1.0uC1 100u C2 100u 1uH C17 100u 1uH

Worcester, Massachusetts 01615-0036 U.S.A. Table 8. Component Selection Table for Schematic 3

3 Panasonic EEU-FM1E101 P12924-ND

D2,D3,D3a,D3b Schottky diode, 50 V, 3 A SMA 6 Diodes, Inc.

2 Cooper Bussman DRA73-4R7-R 283-3617-1-ND

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Schematic 4. A8302 application circuit using ceramic capacitors on BOOST and 939 kHz switching frequency . Iout(max) = 500 mA. See table 9 for bill of materials pads pads 4.7uH C3 100nF C12 220nF CTCA P1 100nF GND GND B140 100nF 100 10nF RSET1 60K SDA SCL IRQ GND PGND and GND form a single point ground at U1 VIN CTCAP2 100nF GND R9 100 C11 10nF LNB1 LNB2 D3a B350A LNB out2 LNB out1 C18 1uF 1206 50V TCTRL 2 TCTRL 1 LNB out1 GND 4.7uH C16 100nF B140 VIN D3b B350A C10 1uF 1206 50V GND GND RSET2 60K GND RT1 10k RT2 10k SDA14 ADD15 SCL13 GND28 TCTRL 117 VIN29 IRQ16 TDI1 4 BO OST2 LNB1 2 BOOST1 VCP1 TCAP 1 21 LX2 G ND LX1 VREG24 LX PAD0 ISET119 LNB2 7 TCTRL 218 GND LX2 TDI2 5 VCP2 TCAP 2 22 NC 12 SLEEP23 ISET220 TDO126 TDO225 EPF BFGATE1 3 BFGATE2 6 A 8302 R11a 205k R12a 102k GND EPF EPF C10a 100nF Jumper Vin Jumper Vreg B350A C7 100nF DR1040-221-R 220uH LNB1 0805 220nF 10nF D4 LNBTVS6-221S 2 3 4 COAX-F GND LNB1 GND R18 R25 2.0 >40V <0.5ohms LNB B350A C19 100nF DR1040-221-R 220uH LNB1 0805 C20 220nF C21 10nF LNBTVS6-221S 2 3 4 COAX-F GND LNB1 GND 2.0 >40V <0.5ohms LNB LNB out2 BFGATE1 BFGATE1 2*4.7uF 2*10uF or 3*4.7uF C17 2*10uF or 3*4.7uF SW2 SLEEP\\ GND 10k A8302

Worcester, Massachusetts 01615-0036 U.S.A. Table 9. Component Selection Table for Schematic 4 D2,D3,D3a,D3b Schottky diode, 50 V, 3 A SMA 6 Diodes, Inc.

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package ET 32-Pin QFN with Exposed Thermal Pad For Reference Only – Not for Tooling Use (Reference JEDEC MO-220VHHD-5) Dimensions in millimeters – NOT TO SCALE Exact case and lead configuration at supplier discretion within limits shown A A B C B 3.40 3.40

0.50 BSC

5.00 ±0.05 5.00 ±0.05 0.90 ±0.10 0.25 +0.05 -0.07 0.40 ±0.10 3.40 3.40 0.30 0.50 1.00 5.00 5.00 C C0.08 33X SEATING PLANE CD D PCB Layout Reference View Terminal #1 mark area Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) Reference land pattern layout (reference IPC7351 QFN50P500X500X100-33V6M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Coplanarity includes exposed thermal pad and terminals

Dual LNB Supply and Control Voltage RegulatorsA8302 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. I2C™ is a trademark of Philips Semiconductors. DiSEqC™ is a trademark of Eutelsat S.A. Copyright ©2012-2014, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.