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Intended for analog and digital satellite receivers, this single low noise block converter regulator (LNBR) is a monolithic linear and switching voltage regulator, specifically designed to provide the power and the interface signals to an LNB down converter via coaxial cable. The A8294 requires few external components, with the boost switch and compensation circuitry integrated inside of the device. A high switching frequency is chosen to minimize the size of the passive filtering components, further assisting in cost reduction. The high levels of component integration ensure extremely low noise and ripple figures. The A8294 has been designed for high efficiency, utilizing the Allegro ™ advanced BCD process. The integrated boost switch has been optimized to minimize both switching and static losses. To further enhance efficiency, the voltage drop across the tracking regulator has been minimized. For DiSEqC™ communications, several schemes are available for generating tone signals, all the way down to no-load, and using either the internal clock or an external time source. A comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, and power not good. 8294-DS, Rev. 5 Features and Benefits ▪ 2-wire serial I2C™ -compatible interface: control (write) and status (read) ▪ LNB voltages (6 programmable levels) compatible with all common standards ▪ Tracking switch-mode power converter for lowest dissipation ▪ Integrated converter switches and current sensing ▪ Provides up to 700 mA continuous load current ▪ Output current limit of 800 mA minimum, with 48 ms timer ▪ Static current limit circuit allows full current at startup and 13→18 V output transition; reliably starts wide load range ▪ Push-pull output stage minimizes 13→18 V and 18→13 V output transition times for highly capacitive loads ▪ Adjustable rise/fall time via external timing capacitor ▪ Built-in tone oscillator, factory-trimmed to 22 kHz facilitates DiSEqC™ tone encoding, even at no-load ▪ Two methods of 22 kHz tone generation, including outgoing tone verification (TDET) ▪ Auxiliary modulation input ▪ LNB overcurrent with timer ▪ Diagnostics for output voltage level, input supply UVLO, and DiSEqCTM tone output Single LNB Supply and Control Voltage Regulator Continued on the next page… Functional Block Diagram A8294 LX Boost Converter LNB BOOSTVIN TCAP 22 nF Clock Divider VCP VOUT D3 and D4 are used for surge protection. 100 nF SDA SCL ADD Fault Monitor OCP PNG TSD VUV EXTM VDD VS IRQ Charge Pump Oscillator Regulator VREG TCAP fsw fsw 22 kHz EXTM TGate GNDLX DAC LNB Voltage Control Wave Shape Linear Stage 10 nF 220 nF C10 100 nF 220 nF R1 R2 R3 33 μH D1 A A A GND I2 C™- Compatible Interface Tone Detect TDI TDO 10 nF C10R8 100 7 100 μF 100 μF C5 1 μF PAD nF 100 Package: 20-contact 4 × 4 mm MLP/QFN (suffix ES) For recommended external components, refer to table 7
Single LNB Supply and Control Voltage RegulatorA8294 2Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A. Selection Guide Part Number Packing a Description A8294SESTR-Tb 7 in. reel, 1500 pieces/reel 12 mm carrier tape ES package, MLP/QFN surface mount 4 mm × 4 mm × 0.75 mm nominal height aContact Allegro for additional packing options. bLeadframe plating 100% matte tin. The device uses a 2-wire bidirectional serial interface, compatible with the I2C™ standard, that operates up to 400 kHz. The A8294 is supplied in a lead (Pb) free MLP/QFN package, ES, 20-contact, 4 mm × 4 mm, 0.75 nominal overall height. Description (continued) Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 37 ºC/W *Additional thermal information available on the Allegro website Absolute Maximum Ratings Characteristic Symbol Conditions Rating Units Load Supply Voltage, VIN pin V IN 30 V Output Current1 IOUT Internally Limited A Output Voltage, BOOST pin –0.3 to 33 V Output Voltage, LNB pin Surge2 –1 to 33 V Output Voltage, LX pin –0.3 to 30 V Output Voltage, VCP pin V CP –0.3 to 41 V Logic Input Voltage, EXTM pin –0.3 to 5 V Logic Input Voltage, other pins –0.3 to 7 V Logic Output Voltage –0.3 to 7 V Operating Ambient Temperature T A –20 to 85 °C Junction Temperature T J(max) 150 °C Storage Temperature T stg –55 to 150 °C 1Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the speci- fied current ratings, or a junction temperature, TJ, of 150°C. 2Use Allegro recommended Application circuit.
Single LNB Supply and Control Voltage RegulatorA8294 3Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. PAD LNB GND LX VIN NC TDI GND VREG SDA ADD FLOAT GND NC SCL IRQ BOOST VCP TCAP FLOAT EXTM Terminal List Table Name Number Function ES ADD 10 Address select FLOAT 4, 15 These pins must not be connected to anything; do not ground these pins BOOST 1 Tracking supply voltage to linear regulator EXTM 5 External modulation input GND 7, 14 Signal ground GNDLX 19 Boost switch ground IRQ 11 Interrupt request LNB 20 Output voltage to LNB LX 18 Inductor drive point NC 13, 16 No connection PAD Pad Exposed pad; connect to the ground plane, for thermal dissipation SCL 12 I 2C™-compatible clock input SDA 9 I 2C™-compatible data input/output TCAP 3 Capacitor for setting the rise and fall time of the LNB output TDI 6 Outgoing Tone Detect Feedback (for verification) VCP 2 Gate supply voltage VIN 17 Supply input voltage VREG 8 Analog supply Device Pin-out Diagram (Top View)
Single LNB Supply and Control Voltage RegulatorA8294 4Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS at TA = 25°C, VIN = 10 to 16 V, unless noted otherwise1 Characteristics Symbol Test Conditions Min. Typ. Max. Units General Set-Point Accuracy, Load and Line Regulation2 Err Relative to selected VLNB target level, ILOAD = 0 to 450 mA –3.0 – 3.0 % Supply Current IIN(Off) ENB bit = 0, LNB output disabled, VIN = 12 V – – 10.0 mA IIN(On) ENB bit = 1, LNB output enabled, ILOAD = 0 mA, VIN = 12 V – – 19.0 mA Boost Switch On Resistance R DS(on)BOOST ILOAD = 450 mA – 300 – m Ω Switching Frequency f SW 320 352 384 kHz Switch Current Limit I LIMSW VOUT = 19.0 V – 2.7 – A Linear Regulator Voltage Drop ∆VREG VBOOST – VLNB, no tone signal, ILOAD = 450 mA – 800 – mV TCAP Pin Current ICHG TCAP capacitor (C7) charging –12.5 –10 –7.5 μA IDISCHG TCAP capacitor (C7) discharging 7.5 10 12.5 μA Output Voltage Rise Time3 tr(VLNB) For VLNB 13 → 18 V; CTCAP = 5.6 nF, ILOAD = 450 mA – 500 – μs Output Voltage Pull-Down Time3 tf(VLNB) For VLNB 18 → 13 V; CLOAD = 100 μF, ILOAD = 0 mA – 12.5 – ms Output Reverse Current I RLNB ENB bit = 0, VLNB = 33 V , BOOST capacitor (C5) fully charged –1 5 m A Ripple and Noise on LNB Output4 Vrip,n(pp)
20 MHz BWL; reference circuit shown in
Functional Block diagram; contact Allegro for additional information on application circuit board design –3 0 – m V PP Protection Circuitry Output Overcurrent Limit5 ILIMLNB VBOOST – VLNB = 800 mV 800 850 950 mA Overcurrent Disable Time t DIS –4 8 – m s VIN Undervoltage Lockout Threshold V UVLO VIN falling 7.05 7.35 7.65 V VIN Turn On Threshold V IN(th) VIN rising 7.40 7.70 8.00 V Undervoltage Hysteresis V UVLOHYS – 350 – mV Thermal Shutdown Threshold3 TJ – 165 – °C Thermal Shutdown Hysteresis3 ∆TJ –2 0 – ° C Power Not Good Flag Set PNG SET With respect to VLNB 77 85 93 % Power Not Good Flag Reset PNG RESET With respect to VLNB 82 90 98 % Power Not Good Hysteresis PNG HYS With respect to VLNB –5 – % Tone Tone Frequency f TONE 20 22 24 kHz Tone Amplitude, Peak-to-Peak V TONE(pp) ILOAD = 0 to 450 mA, CLOAD = 750 nF 400 620 900 mV Tone Duty Cycle DC TONE ILOAD = 0 to 450 mA, CLOAD = 750 nF 40 50 60 % Tone Rise Time t rTONE ILOAD = 0 to 450 mA, CLOAD = 750 nF 5 10 15 μs Tone Fall Time t fTONE ILOAD = 0 to 450 mA, CLOAD = 750 nF 5 10 15 μs Outgoing Tone Detection Outgoing Tone Amplitude, Peak to Peak3 VTDT(pp)init fTONE = 22 kHz sine wave, using internal tone 400 – – mV Outgoing Tone Frequency Capture3 fTDI 600 mVpp sine wave 20 – 24 kHz Continued on the next page…
Single LNB Supply and Control Voltage RegulatorA8294 5Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. I2C™-Compatible Interface Logic Input (SDA,SCL) Low Level V SCL(L) – – 0.8 V Logic Input (SDA,SCL) High Level V SCL(H) 2.0 – – V Logic Input Hysteresis V I2CIHYS – 150 – mV Logic Input Current I I2CI VI2CI = 0 to 7 V –10 <±1.0 10 μA Logic Output Voltage SDA and IRQ V t2COut(L) ILOAD = 3 mA – – 0.4 V Logic Output Leakage SDA and IRQ V t2CLKG Vt2COut = 0 to 7 V – – 10 μA SCL Clock Frequency f CLK – – 400 kHz Output Fall Time t fI2COut Vt2COut(H) to Vt2COut(L) – – 250 ns Bus Free Time Between Stop/Start t BUF 1.3 – – μs Hold Time Start Condition t HD:STA 0.6 – – μs Setup Time for Start Condition t SU:STA 0.6 – – μs SCL Low Time t LOW 1.3 – – μs SCL High Time t HIGH 0.6 – – μs Data Setup Time t SU:DAT 100 – – ns Data Hold Time t HD:DAT For tHD:DAT(min) , the master device must provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the SCL signal falling edge 0 – 900 ns Setup Time for Stop Condition t SU:STO 0.6 – – μs I2C™ Address Setting ADD Voltage for Address 0001,000 Address1 0 – 0.7 V ADD Voltage for Address 0001,001 Address2 1.3 – 1.7 V ADD Voltage for Address 0001,010 Address3 2.3 – 2.7 V ADD Voltage for Address 0001,011 Address4 3.3 – 5.0 V 1Operation at 16 V may be limited by power loss in the linear regulator. 2For the selected VLNB target level 13.375 V, Err(min) = –3.7%. 3Guaranteed by worst case process simulations and system characterization. 4LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layout recommendations. Not production tested. 5Current from the LNB output may be limited by the choice of Boost components. ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 10 to 16 V, unless noted otherwise1 Characteristics Symbol Test Conditions Min. Typ. Max. Units I2C™ Interface Timing Diagram tSU:STA t HD:STA t SU:DAT t HD:DAT t BUF tSU:STO tHIGH tLOW SDA SCL
Single LNB Supply and Control Voltage RegulatorA8294 6Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Protection The A8294 has a wide range of protection features and fault diag- nostics which are detailed in the Status Register section. Boost Converter/Linear Regulator The A8294 solution contains a tracking current-mode boost converter and linear regulator. The boost converter tracks the requested LNB voltage to within 800 mV , to minimize power dissipation. Under conditions where the input voltage, V BOOST , is greater than the output voltage, VLNB, the linear regulator must drop the differential voltage. When operating in these conditions, care must be taken to ensure that the safe operating temperature range of the A8294 is not exceeded. The boost converter operates at 352 kHz typical: 16 times the internal 22 kHz tone frequency. All the loop compensation, current sensing, and slope compensation functions are provided internally. The A8294 has internal pulse-by-pulse current limiting on the boost converter and DC current limiting on the LNB output to protect the IC against short circuits. When the LNB output is shorted, the LNB output current is limited to 700 mA typical, and the IC will be shut down if the overcurrent condition lasts for more than 48 ms. If this occurs, the A8294 must be reenabled for normal operation. The system should provide sufficient time between successive restarts to limit internal power dissipation; a minimum of 2 s is recommended. At extremely light loads, the boost converter operates in a pulse-skipping mode. Pulse skipping occurs when the BOOST voltage rises to approximately 450 mV above the BOOST target output voltage. Pulse skipping stops when the BOOST voltage drops 200 mV below the pulse skipping level. In the case that two or more set top box LNB outputs are con- nected together by the customer (e.g., with a splitter), it is pos- sible that one output could be programmed at a higher voltage than the other. This would cause a voltage on one output that is higher than its programmed voltage (e.g., 19 V on the output of a 13 V programmed voltage). The output with the highest voltage will effectively turn off the other outputs. As soon as this voltage is reduced below the value of the other outputs, the A8294 output will auto-recover to their programmed levels. Charge Pump. Generates a supply voltage above the internal tracking regulator output to drive the linear regulator control. Slew Rate Control. During either start-up, or when the output voltage at the LNB pin is transitioning, the output voltage rise and fall times can be set by the value of the capacitor connected from the TCAP pin to GND (CTCAP or C7 in the Applications Schematic). Note that during start-up, the BOOST pin is pre- charged to the input voltage minus a voltage drop. As a result, the slew rate control for the BOOST pin occurs from this voltage. The value of C TCAP can be calculated using the following for- mula: CTCAP = (ITCAP × 6) / SR , where SR is the required slew rate of the LNB output voltage, in V/s, and ITCAP is the TCAP pin current specified in the data sheet. The recommended value for CTCAP, 10 nF, should provide satisfactory operation for most applications. However, in some cases, it may be necessary to increase the value of CTCAP to avoid activating the current limit of the LNB output. One such situa- tion is when two set-top boxes are connected in parallel. If this is the case, the following formula can be used to calculate C TCAP: C TCAP ≥ (ITCAP × 6)(2 × CBOOST) / ILIMLNB , C TCAP ≥ (10 μA × 6)(2 × 100 μF) / 500 mA = 24 nF . The minimum value of CTCAP is 2.2 nF. There is no theoretical maximum value of CTCAP however too large a value will prob- ably cause the voltage transition specification to be exceeded. Tone generation is unaffected by the value of C TCAP . Pull-Down Rate Control. In applications that have to operate at very light loads and that require large load capacitances (in the order of tens to hundreds of microfarads), the output linear stage provides approximately 40 mA of pull-down capability. This ensures that the output volts are ramped from 18 V to 13 V in a reasonable amount of time. ODT (Overcurrent Disable Time) If the LNB output current exceeds 850 mA, typical, for more than 48 ms, then the LNB output will be disabled and the OCP bit will be set. Short Circuit Handling If the LNB output is shorted to ground, the LNB output current will be clamped to 850 mA, typical. If the short circuit condition lasts for more than 48 ms, the A8294 will be disabled and the OCP bit will be set. Auto-Restart After a short circuit condition occurs, the host controller should periodically reenable the A8294 to check if the short circuit has Functional Description
Worcester, Massachusetts 01615-0036 U.S.A. 2 s of delay between restarts. control bit, TMODE (tone mode), provides the necessary control. with the minimum tone detect amplitude of 400 mV . The two options for tone generation are shown in figure 1. Figure 1. Options for tone generation
Worcester, Massachusetts 01615-0036 U.S.A. to access the internal Control and Status registers of the A8294. depending on the direction of the data.
- Start Condition. Defined by a negative edge on the SDA line,
- Address Cycle. 7 bits of address, plus 1 bit to indicate read (1)
fined by the remaining two bits, are selected by the ADD input. The address is transmitted MSB first. Register section for more information.
- Stop Condition. Defined by a positive edge on the SDA line,
A8294 always responds by resetting the data transfer sequence. Figure 2. I2C™ Interface. Read and write sequences.
Worcester, Massachusetts 01615-0036 U.S.A. write operations must be preceded with the address. during the ninth clock cycle. clock cycle, in order to allow this handshaking to occur. of the SDA line and send the data from register 1 to the master. data and waits for a stop signal. register section for full description. changes when the LNB is either disabled, faulted, or is enabled. dicates that the A8294 is fully active with no fault conditions. Figure 3. I2C™ Interface. Read sequences after interrupt request.
Worcester, Massachusetts 01615-0036 U.S.A. bit 7). The power-up states for the control functions are all 0s. Table 1. Control Register Address (I1, I0) = 00
0 VSEL0
2 VSEL2
3 VSEL3
4 ODT 1 (recommended): The ODT functions are always
enabled, but setting 1 recommended at all times.
5 ENB
6 I0 Address Bit: 0
7 I1 Address Bit: 0
Bit 0 VSEL0 These three bits provide incremental control over the voltage on the LNB output. levels are defined in table 3, Output V oltage Amplitude Selection. Bit 3 VSEL3 Switches between the low level and high level output voltages on the LNB output. in steps of 333 mV using the VSEL2, VSEL1 and VSEL0 control register bits. Bit 4 ODT The overcurrent disable timer is always enabled. 0, the LNB output is disabled.
Worcester, Massachusetts 01615-0036 U.S.A. Table 2. Control Register Address (I1, I0) = 10
0 TMODE
1 TGATE Must be set to 1: Tone Ready
7 I1 Address Bit: 1
Bit 1 TGATE Tone Ready. Must be set to 1.
Worcester, Massachusetts 01615-0036 U.S.A. Table 3. Output Voltage Amplitude Selection
Worcester, Massachusetts 01615-0036 U.S.A. master, assuming the fault has been resolved. the condition of each bit when set and how it is reset. performed, register 1 is always read first. Status registers is all 0s, to simplify checking of the Status bit. Table 4. Status Register Bit Setting
Worcester, Massachusetts 01615-0036 U.S.A. Table 5. Status Register 1
0 DIS LNB output disabled
2 OCP Overcurrent
4 PNG Power Not Good
6 TSD Thermal Shutdown
7 VUV V
if the LNB output is enabled. OCP bit is reset in all cases, allowing the master to reenable the LNB output. mal shutdown occurs, the LNB output will be disabled and the TSD bit will be set. within 90% of the programmed LNB voltage. condition and has disabled the LNB output. The disable bit, DIS, will also be set. the condition is still present, then the TSD bit will remain at 1. put if required. If the condition is still present, then the VUV bit will remain at 1.
Worcester, Massachusetts 01615-0036 U.S.A. Table 6. Status Register 2
2 TDET Outgoing Tone Detect
pears at the LNB output. When the tone is disabled, TDET is reset.
Worcester, Massachusetts 01615-0036 U.S.A. Table 7. Component Selection Table
Single LNB Supply and Control Voltage RegulatorA8294 17Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package ES 20-Pin MLP/QFN 0.95 CSEATING PLANEC0.08 21X A Terminal #1 mark area Coplanarity includes exposed thermal pad and terminals B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) For Reference Only, not for tooling use (reference DWG-2864, JEDEC MO-220 WGGD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C D D C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 4.10 0.30 0.50 4.10 0.50 0.75 ±0.05 2.45 2.45 0.25 +0.05 –0.07 0.40 ±0.10 4.00 ±0.10 4.00 ±0.10 2.45 2.45 B PCB Layout Reference View
Single LNB Supply and Control Voltage RegulatorA8294 18Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. I2C™ is a trademark of Philips Semiconductors. DiSEqC™ is a trademark of Eutelsat S.A. Copyright ©2007-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.