A8186SLU

8186 ALLEGRO

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Technical content

LOW-DROPOUT,

3.3 V REGULATOR

Ñ FOR REFERENCE ONLY Designed specifically to meet the requirement for extended opera- tion of battery-powered equipment such as cordless and cellular telephones, the A8186SLU voltage regulator offers the reduced dropout voltage and quiescent current essential for maximum battery life. Applicable also to palmtop computers and personal data assistants, the device delivers a regulated, continuous 3.3 V output at up to 75 mA under normal operating conditions, or to 150 mA (transient) under worst-case conditions. A PMOS pass element provides a typical dropout voltage of only 85 mV at 60 mA of load current. The low dropout voltage permits deeper battery discharge before output regulation is lost. Furthermore, quiescent current does not increase as the dropout voltage is ap- proached, an ideal feature in standby/resume power systems where data integrity is crucial. Regulator accuracy and excellent temperature characteristics are provided by a bandgap reference. An ENABLE input gives the designer complete control over power up, standby, or power down. This device is supplied in a 6-lead small-outline plastic package (similar to the SOT-89/TO-243AA) for surface-mount applications. The A8186SLU is rated for operation over a temperature range of -20°C to +85°C. FEATURES AND BENEFITS n High Efficiency Provides Extended Battery Life n 85 mV Typical Dropout Voltage at IO = 60 mA n 45 µA Typical Quiescent Current at VI = 6 V Less Than 1 µA “Sleep” Current n Up to 150 mA Output Current n CMOS-Compatible ON/OFF Control For Power-Up, Standby, or Shutdown n Internal Thermal Protection n Surface-Mount Package

APPLICATIONS

n Cordless and Cellular Telephones n Personal Data Assistants n Personal Communicators n Palmtop Computers 8186 Data Sheet 27468.14 LOW-DROPOUT, 3.3 V REGULATOR — HIGH EFFICIENCY ABSOLUTE MAXIMUM RATINGS Operating Temperature Range, Junction Temperature, TJ . . . +150°C † Storage Temperature Range, * Output current rating is limited by input voltage, duty cycle, and ambient temperature. Under any set of conditions, do not exceed a junction temperature of +150°C. See next page. † Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated but should be avoided. Always order by complete part number:A8186SLU . PRELIMINARY INFORMATION (subject to change without notice) January 12, 1995 Dwg. PS-021-1 VR 3.3 V 2SUB 3ENABLE 1GND

6 OUT

LOW-DROPOUT,

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 FUNCTIONAL BLOCK DIAGRAM Dwg. FS-012-3 BIAS DRIVE ENABLE THERMAL PROTECT. BANDGAP REF. ERROR AMP IN ENABLE OUT4 6 3 2 GND SUB SUB SUB Terminal numbering is in accordance with EIA/JEDEC convention. Where EIAJ conventions apply, the tab is not numbered, resulting in terminal 6 being designated terminal 5. For proper operation, terminals 1 and 2 must be externally con- nected together. W Copyright © 1995 Allegro MicroSystems, Inc. MAXIMUM ALLOWABLE OUTPUT CURRENT with device mounted on 2.24" x 2.24" (56.9 mm x 56.9 mm) solder-coated copper-clad board in still air. Maximum Allowable Output Current in Milliamperes with VI = 8 V, TJ = 150°C, Period ≤10 s* dc (Duty Cycle) TA 100% 90% 80% 70% 60% 50% 40% 30% 20% 25°C 100 115 125 145 150 150 150 150 150 50°C 80 90 100 115 135 150 150 150 150 70°C 65 70 80 90 110 130 150 150 150 85°C 50 60 65 75 85 105 130 150 150 *IO = (TJ - TA)/([VI - VO ] RθJA • dc) = (150 - TA)/(4.7 • 258 • dc) Output current rating can be increased (to 150 mA maximum) by heat sinking or reducing the input voltage. Conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated but should be avoided.

LOW-DROPOUT, ELECTRICAL CHARACTERISTICS at TA = +25°C (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Voltage V O 4 V ≤ VI ≤ 8 V, T A = +25°C 3.25 3.30 3.35 V 10 µA ≤ IO ≤ 100 mA* -20°C ≤ TA ≤ +85°C 3.20 3.30 3.40 V Output Volt. Temp. Coeff. αVO VI = 6 V, IO = 10 mA — — ±1.0 mV/ °C Line Regulation ΔVO(ΔVI) 6 V ≤ VI ≤ 8 V, IO = 1 mA — 8.0 12 mV

4 V ≤ VI ≤ 6 V, IO = 1 mA — 10 20 mV

Load Regulation ΔVO(ΔIO) 1 mA ≤ IO ≤ 100 mA*, VI = 8 V — 20 30 mV 1 mA ≤ IO ≤ 100 mA*, VI = 6 V — 13 25 mV 1 mA ≤ IO ≤ 100 mA*, VI = 4 V — 8.0 20 mV Dropout Voltage V Imin - VO IO = 60 mA* — 85 150 mV IO = 125 mA* — 190 300 mV Quiescent Current I Q VI = 6 V, 1 mA ≤ IO ≤ 100 mA*, VE ≥ 2.0 V — 45 60 µA (GND terminal current) V I = 8 V, 1 mA ≤ IO ≤ 100 mA*, VE ≥ 2.0 V — 50 65 µA IQ(off) 4 V ≤ VI ≤ 8 V, VE ≤ 0.8 V — 0.05 1.0 µA ENABLE Input Voltage V EH 4 V ≤ VI ≤ 8 V, Output ON 2.0 — — V VEL -20°C ≤ TA ≤ +85°C Output OFF — — 0.8 V ENABLE Input Current I E TA ≤ +85°C, VE = VI = 8 V — — ±0.1 µA Thermal Shutdown Temp. T J 150 — — °C Thermal Resistance R θJA Mounted on 2.24" x 2.24" solder-coated — 258 — °C/W copper-clad board in still air Typical values are at TA = +25°C and are given for circuit design information only. * Pulse test (≤20 ms). See previous page for duty cycle limitations.

LOW-DROPOUT, Worcester, Massachusetts 01615-0036 (508) 853-5000 TYPICAL CHARACTERISTICS LOAD REGULATION LINE REGULATION OUTPUT CURRENT in mA Dwg. GP-052-6 25 50 100 150 75 T = -20°CA 3.34 3.30 3.32 3.28 OUTPUT VOLTAGE in VOLTS 3.26 3.24 3.36 3.22 125 V = 8 VI V = 4 VI V = 6 VI 2.0 Dwg. GP-053-6 T = -20°C 50 mA INTERVALS A3.34 3.30 3.32 3.28 OUTPUT VOLTAGE in VOLTS 3.26 3.24 3.36 3.22 I = 0 mAO I = 100 mAO INPUT VOLTAGE in VOLTS 7.0 OUTPUT CURRENT in mA Dwg. GP-052-7 25 50 100 150 75 T = 25°C

2 V INTERVALS

A 3.34 3.30 3.32 3.28 OUTPUT VOLTAGE in VOLTS 3.26 3.24 3.36 3.22 125 V = 4 VI V = 8 VI 2.0 Dwg. GP-053-7 T = 25°C 50 mA INTERVALS A3.34 3.30 3.32 3.28 OUTPUT VOLTAGE in VOLTS 3.26 3.24 3.36 3.22 I = 0 mAO INPUT VOLTAGE in VOLTS 7.0 I = 100 mAO CAUTION: Maximum allowable duty cycle will be significantly less than 100% at high temperatures, at high input voltages, or at high output currents. See Maximum Allowable Output Current table.

LOW-DROPOUT, TYPICAL CHARACTERISTICS (contÕd) LOAD REGULATION LINE REGULATION OUTPUT VOLTAGE OUTPUT CURRENT in mA Dwg. GP-052-8 25 50 100 150 75 T = 85°C A 3.34 3.30 3.32 3.28 OUTPUT VOLTAGE in VOLTS 3.26 3.24 3.36 3.22 V = 4 VI V = 8 VI 125 2.0 Dwg. GP-053-8 T = 85°C 50 mA INTERVALS A 3.34 3.30 3.32 3.28 OUTPUT VOLTAGE in VOLTS 3.26 3.24 3.36 3.22 I = 0 mAO INPUT VOLTAGE in VOLTS 7.0 I = 100 mAO -50 AMBIENT TEMPERATURE in °C Dwg. GP-050-2 3.31 3.29 0 +50 3.30 +100 3.28 OUTPUT VOLTAGE in VOLTS V = 6 V I = 0 I O 1.0 Dwg. GP-059-1 2.0 4.03.0 INPUT VOLTAGE in VOLTS 3.0 2.0 2.5 1.5 OUTPUT VOLTAGE in VOLTS 1.0 0.5 3.5 I = 0 - 100 mA O T = 25°CA CAUTION: Maximum allowable duty cycle will be significantly less than 100% at high temperatures, at high input voltages, or at high output currents. See Maximum Allowable Output Current table.

LOW-DROPOUT, Worcester, Massachusetts 01615-0036 (508) 853-5000 TYPICAL CHARACTERISTICS (contÕd) QUIESCENT (GROUND TERMINAL) CURRENT -50 AMBIENT TEMPERATURE in °C Dwg. GP-051-1 0 +50 +100 QUIESCENT (GROUND TERMINAL) CURRENT in mA V = 6 V I = 0 V ‡ 2 V I O E 2.0 Dwg. GP-058 4.0 8.06.0 INPUT VOLTAGE in VOLTS QUIESCENT (GROUND TERMINAL) CURRENT in mA I = 0 O T = 25°CA T = -20°CA T = 85°CA OUTPUT CURRENT in mA Dwg. GP-054-1 25 50 100 150 75 T = -20°C T = 25°C T = 85°CA A A0.15 0.20 0.10 DROPOUT VOLTAGE in VOLTS0.05 0.25 125 DROPOUT VOLTAGE CAUTION: Maximum allowable duty cycle will be significantly less than 100% at high temperatures, at high input voltages, or at high output currents. See Maximum Allowable Output Current table.

LOW-DROPOUT, TYPICAL CHARACTERISTICS (concluded) LOAD TRANSIENT PERFORMANCE VI = 3.5 V to 6.5 V, CO as specified, TA = 25°C ENABLE TRANSIENT PERFORMANCE VI = 3.5 V to 6.5 V, CO = 1 µF, TA = 25°C Dwg. WP-028-1 VO IO 100 mA 1 mA 3.8 V 3.3 V 2.8 V <50 ms <600 ms VO 3.55 V 3.3 V 3.05 V C = 10 mFO C = 1 mFO Dwg. WP-027-2 VO VE 3.3 V <100 ms <150 ms V I

LOW-DROPOUT, Worcester, Massachusetts 01615-0036 (508) 853-5000 Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor’s option within limits shown. 3.Terminal numbering is in accordance with EIA/JEDEC convention. Where EIAJ conventions apply, the tab is not numbered, resulting in terminal 6 being designated terminal 5. Dwg. MA-009-6 in 2 3 0.059 BSC 0.019 MAX (5 PL) 0.035 MIN 0.055 0.063 0.017 MAX 0.084 0.090 6 5 4 0.173 0.181 0.094 0.102 0.021 MAX 0.173 0.181 0.055 0.079 0.118 BSC Dwg. MA-009-6 mm 2 3 1.5 BSC 0.49 MAX (5 PL) 0.9 MIN 1.4 1.6 0.44 MAX 2.13 2.29 6 5 4 4.4 4.6 2.4 2.6 0.54 MAX 4.4 4.6 1.4 1.8 3.00 BSC