A81805 Datasheet | DigiCamel IC Datasheet

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A81805 ALLEGRO

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Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
PDF pages: 30

Technical content

The A81805 is a full-featured, 2.5 A, low EMI, DC-DC regulator designed to satisfy demanding power delivery requirements of automotive and industrial applications. The A81805 and A81805-1 include all the control and protection circuitry to produce a robust 3.3 V or 5 V DC output voltage respectively, with ±1.5% output voltage accuracy over the full operating temperature range. Fixed-frequency peak current-mode control is employed to ensure rapid response to load and line transients with programmable switching frequency from 400 kHz to 2.5 MHz. Connect the FSET pin to VCC for a 2.2 MHz switching frequency. The A81805 can also synchronize to an external clock applied to the SYNC pin ranging from 400 kHz to 2.5 MHz. Spread spectrum operation (dithering) is applied, offering lower EMI levels. Low power (LP) mode maintains the output voltage at no load or very light load conditions while drawing only micro-amps from VIN. No-load input current is a mere 6 µA when operating from a standard 12 V battery. The A81805 automatically transitions between PWM and LP modes. Integrated loop compensation components simplify the design process while providing fast response to load and line transients. The A81805 has an internally set soft-start and an open-drain power good output. The accurate ENABLE input has programmable turn-on and turn- off thresholds and a low shutdown current of 1 µA if driven low. Extensive protection features include pulse-by-pulse current limit, hiccup mode short-circuit protection, BOOT open/short voltage protection, VIN undervoltage lockout, VOUT overvoltage protection, and thermal shutdown. The A81805 is supplied in a thermally enhanced, 4 mm × 4 mm × 0.75 mm 20-pin wettable flank QFN package (suffix “ES”) with exposed power pad. A81805-DS, Rev. 1 MCO-0001187

AEC-Q100 Grade 0 qualified
VIN Range: 3.5 to 36 V operating, 40 V transient
VOUT: 3.3 V , ±1.5% accuracy, ‒40°C to 150°C (5 V for the A81805-1)
Up to 2.5 A of continuous output current
High Efficiency: 92%, 12 V input to 5 V output, 1 A, 2 MHz
Integrated Compensation: Eliminates three external components
Low-Power (LP) mode: 6 µA IQ from VIN at no load, automatic transition from LP to PWM mode
Fixed-Frequency PWM (fOSC): 400 kHz to 2.5 MHz programmable
Synchronizable Switching Frequency (400 kHz to

2.5 MHz): PLL-based, fSYNC can be above or below fOSC

Spread spectrum applied: Helps to pass CISPR25 class 5
Internally set Soft-Start
Accurate ENABLE input threshold
Open-drain PGOOD output with delay
Pre-bias startup capable
Maximized duty cycle at low VIN improves dropout
Overvoltage, pulse-by-pulse current limit, hiccup mode short-circuit, and thermal protections
Robust FMEA: pin open/short and component faults 40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 FEATURES AND BENEFITS DESCRIPTION February 11, 2022

APPLICATIONS

Infotainment
Battery-powered systems
Industrial systems
Container tracking
Handheld instruments
Instrument clusters
Audio systems
ADAS PACKAGE Figure 1: Typical Application DiagramNot to scale CIN CVCC CBOOT LOUT RPG FSET VCC PGND VIN EN VOUT SW BOOT SYNC PGOOD PAD A81805 COUT VOUTVIN 20-contact QFN 4 mm × 4 mm × 0.75 mm with exposed thermal pad and wettable flank (suffix ES)

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ABSOLUTE MAXIMUM RATINGS [2] Characteristic Symbol Notes Rating Unit VIN, EN, PGOOD VIN, VEN, VPGOOD –0.3 to 40 V VOUT VOUT -0.3 to 20 V SW VSW Continuous –0.3 to VIN + 0.3 [3] V VIN ≤ 36 V, t < 50 ns –1.0, VIN + 2 V BOOT VBOOT Continuous VSW – 0.3 to VSW + 5.5 V t < 1 ms VSW – 0.3 to VSW + 7.0 V All other pins –0.3 to 5.5 V Operating Junction Temperature TJ(max) –40 to 150 °C Storage Temperature Range Tstg –55 to 150 °C [2] Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [3] This voltage is a function of temperature. SELECTION GUIDE Part Number VOUT (V) Package Packing [1] Lead Frame A81805KESJSR 3.3 20-pin 4 mm × 4 mm × 0.75 mm QFN with exposed thermal pad and wettable flank 6000 pieces per 7-inch reel 100% matte tin A81805KESJSR-1 5 [1] Contact Allegro for additional packing options. THERMAL CHARACTERISTICS Characteristic Symbol Test Conditions [4] Value Unit Junction-to-Ambient Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 37 °C/W On Allegro Evaluation Board [5] 31 °C/W Junction-Case Thermal Resistance RθJC On Allegro Evaluation Board [5] 8 °C/W [4] Additional thermal information available on the Allegro website. [5] See Figure 10: PCB Reference Design.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com TERMINAL DIAGRAM AND TERMINAL LIST 5 11 6 7 8 9 10 1617181920 VOUT NC GND FSET SYNC PGNDPGND NC VIN VIN VIN EN PGOOD NC VCC BOOTSWSWSWSW Terminal List Number Name Function 1 VOUT Output voltage feedback path for the regulator. Powers the internal LDO when the output voltage level is in regulation. Connect this pin to the output of the regulator. 2 NC No connect. 3 GND Analog ground pin. 4 FSET Switching frequency programming pin. A resistor, RFSET, from this pin to GND sets the switching frequency, fSW. Connect FSET directly to VCC to program a fixed 2.2 MHz (typical) frequency. 5 SYNC PWM mode switching frequency pin. Applying an external clock (at SYNC pin) forces PWM mode and synchronizes the PWM switching frequency with dither to the external clock. 6, 7 PGND Power ground pins. 8 NC No connect. 9, 10, 11 VIN Input voltage pin. Place a small ceramic bypass capacitor from VIN to GND very close to this pin. 12 EN ENABLE pin with a hysteretic comparator with an accurate 1.2 V (typical) threshold. Connect EN directly to VIN for “always-on” applications and pull to GND to disable the converter. 13 PGOOD Power Good open-drain output signal. If the output voltage is out of range (undervoltage or overvoltage), this pin will be asserted low. 14 NC No connect. 15 VCC Internal voltage regulator bypass capacitor pin. Connect a 4.7 µF ceramic capacitor from VCC to PGND very close to this pin. 16 BOOT High-side N-channel MOSFET drive supply pin. Connect a 100 nF ceramic capacitor from BOOT to SW. 17, 18, 19, 20 SW Regulator switch node output pins. Connect these pins to the power inductor and keep this node small to minimize EMI. – PAD Exposed thermal pad. Connect to PCB PGND plane for best thermal performance.

3.55 V UVLO

3.3 V LDO 0.8 V VCC EN tDIS 2.5 V REGOK EN LD BOOT REG BOOT FAULT LD Current Sense Amp GcsENd REGOK UVLO ENd OV TSD VCC SW PGND FBUV Slope Compensation Ramp Offset PLL+ Dither Div 2 or 4 Start up or Hiccup or Dropout FB toff CLK FAULT SYNC PWM COMP 0.8 V SWGNDSC FBOV VINSWSC 0.88 V 0.74 V FBUV FBOV Error Amp Over Current ClampOCL OCL HLP Clamp MODE 0.804 V SLEEP LP Mode Comparator MODE GND PGOOD Soft Start Hiccup, Dropout, Stop- Start Recovery, Fault, Start-up Delay SLEEP FB OSC MODE 1.2 V 1.2 V VCC VCC VOUT VOUT ss FSET FB LDO VOUT ↑ 3.15 V REGOK

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Characteristics Symbol Test Conditions Min. Typ. Max. Unit INPUT SUPPLY Input Voltage Range VIN VIN must first rise above VUVLO(ON)(MAX) 3.5 − 36 V Undervoltage Lockout (UVLO) Start VUVLO(ON) VIN rising 3.35 3.55 3.8 V Undervoltage Lockout (UVLO) Stop VUVLO(OFF) VIN falling 3.1 3.3 3.5 V Undervoltage Lockout Hysteresis VUVLOHYS − 250 − mV INPUT SUPPLY CURRENT Input Shutdown Current [1] IIN(SD) VIN = 12 V, VEN = 0 V, VSW = VIN, TJ = 25°C − 1 2.9 µA Input Current, PWM Mode [1] IIN(PWM) VIN = 12 V, VEN = 2 V, no load, no switching − 5 6.5 mA 3.3 VOUT LP Input Current [1][2] ILP(3.3V) VIN = 12 V, IOUT = 0 A, TJ = 25°C − 6 − µA VIN = 12 V, IOUT = 50 µA, TJ = 25°C − 24.3 − µA 5.0 VOUT LP Input Current [1][2] ILP(5.0V) VIN = 12 V, IOUT = 0 A, TJ = 25°C − 7.5 − µA VIN = 12 V, IOUT = 50 µA, TJ = 25°C − 40 − µA REGULATION ACCURACY VOUT Voltage Accuracy VOUT(ACC) −40°C < TJ < 150°C, VIN = 12 V (A81805) 3.251 3.3 3.349 V −40°C < TJ < 150°C, VIN = 12 V (A81805-1) 4.926 5 5.074 V SWITCHING FREQUENCY AND DITHERING (FSET PIN) PWM Switching Frequency fOSC FSET connected to VCC 1.98 2.2 2.42 MHz RFSET = 14.3 kΩ 1.935 2.15 2.365 MHz RFSET = 34 kΩ 0.9 1 1.1 MHz RFSET = 71.5 kΩ 450 500 550 kHz RFSET = 86.6 kΩ 360 410 460 kHz External clock on SYNC pin at fSW(SYNC) − fSW(SYNC) − kHz Dropout Switching Frequency fDROP − fOSC / 2 − kHz PWM Frequency Dither Range fDITH(RNG) − ±5 ±6.5 % of fOSC PWM Dither Modulation Frequency fDITH(FREQ) − ±0.5 − % of fOSC PULSE WIDTH MODULATION (PWM) TIMING AND CONTROL Minimum Controllable SW On-Time tON(MIN) VIN = 12 V, IOUT = 0.5 A, VBOOT – VSW = 3.3 V, TJ = 25°C − 45 70 ns Minimum SW Off-Time tOFF(MIN) VIN = 12 V, IOUT = 0.5 A, TJ = 25°C − 70 95 ns LOW POWER (LP) MODE LP Output Voltage Ripple [2][3] VPP(HLP) LP Mode, 8 V < VIN < 16 V, COUT = 47 µF − − 50 mV INTERNAL MOSFET PARAMETERS High-Side On Resistance RDSON(HS) TJ = 25°C, VIN = 12 V, VBOOT – VSW = 3.3 V, IDS = 1 A − 170 200 mΩ Low-Side On Resistance RDSON(LS) TJ = 25°C, VIN = 12 V, IDS = 1 A − 130 160 mΩ High-Side Leakage Current [1] ILKG(HS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 0 V − − 3.5 µA Low-Side Leakage Current [1] ILKG(LS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 12 V − − 1.5 µA Gate Drive Non-Overlap Time tNO VBOOT – VSW = 3.3 V − 5 − ns Switch Node Rising Slew Rate SRHS 12 V < VIN < 16 V, VBOOT – VSW = 3.3 V − 4 − V/ns ELECTRICAL CHARACTERISTICS: Valid at 3.5 V ≤ VIN ≤ 36 V, −40°C ≤ TJ ≤ 150°C, unless otherwise specified. Continued on the next page…

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Characteristics Symbol Test Conditions Min. Typ. Max. Unit MOSFET CURRENT PROTECTION THRESHOLDS High-Side Current Limit ILIM(HS) 3.1 3.8 4.5 A Low-Side Negative Current Limit [4] ILIM(LSx) − 1.7 − A SYNCHRONIZATION INPUT (SYNC PIN) Synchronization Frequency Range fSW(SYNC) RFSET tuned accordingly 0.4 − 2.5 MHz SYNC Duty Cycle DCSYNC 20 50 70 % SYNC Pulse Width tPWSYNC 80 − − ns SYNC Voltage Thresholds [4] VSYNC(HI) VSYNC rising − 1.35 1.5 V VSYNC(LO) VSYNC falling 0.8 1.2 − V SYNC Hysteresis VSYNC(HYS) VSYNC(HI) ‒ VSYNC(LO) − 150 − mV SYNC Pin Current [1] ISYNC VSYNC = 5 V − 1 − µA SOFT-START Soft-Start Delay Time [4] tdSS − 600 − µs Soft-Start Ramp Time [4] tSS − 880 − µs Soft-Start Frequency Foldback fSW(SS) 0 V < VOUT < 0.825 V, 3.3 VOUT option − fOSC/4 − − 0.825 V < VOUT < 1.65 V, 3.3 VOUT option − fOSC/2 − − 1.65 V < VOUT, 3.3 VOUT option − fOSC − − 0 V < VOUT < 1.25 V, 5 VOUT option − fOSC/4 − − 1.25 V < VOUT < 2.5 V, 5 VOUT option − fOSC/2 − −

2.5 V < VOUT, 5 VOUT option − fOSC − −

High-Side Overcurrent Count HIC_OC − 120 − fOSC count SW Short-to-Ground Count HIC_SW,GND − 3 − fOSC count BOOT Over/Undervoltaage Count [5] HICBOOT − 120 − fOSC count Hiccup Period [2] tHIC − 20 − ms OUTPUT VOLTAGE PROTECTION THRESHOLDS (V OUT, OV, UV) VOUT Overvoltage Threshold in PWM Mode VOUT(OV) VOUT rising, 3.3 VOUT option 3.45 3.55 3.65 V VOUT rising, 5 VOUT option 5.25 5.375 5.5 V VOUT Overvoltage Hysteresis in PWM Mode VOUT(OV,HYS) VOUT falling, relative to VOUT(OV), 3.3 VOUT option − 40 − mV VOUT falling, relative to VOUT(OV), 5 VOUT option − 94 − mV VOUT Undervoltage Threshold in PWM Mode VOUT(UV) VOUT falling 3.3 VOUT option 2.95 3.05 3.15 V VOUT falling, 5 VOUT option 4.47 4.625 4.78 V VOUT Undervoltage Hysteresis in PWM Mode VOUT(UV,HYS) VOUT rising, relative to VOUT(UV), 3.3 VOUT option − 40 − mV VOUT rising, relative to VOUT(UV), 5 VOUT option − 94 − mV VOUT Undervoltage Threshold in LP Mode [2] VOUT(UV,HLP) VOUT falling, 3.3 VOUT option 2.75 2.9 3.05 V VOUT falling, 5 VOUT option 4.15 4.375 4.6 V ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, −40°C ≤ TJ ≤ 150°C, unless otherwise specified. Continued on the next page…

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Characteristics Symbol Test Conditions Min. Typ. Max. Unit POWER GOOD OUTPUT (PGOOD PIN) PGOOD Startup (SU) Delay tdPG(SU) Increasing VOUT due to startup − 30 − µs PGOOD Undervoltage (UV) Delay tdPG(UV) Decreasing VOUT 100 120 − µs PGOOD Overvoltage (OV) Delay tdPG(OV) After overvoltage event − 310 − µs PGOOD Low Output Voltage VPG(L) IPGOOD = 5 mA − 200 400 mV PGOOD Leakage Current [1] IPG(LKG) VPGOOD = 5.5 V − − 2 µA EN PIN INPUT EN High Threshold VEN(HI) VEN rising 1.14 1.2 1.26 V EN Input Hysteresis VEN(HYS) VENHI – VENLO 150 200 250 mV Disable Delay tdDIS VEN transitions low to when SW stops − 155 − µs EN Pin Input Current IVEN VEN = 5 V 0.8 1.6 2.4 µA BOOT REGULATOR (BOOT PIN) BOOT Charging Frequency fBOOT − fOSC − − BOOT Voltage VBOOT VIN = 12 V, VBOOT – VSW − 3.2 3.66 V INTERNAL REGULATOR (VCC PIN) VCC Voltage VCC VOUT = 5 V, 5 V option 3.1 3.3 3.66 V THERMAL SHUTDOWN PROTECTION (TSD) TSD Rising Threshold [2] TTSD TJ rising, PWM stops immediately 155 170 − °C TSD Hysteresis [2] TTSDHYS TJ falling, relative to TTSD − 20 − °C [1] Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. [2] Ensured by design, characterization, and statistical correlation; not production tested. [3] Validated using component values shown in Table 1: Recommended External Filter Component Values. [4] Limits ensured by design, characterization, and statistical correlation. Only functionally tested in production. [5] Only for protection at startup. ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com TYPICAL OPERATING CHARACTERISTICS 0 0.5 11 .5 22 .5 Load Current (A) 100Efficiency (%) Efficiency vs. Load VOUT = 3.3V, fSW = 2.2 MHz 12 V 24 V VIN 0.01 0.1 11 0 100 1000 Load Current (mA) 100Efficiency (%) Efficiency vs. Load (Light Load) VOUT = 3.3V, fSW = 2.2 MHz 12 V 24 V VIN 0 0.5 11 .5 22 .5 Load Current (A) 100Efficiency (%) Efficiency vs. Load VOUT = 5V, fSW = 2.2 MHz 12 V 24 V VIN 0.01 0.1 11 01 00 1000 Load Current (mA) 100Efficiency (%) Efficiency vs. Load (Light Load) VOUT = 5V, fSW = 2.2 MHz 12 V 24 V VIN

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com EMI/EMC PERFORMANCE CHARACTERISTICS EMI test results are obtained using standard A81805 demo board with input EMI filter. VIN = 12 V , VOUT = 5 V , fSW = 400 kHz. Conducted Emissions Radiated Emissions (150 kHz – 30 MHz) Radiated Emissions (30 MHz – 330 MHz) NOTE: Allegro is not an accredited EMC laboratory. The information presented here is for reference only.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com FUNCTIONAL DESCRIPTION Overview The A81805 is a wide input voltage (3.5 to 36 V) synchronous PWM buck regulator that integrates low RDS(on) high-side and low-side N-channel MOSFETs. The A81805 employs peak cur- rent mode control to provide superior line and load regulation, cycle-by-cycle current limit, fast transient response, and simple internal compensation. The features of the A81805 include ultra- low IQ in LP mode, extremely low minimum on-time, maximized duty cycle for low dropout operation, and pre-bias startup capa- bility. Protection features of the A81805 include VIN undervoltage lockout, cycle-by-cycle overcurrent protection, BOOT over- voltage and undervoltage protection, hiccup mode short-circuit protection, output overvoltage protection, and thermal shutdown. In addition, the A81805 provides open circuit, adjacent pin short circuit, and pin-to-ground short-circuit protections. Enable A voltage on EN above the nominal 1.2 V threshold enables the A81805. The EN comparator has a typical hysteresis of 200 mV . Once enabled, if EN decreases below 1 V (typical), the A81805 enters the shutdown state, stops switching, and draws only 1 µA (typical) from VIN. Internal VCC Regulator VCC is used as the power supply for internal control circuitry and low-side MOSFET driver. The A81805 consists of two internal low dropout regulators, VIN LDO and VOUT LDO, to generate VCC voltage. VIN LDO is powered from the input voltage to generate 3.3 V for VCC supply during power-up and soft-start. VOUT LDO is powered through the VOUT pin to generate VCC once the converter output is in regulation. Switching Frequency The PWM switching frequency of the A81805 is adjustable from 400 kHz to 2.5 MHz by programming the internal clock frequency of the oscillator by connecting an RFSET resistor from the FSET pin to GND. The internal clock has an accuracy of ±10% over the operating temperature range. Figure 2 shows the relationship between the typical switching frequency and RFSET resistor.The A81805 will suspend operation if the FSET pin is shorted to GND or left open. For a required switching frequency (fSW), the RFSET resistor value can be calculated as follows: Equation 1: RFSET = 37037 fSW – 2.96 where fSW is in kHz and RFSET is in kΩ. 10 20 30 40 50 60 70 80 90 RFSET (k ) 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600Switching Frequency (kHz) Figure 2: Switching Frequency vs. RFSET While choosing the PWM switching frequency, the designer should be aware of the minimum controllable on-time, tON(MIN), of the A81805. If the required on-time of the system is less than the minimum controllable on-time, pulse skipping will occur and the output voltage will have increased ripple. The PWM switch- ing frequency should be calculated using Equation 2, where VOUT is the output voltage, tON(MIN) is the minimum controllable on- time of the device (see EC table), and VIN(MAX) is the maximum required operational input voltage (not the peak surge voltage). Equation 2: fSW = VOUT tON(MIN) × VIN(MAX)

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 500 10001 5002 0002 500 Switching Frequency (kHz) 40Input Voltage Range (V) Typical Operating Area VOUT = 3.3 V VOUT = 5 V Figure 3: VIN Range Limitation Based On Minimum On and Off Times Synchronization (SYNC) The Phase-Locked Loop (PLL) in the A81805 allows its internal oscillator to be synchronized to an external clock applied on the SYNC pin. If the SYNC pin is driven by an external clock, the A81805 will be forced to operate in PWM mode at the synchro- nized switching frequency and will not enter LP mode. The exter- nal clock must satisfy the pulse width, duty cycle, and rise/fall time requirements shown in the Electrical Characteristics table. If an external clock fSYNC is used for synchronization, the FSET pin must still have a resistor to GND, RFSET, based on Equation 1, to ensure proper slope compensation. The switching frequency, fSW, used to calculate RFSET, should be chosen such that pulse skipping will not occur at the maximum synchronized switching frequency (i.e., 1.5 × fSYNC < fSW in Equation 2). Frequency Dither Frequency dither helps to minimize peak emissions by spreading the emissions across a wide range of frequencies. The A81805 provides frequency dither by spreading the switching frequency over ±5% using a triangular modulated wave of 0.5% switching frequency. The A81805 is capable of adding dither to an external clock applied to the SYNC pin. This unique feature allows the minimiz- ing of EMI even when the device is using external clock. Table 1: PWM Frequency and Dithering SYNC SW Frequency Dither Frequency Range Dither Modulation Frequency Low fOSC ±0.05 × fOSC 0.005 × fOSC High fOSC fSYNC fSYNC ±0.05 × fOSC 0.005 × fOSC Ultra-Low Quiescent Current Low Power (LP) Mode When in Low Power (LP) Mode, the A81805 operates with ultra- low quiescent current (IQ). The A81805 is in continuous conduction PWM Mode until peak inductor current decreases to IPEAK(LP), 700 mA typ. When peak inductor current falls below IPEAK(LP), the regulation of the output voltage will be managed by the LP comparator, which will moni- tor the internal feedback node voltage. The reference for the LP comparator is calibrated approximately 0.5% above the PWM regulation point. The transition point from PWM to LP mode is defined by the input voltage, output voltage, and inductor value. The exact operation of A81805 in LP mode is described below. When voltage on the internal COMP node falls to the voltage cor- responding to the Ultra-Low IQ peak current threshold value, an internal clamp prevents the COMP voltage from falling further. This results in a momentary rise in the internal feedback volt- age beyond the LP comparator upper threshold which causes the LP comparator to trip. Once the LP comparator trips, the device enters a coast period during which converter switching is termi- nated and the associated control circuitry is also shut down. This ensures a very low quiescent current is drawn from the input. The coast period terminates once the internal feedback voltage falls below the LP comparator lower threshold. The converter will operate at the PWM switching frequency until the voltage at the internal feedback node rises again above the LP comparator threshold. The rate of rise of the output voltage is determined by the input voltage, output voltage, inductor value, output capaci- tance, and load. Due to the hysteretic nature of the LP control algorithm, higher output voltage ripple is expected. Typically, output voltage peak- to-peak ripple will be less than 50 mV . The thermal shutdown (TSD) circuit is disabled in LP mode to further reduce the ultra-low quiescent current, since power dis- sipation and self-heating in LP mode is very low.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Low Input Voltage Operation The A81805 is designed to operate at extremely wide duty cycles to minimize any reduction in output voltage during dropout conditions such as an automotive cold crank. When the A81805 senses the dropout condition, it reduces the switching frequency to extend the duty cycle and regulate the output voltage with a lower input voltage. Power MOSFETs The A81805 includes a 170 mΩ, high-side N-channel MOSFET and a 130 mΩ, low-side N-channel MOSFET to provide synchro- nous rectification. When the A81805 is disabled by pulling the EN input low or by a fault condition, its output stage is tri-stated by turning off both the upper and lower MOSFETs. BOOT Regulator The A81805 includes a BOOT regulator to supply the power for a high-side MOSFET gate driver. The voltage across the BOOT capacitor is typically 3.2 V . Soft-Start (Startup) and Inrush Current Control The A81805 provides an internal fixed soft-start function to limit inrush current at startup. When the part is enabled, the high-side and low-side MOSFETs will begin switching after tdSS. The output voltage is ramped to the VOUT target level of 3.3 V for the A81805 or 5 V for the A81805-1 during the tSS period. During startup, PWM switching frequency is reduced to 25% of fSW while VOUT is below 25% of the regulation voltage. When VOUT is between 25% to 50% level, the switching frequency is set to 50% of fSW. When VOUT is above 50% of the regula- tion voltage, the switching frequency is no longer reduced. The reduced switching frequency is necessary to help improve output regulation and stability when VOUT is very low. During low VOUT, the PWM control loop requires on-time near the minimum controllable on-time and very low duty cycles that are not pos- sible at the nominal switching frequency. After the soft-start period, tSS, the error amplifier will switch over and begin regulating the output voltage to desired level. If the A81805 is disabled or a fault occurs, the internal fault latch is set and the soft-start circuit is reset, forcing the converter to go through another soft-start. Pre-Biased Startup If the output of the buck regulator is pre-biased at a certain output voltage level upon startup, the A81805 will modify the normal startup routine to prevent discharging the output capacitors. If the output is pre-biased, the voltage at the internal FB node will be non-zero. The device will not start switching until the internal reference to the error amplifier exceeds the FB voltage. Then the error amplifier becomes active and normal startup sequence is followed. PGOOD Output The A81805 provides a Power Good (PGOOD) status signal to indicate if the output voltage is within the regulation limits. Since the PGOOD output is an open-drain output, an external pull-up resistor must be used as shown in the applications schematic. PGOOD transitions high when the output voltage, sensed at the internal FB node is within regulation. During startup, PGOOD signal exhibits an additional delay of tdPG(SU) after the internal FB node voltage reaches the reference voltage, indicating VOUT is in regulation. This delay helps to filter out any glitches on the internal FB node voltage. The PGOOD output is pulled low if either an output undervoltage or overvoltage condition occurs or the A81805 junction tempera- ture exceeds thermal shutdown threshold (TSD). The PGOOD overvoltage and undervoltage comparators incorporate a small amount of hysteresis to prevent chattering and deglitch filtering (tdPG(UV), tdPG(OV)) to eliminate false triggering. Current Sense Amplifier The A81805 incorporates a high-bandwidth current sense ampli- fier to monitor the current through the high-side MOSFET. This current signal is used to regulate the peak current when the high-side MOSFET is turned on. The current signal is also used by the protection circuitry for the cycle-by-cycle current limit and hiccup mode short-circuit protection.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Pulse Width Modulation (PWM) The A81805 employs fixed-frequency, peak current-mode con- trol to provide excellent load and line regulation, fast transient response, and simple compensation. A high-speed comparator and control logic are included in the A81805. The inverting input of the PWM comparator is connected to the output of the error amplifier. The non-inverting input is connected to the sum of the current sense signal, the slope compensation signal, and a DC PWM Ramp offset voltage (Ramp Offset). At the beginning of each PWM cycle, the CLK signal sets the PWM flip-flop, the low-side MOSFET is turned off, the high-side MOSFET is turned on, and the inductor current increases. When the voltage at the non-inverting input of the PWM comparator rises above the error amplifier output COMP, the PWM flip-flop is reset, the high-side MOSFET is turned off, the low-side MOS- FET is turned on, and the inductor current decreases. Since the PWM flip-flop is reset, the dominant error amplifier may override the CLK signal in certain situations. Internal Loop Compensation The A81805 has internal control loop compensation that ensures adequate stability margins and maintains a high loop gain at DC to achieve excellent output voltage regulation and to obtain a high loop bandwidth for superior transient response. Slope Compensation The A81805 incorporates internal slope compensation that ensures stable operation at PWM duty cycles above 50% for a wide range of input/output voltages and switching frequencies. As shown in the functional block diagram, the slope compensa- tion signal is added to the sum of the current sense and PWM Ramp Offset. The relationship between slope compensation and switching frequency is given by Equation 3. Equation 3: SE = 1.4 × fSW – 0.205 where fSW is the switching frequency in MHz and SE is slope compensation in A/μs. PROTECTION FUNCTIONS AND FAULT HANDLING The A81805 was designed to satisfy the most demanding automo- tive and non-automotive applications. The following sections contain a description of each protection feature as well as Table 2 which summarizes the protections and their operation. Undervoltage Lockout (UVLO) The undervoltage lockout (UVLO) comparator in the A81805 monitors the voltage at the VIN pin and keeps the regulator dis- abled if the voltage is below the start threshold (VINUV(ON), VIN rising) or the stop threshold (VINUV(OFF), VIN falling). The UVLO comparator incorporates some hysteresis (VINUV(HYS)) to help prevent on-off cycling of the regulator due to resistive or induc- tive drops in the VIN path during heavy loading or during startup. Pulse-by-Pulse Peak Current Protection (PCP) The A81805 monitors the current in the high-side MOSFET. When the peak MOSFET current exceeds the pulse-by-pulse overcurrent limit ILIM(HS), the high-side MOSFET is turned off and the low-side MOSFET is turned on until the start of the next clock pulse from the oscillator. The device includes leading-edge blanking to prevent false triggering of pulse-by-pulse current protection when the high-side MOSFET is turned on. Overcurrent Protection (OCP) and Hiccup Mode An OCP counter and hiccup mode circuit protect the buck regula- tor when the output of the regulator is shorted to ground or when the load is too high. The device asserts the fault state by pulling PGOOD low and stopping switching after HIC_OC switching cycles for an overcurrent condition or HIC_SW,GND cycles if SW is shorted to ground. While the overcurrent protection is active, the device will periodically retry a soft-start every tHIC to check if the short was removed. During the soft-start ramp the OCP hiccup counter is disabled. The A81805 resumes normal operation when the short is removed. A typical hiccup operation during short circuit is shown in Figure 4. Figure 4: Hiccup Operation During Short Circuit

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Boot Capacitor Protection The A81805 monitors the voltage across the BOOT capacitor to detect open and short conditions. If an open BOOT capacitor is detected, the regulator pulls PGOOD low and enters hiccup mode, trying to start again with period tHIC. When the open fault is removed, the device exits hiccup mode and returns to normal operation. If the BOOT capacitor is shorted before startup is complete, the regulator will not switch or regulate until the short is removed. If the BOOT capacitor is shorted after startup is com- plete, the regulator shuts down and must be powercycled after the short is removed to resume normal operation. In both cases, when the BOOT capacitor is shorted, PGOOD is tri-stated and is not asserted low. Overvoltage Protection (OVP) The A81805 consists of an always-on overvoltage protection cir- cuit that monitors the voltage on the VOUT pin. During an over- voltage event, the controller tries to reduce the output overvoltage by terminating the high-side MOSFET switching and pulsing the low-side MOSFET for the minimum off-time (tOFFmin) until VOUT returns to regulation. Upon an OVP event, the A81805 waits for the PGOOD overvoltage delay, tdPG(OV), before pulling PGOOD low. If the overvoltage fault is not cleared after tdPG(OV), PGOOD is pulled low and the device continuously attempts to reduce the output overvoltage. SW Pin Protection The A81805 protects itself upon a SW pin short to ground. If the SW pin is shorted to ground, there will be a very high current in the high-side MOSFET when it is turned on. The A81805 incorporates internal secondary current protection to detect this unusually high current and turns off the high-side MOSFET if the high current persists for more than two consecutive switching cycles. After turn- ing off the high-side MOSFET, the device enables the hiccup latch and attempts to restart after hiccup latch is cleared. If the short to ground is removed, the regulator will automatically recover; other- wise, the device continues hiccupping. Pin-to-Ground and Pin-to-Pin Short Protections The A81805 is designed to satisfy the most demanding automo- tive applications. For example, the device has been carefully designed to withstand a short-circuit to ground at each pin with- out causing any damage to the IC. In addition, the device’s pinout is optimized to provide protection against pin-to-pin adjacent short circuits. For example, logic pins and high-voltage pins are separated as much as possible. Table 2: Summary of A81805 Fault Modes and Operation Fault Mode Hiccup High-Side MOSFET Low-Side MOSFET PGOOD Reset Condition VIN Undervoltage No Off Off Low VIN above UVLO Output Short / Overcurrent Yes Off Turned On if BOOT Voltage is too low Low Short / Overcurrent removed SW Short-to-GND Yes Off Off Low Short removed BOOT Cap Open Yes Off Off Low BOOT capacitor circuit closed BOOT Cap Shorted – Before Startup Complete No Off Off Hi-Z BOOT capacitor short removed BOOT Cap Shorted – After Startup Complete No Off Off Hi-Z BOOT capacitor short removed and power cycle Output Overvoltage No Off Pulsed with Minimum TOFF Low VOUT within operative range Output Undervoltage No Normal Behavior Low VOUT within operative range FSET Short-to-GND or Open No Off Off Low FSET shorted removed Thermal Shutdown No Off Off Low Part cools down

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Thermal Shutdown (TSD) The A81805 monitors internal junction temperature and stops switching if the junction temperature exceeds the Thermal Shut- down Threshold, TTSD. To prepare for a restart, the internal soft- start voltage and the error amplifier output (COMP) are pulled low. Thermal shutdown is a non-latched fault, so the device automatically recovers. In LP mode, self-heating is minimal due to the low input current and light loading of the converter. To further reduce the quiescent current, thermal shutdown circuitry is disabled in LP mode.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com APPLICATIONS INFORMATION Component Selection Guidelines Recommended values for the output inductor, input capacitors, and output capacitors are shown in Table 3. These values are well suited for most applications. The following guidance should be followed if the application requires deviating from these recom- mended values. Output Inductor (LO) The A81805 incorporates a peak current-mode control tech- nique for closed-loop regulation of the output voltage. Without adequate slope compensation, a peak current-mode-controlled regulator may become unstable when duty cycle is near or above 50%. To stabilize the regulator over the complete range of its operating duty cycle, the A81805 employs an internal slope compensation (SE) proportional to the switching frequency as described in the Slope Compensation section. Many factors determine the selection of output inductor, such as switching frequency, output/input voltage ratio, transient response, transi- tion to LP mode, and desired ripple current. A larger value induc- tor will result in less ripple current, which also results in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. A good rule of thumb for determining the output inductor is to allow the peak-to-peak ripple current in the inductor to be approximately 30% of the maximum output current (IOUT(MAX)). The inductance value can be calculated from the following equa- tion: Equation 4: LO = VOUT fSW × ΔILO VOUT VIN × (1 – ) where ΔILO is the peak-to-peak inductor ripple current, which is 0.3 × IOUT(MAX). A second constraint on inductor value arises from the loop stabil- ity at duty cycles greater than 50%. Although slope compensa- tion is primarily required to avoid subharmonic oscillations, the inductor value calculated from Equation 5 can critically damp the pole pair at half the switching frequency. Equation 5: LO ≥ VOUT SE VOUT VIN(MIN) × (1 – 0.18 × ) where LO is output inductance in μH and SE is external slope compensation. To avoid dropout, VIN(MIN) must be approximately 1 to 1.5 V above VOUT. Choose an output inductor such that its inductance is greater than the maximum of inductance values calculated in Equation 4 and Equation 5. The saturation current of the inductor should be higher than the peak current capability of the A81805. Ideally, for output short- circuit conditions, the inductor should not saturate given the peak current limit (ILIM(HS)). The output inductor should be sized to not saturate with the peak operating current according to the fol- lowing equation. Equation 6: ISAT_LO > ILIM(HS)(MAX) – ( SE × tON(MIN) 1.15 ) where tON(MIN) is the minimum on-time provided in the Electrical Characteristics table. The typical DC output current capability of the regulator at any given duty cycle (D) is: Equation 7: IOUT(TYP) > ILIM(HS)(TYP) – SE × D fSW – VOUT × (1 – D) 2 × fSW × LO After an inductor is chosen, it should be tested during output short-circuit conditions. The inductor current should be moni- tored using a current probe. A good design should ensure neither the inductor nor the regulator are damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. Output Capacitors (CO) A switching regulator’s output capacitor filters the output voltage to provide an acceptable level of ripple and stores energy to help maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. The output voltage ripple (ΔVOUT) is a function of the output capacitor parameters: CO, ESRCO, and ESLCO. Equation 8: ΔVOUT = ΔILO × ESRCO + VIN – VOUT LO × ESLCO + ΔILO 8 × fSW × CO The type of output capacitors determines which terms of Equation 10 are dominant. For ceramic output capacitors, ESRCO and ESLCO are

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com virtually zero, so the output voltage ripple will be dominated by the third term of Equation 8. The value of CO can be calculated as: Equation 9: CO ≥ ΔILO 8 × fSW × ΔVOUT V oltage ripple of a regulator using ceramic output capacitors can be reduced by increasing the total capacitance, reducing the inductor current ripple or increasing the switching frequency. For electrolytic output capacitors, the value of capacitance will be relatively high, so the third term in Equation 8 will be very small and the output voltage ripple will be determined primarily by the first two terms: Equation 10: ΔVOUT = ΔILO × ESRCO + VIN – VOUT LO × ESLCO V oltage ripple of a regulator using electrolytic output capacitors can be reduced by decreasing the equivalent ESRCO and ESLCO by using a high-quality capacitor, adding more capacitors in par- allel, or reducing the inductor current ripple. As the ESR of some electrolytic capacitors can be quite high, Allegro recommends choosing a quality capacitor for which the ESR or the total impedance is clearly documented in the capaci- tor datasheet. Also, the ESR of electrolytic capacitors usually increases significantly at cold ambient temperatures, as much as 10 times, which increases the output voltage ripple and may affect the stability of the converter. The transient response of the regulator depends on the quantity and type of output capacitors. In general, minimizing the ESR of the output capacitance will result in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. At the instant of a fast load transient (high diO/dt), the change in the output voltage, using electrolytic output capacitors, is: Equation 11: ΔVOUT = ΔILO × ESRCO + diO dt × ESLCO When ceramic capacitors are used on the output, the output voltage deviation during load transients depends on the bulk output capacitance along with various other factors. To calculate the bulk ceramic capacitance required, the entire load transient duration can be divided into two stages: large signal and small signal. During large signal load transients, immediately after the transient event, the output voltage deviates from the nominal value due to large mismatch in the load current requirement and the inductor current. The output voltage deviation during this interval is maximum and depends on output inductor, bulk output capacitance, and closed-loop crossover frequency. For designs with higher crossover frequency, the controller typically saturates the duty cycle, i.e., either minimum or maximum. For a chosen output inductor and crossover frequency values, the output volt- age deviation can be minimized by increasing the output bulk capacitance. In the case of a buck converter, operating with a low duty cycle, the step-down load transient is more severe and hence the output capacitance should be determined for this scenario. The bulk ceramic output capacitance required is given by: Equation 12: CO(BULK) ≥ 2 × VOUT × ΔVOUT(SPEC) ΔIO × LO where ΔIO is the magnitude of the change in the load current, ΔVOUT(SPEC) is the maximum allowed output voltage deviation during load transient event. Gradually, as the mismatch between the load current and the inductor current becomes small, the output voltage deviation also reduces, resembling a small signal transient event. Eventually, during small signal transient interval, the error amplifier brings the output voltage back to its nominal value. The speed with which the error amplifier brings the output voltage back into regulation depends mainly on the loop cross- over frequency. A higher crossover frequency usually results in a shorter time to return to the nominal set voltage. Output Voltage Ripple – Ultra-Low IQ LP Mode After choosing output capacitor(s), it is important to calculate the output voltage ripple (VPP(LP)) during ultra-low IQ LP mode. With ceramic output capacitors, the output voltage ripple in PWM mode is usually negligible, but this is not the case during LP mode. In LP mode, the peak inductor current during on-time of the high- side switch is limited to IPEAK(LP). Also, in LP mode, the low-side switch is constantly turned off thereby forcing the regulator to operate in Discontinuous Conduction Mode (DCM) in order to reduce switching losses. The LP comparator monitors the output voltage on the internal feedback node and allows the regulator to switch until the internal feedback voltage is greater than 0.5% of its nominal value (0.8 V). When internal feedback voltage is greater than 0.804 V , the A81805 coasts by terminating the switching pulses. During coasting, the device shuts down most of its internal con- trol circuitry to ensure very low quiescent current is drawn from the input. The number of switching pulses required in LP mode

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com to coast the device depend on various factors including input voltage, output voltage, load current, output inductor, and output capacitor. If A81805 starts coasting after a single switching pulse, then the output voltage ripple would be dictated by this single pulse. The peak inductor current without slope compensation (IPEAK_L) is given by: Equation 13: IPEAK_L ≅ VIN ×L × fSW (VIN – VOUT) × VOUT where IPEAK_LP is the peak inductor current, specified in the Electrical Characteristics table, at which device enters into LP mode. Referring to Figure 1, on-time and off-time calculations are given as: Equation 14: tON = VIN – VOUT – IPEAK_L × (RDS(ON)HS + LO(DCR)) IPEAK_L × LO Equation 15: tOFF = VOUT IPEAK_L × LO where RDS(ON)HS is the on-resistance of internal high-side MOS- FET and LO(DCR) is the DC resistance of the output inductor, LO. Figure 5: Output Voltage Ripple in LP Mode During on-time interval, the length of the time for the inductor current to rise from 0 A to IOUT is: Equation 16: t1 = VIN – VOUT – IPEAK_L × (RDS(ON)HS + LO(DCR)) IOUT × LO During off-time interval, the length of the time for the inductor current to fall from IOUT to 0 A is: Equation 17: t2 = VOUT IOUT × LO Given the peak inductor current (IPEAK_L) and the rise and fall times (tON and tOFF) for the inductor current, the output voltage ripple for a single switching pulse can be calculated as follows: Equation 18: VPP(LP) = 2 × COUT IPEAK_L × LOUT × (tON + tOFF – t1 – t2) Input Capacitor Selection (CIN) Three factors should be considered when choosing the input capacitors. First, the capacitors must be chosen to support the maximum expected input surge voltage with adequate design margin. Second, the capacitor RMS current rating must be higher than the expected RMS input current to the regulator. Third, the capacitors must have enough capacitance and a low enough ESR to limit the input voltage dV/dt to much less than the hysteresis of the UVLO circuitry (250 mV nominal) at maximum loading and minimum input voltage. The input capacitors must deliver an RMS current (IRMS) given by: Equation 19: IRMS = IOUT × √D × (1 – D) where D is the duty cycle Equation 20: D ≈ VIN VOUT Figure 5 shows the normalized input capacitor RMS current versus duty cycle. To use this graph, simply find the operational duty cycle (D) on the x-axis and determine the input/output cur- rent multiplier on the y-axis. For example, at a 20% duty cycle, the input/output current multiplier is 0.40. Therefore, if the regulator is delivering 1.0 A of steady-state load current, the input capacitor(s) must support 0.40 × 1.0 A or 0.4 A RMS.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 02 04 06 08 01 00 Duty Cycle (%) 0.1 0.2 0.3 0.4 0.5 IRMS / IOUT Figure 6: Normalized Input Capacitor Ripple vs. Duty Cycle The input capacitor(s) must limit the voltage deviations at the VIN pin to significantly less than the device UVLO hysteresis during maximum load and minimum input voltage condition. The following equation allows to calculate the minimum input capacitance required: Equation 21: CIN ≥ 0.85 × fSW × ΔVIN(MIN) IOUT × D × (1 – D) where ΔVIN(MIN) is chosen to be much less than the hysteresis of the VIN UVLO comparator (ΔVIN(MIN) ≤ 150 mV is recom- mended), and fSW is the nominal PWM frequency. The D × (1–D) term in Equation 21 has an absolute maximum value of 0.25 at 50% duty cycle. A good design should consider the DC bias effect on a ceramic capacitor: as the applied voltage approaches the rated value, the capacitance value decreases. This effect is very pronounced with the Y5V and Z5U temperature characteristic devices (as much as 90% reduction), so these types should be avoided. The X5R, X7R, and X8R type capacitors should be the primary choices due to their stability versus both DC bias and temperature. A ceramic capacitor of 47 nF along with an aluminum electrolytic capacitor is recommended (≥47 μF). The electrolytic capacitor is used to meet load-transient response requirements and to avoid input voltage oscillation due to the negative input impedance of the DC-DC regulator, while the ceramic capacitor is used to bypass high di/dt input ripple current. Use of EN Pin for Input Undervoltage Protection EN is input to a hysteretic comparator with an accurate 1.2 V (typical) threshold. A voltage on EN above the nominal 1.2 V threshold enables the A81805. Once enabled, the EN comparator has a typical hysteresis of 200 mV and if EN is lowered below 1.0 V (typical), the A81805 will enter the shutdown state. This pin can be used to shut the converter down if input voltage falls below desired voltage, as shown in Figure 7. VOUTVIN FSET VCC PGND VIN EN VOUT SW BOOT SYNC PGOOD PAD A81805 LOUT COUTCBOOTCIN RPG CVCC REN1 REN2 Figure 7: Application Circuit for Setting Input Undervoltage A voltage divider circuit with two resistors can be used to adjust the enable voltage threshold or undervoltage lockout thresh- old. Select a convenient value for REN2 and use Equation 22 to calculate REN1 for a rising enable threshold level using the typical value for VEN(HI) of 1.2 V: Equation 22: REN1 = VINTH(RISE) – 1.2 V IVEN + 1.2 V REN2 where VINTH(RISE) is the desired input voltage threshold to enable the device, and IVEN is the typical enable pin input current. Use Equation 23 to estimate the falling input voltage threshold level once both resistors are known, using the typical value for VEN(HI) of 1.2 V and typical value of VEN(HYS) of 200 mV . Equation 23: VINTH(FALL) = VENTH(FALL) × REN2 REN1 + REN2 + (IVEN × REN1) where VENTH(FALL) =VEN(HI) – VEN(HYS), typically 1 V .

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com CIN CVCC CBOOT LOUT RPG FSET VCC PGND VIN EN VOUT SW BOOT SYNC PGOOD PAD A81805 COUT VOUTVIN Figure 8: Typical Applications Schematic Table 3: Recommended External Filter Component Values Device VOUT fOSC LO CO CIN(MIN) A81805 3.3 V 2.15 MHz 2.2 µH 2 × 10 µF 1 × 4.7 µF A81805 3.3 V 400 kHz 8.2 µH 3 × 22 µF 3 × 4.7 µF A81805-1 5 V 2.15 MHz 2.2 µH 2 × 10 µF 1 × 4.7 µF A81805-1 5 V 400 kHz 12 µH 1 × 47 µF 3 × 4.7 µF Components were chosen to maintain LP ripple voltage and mini- mize voltage droop during LP to PWM changeover. APPLICATION SCHEMATIC AND RECOMMENDED EXTERNAL COMPONENTS

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com PCB LAYOUT GUIDELINES The A81805 is designed to minimize electromagnetic interference (EMI) when proper PCB layout techniques are adopted. A good PCB layout is also critical for the A81805 to provide clean and stable output voltages. Design guidelines for EMI/EMC-aware PCB layout and minimized thermal impedance are presented below. Figure 9 shows a typical application schematic of a syn- chronous buck regulator IC with critical power paths/loops. Place the ceramic input capacitors as close as possible to the VIN pin and PGND pins to minimize the loop area and keep the traces from the VIN pin to these capacitors as short and wide as possible to minimize the impedance. This critical loop is shown as trace 1 in Figure 9. The bulk/electrolytic input capacitor can be located further away from VIN pin. The input capacitors and A81805 IC should be on the same side of the board with traces on the same layer. The loop from the input supply and capacitors, through the high- side MOSFET, into the output capacitor via the output inductor, and back to ground should be minimized with relatively wide traces. When the high-side MOSFET is off, free-wheeling current flows from ground through the synchronous low-side MOSFET, as path 2 shown in Figure 9. Place the output capacitors relatively close to the output induc- tor (LO) and the A81805. Ideally, the output capacitors, output inductor, and the A81805 should be on the same layer. Connect the output inductor and the output capacitors with a fairly wide trace. The output capacitors must use a ground plane to make a very low-inductance connection to the PCB GND. These critical connections are shown as trace 3 in Figure 9. Place the output inductor (LO) as close as possible to the SW pin with short and wide traces. This critical trace is shown as trace 4 in Figure 9. The voltage at the SW node transitions from approxi- mately 0 V to VIN with a high dv/dt rate. This node is the root cause of many EMI and other noise issues. It is suggested to min- imize the SW copper area to minimize the coupling capacitance between SW node and other noise-sensitive nodes; however, the SW node area cannot be too small because it must conduct high current. A ground copper area can be placed underneath the SW node to provide additional shielding. If an RFSET resistor is used, place it as close as possible to the FSET pin. The output voltage sense trace should connect to VOUT as close as possible to the load to ensure optimal load regulation. Place the bootstrap capacitor (CBOOT) near the BOOT pin and keep the routing from this capacitor to the SW polygon as short as possible. This critical trace is shown as trace 5 in Figure 9. Allegro recommends a 4-layer PCB as shown in Figure 9. Heavier copper layers, reduced material between layers, and a good amount of thermal vias are the keys to improved thermal performance. Use the top layer for routing high-current traces, layer 2 for a solid PGND plane, layer 3 for most other routing, and the bottom layer for solid PGND plane or optionally other components without low-impedance traces constraints—the PGOOD pull-up resistor could be on the bottom layer if desired. Routing on the bottom and top planes interrupts the flow of heat energy from the converter and inductor to the ambient and results in increased board thermal impedance. To the extent possible without compromising the design electrically, routing should be located on layer 3 to optimize the board’s ability to dissipate heat. If a two-layer-only PCB is mandatory, place all the components on the top layer and limit the routing only to the top layer. Use the bottom layer as PGND plane. When connecting the input and output ceramic capacitors, use multiple vias to the PGND planes and place the vias as close as possible to the pads of the components. Do not use thermal reliefs around the pads for the input and output ceramic capacitors as they increase the impedance of the connections. To minimize thermal resistance (RθJA), extend the PGND plane on the top layer as much as possible and use plenty of thermal vias to connect them to the PGND plane in the bottom layer. To minimize PCB losses and improve system efficiency, the power traces should be as wide as possible.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com CO LO VOUT BOOT VOUT SWSW FSET VCC VIN Buck Switcher PWM Controller A81805 CIN PGOOD SYNC EN CBOOT PGND Figure 9: PCB Layout Critical Paths Top Layer Middle Layer 1 Middle Layer 2 Bottom Layer Figure 10: PCB Reference Design

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com POWER DISSIPATION AND THERMAL CALCULATIONS The total power dissipated in the A81805 is the sum of the power dissipated from the VIN supply current (PIN), the power dissipated due to the switching of the high-side power MOSFET (PSWH), the power dissipated due to the conduction of RMS current in the high-side MOSFET (PCH) and low-side MOSFET (PCL), power dissipated due to the low-side MOSFET body diode conduction during the non-overlap time (PNO), and the power dissipated by both high-side and low-side gate drivers (PDRIVER). The power dissipated from the VIN supply current can be calcu- lated using Equation 24: Equation 24: PIN = VIN × IIN(PWM) where VIN is the input voltage, IIN(PWM) is the input quiescent current drawn by the A81805 in PWM mode (see EC table), QGH and QGL are the internal high-side and low-side MOSFET gate charges, and fSW is the PWM switching frequency. The power dissipated by the high-side MOSFET during PWM switching can be calculated using Equation 25: Equation 25: PSWH = VIN × IOUT × (tr + tf) × fSW where VIN is the input voltage, IOUT is the regulator output cur- rent, fSW is the PWM switching frequency, tr and tf are the rise and fall times measured at the switch node. The exact rise and fall times at the SW node will depend on the external components and PCB layout, so each design should be measured at full load. The power dissipated in the high-side MOSFET while it is con- ducting can be calculated using Equation 26: Equation 26: PCH = IRMS(H) × RDS(ON)H = VOUT VIN × (IOUT + ΔILO 12 ) × RDS(ON)H Similarly, the conduction losses dissipated in the low-side MOS- FET while it is conducting can be calculated by Equation 27: Equation 27: PCL = IRMS(L) × RDS(ON)L = (1 – VOUT VIN ) × (IOUT + ΔILO 12 ) × RDS(ON)L where IOUT is the regulator output current, ΔILO is the peak-to- peak inductor ripple current, RDS(ON)H is the on-resistance of the high-side MOSFET, RDS(ON)L is the on-resistance of the low-side MOSFET. The power dissipated in the low-side MOSFET body diode dur- ing the non-overlap time can be calculated using Equation 28: Equation 28: PNO = VSD × IOUT × 2 × tNO × fSW where VSD is the source-to-drain voltage of the low-side MOS- FET (typically 0.60 V), and tNO is the non-overlap time. The power dissipated in the internal gate drivers can be calculated using Equation 29: Equation 29: PDRIVER = (QGH + QGL) × VOUT × fSW where VGS is the gate drive voltage. Finally, the total power dissipated in the A81805 is given by Equation 30: Equation 30: PTOTAL = PIN + PSW + PCH + PCL + PNO + PDRIVER The average junction temperature (TJ) can be calculated as follows. Equation 31: TJ = PTOTAL × RθJA + TA where PTOTAL is the total power dissipated from Equation 30, RθJA is the junction-to-ambient thermal resistance (see Thermal Characteristics), and TA is the ambient temperature. RθJA includes the thermal impedance from junction to case, RθJC, and the thermal impedance from case to ambient, RθCA. RθCA is generally determined by the amount of copper that is used under- neath and around the device on the printed circuit board. See PCB Layout Guidelines section for more details on optimizing the thermal impedance of the board. The maximum allowed power dissipation depends on how effi- ciently heat can be transferred from the junction to the ambient air, i.e., minimizing the RθJA. As with any regulator, there are limits to the amount of heat that can be dissipated before risking thermal shutdown. There are tradeoffs between ambient operat- ing temperature, input voltage, output voltage, output current, switching frequency, PCB thermal resistance, airflow, and other nearby heat sources. Even a small amount of airflow can reduce the junction temperature considerably.

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com INPUT/OUTPUT STRUCTURES VDD 7 V PINPIN 10 kΩ VDD PIN 7 V PINPIN 4 kΩ 2 kΩ PIN 40 V HVRING 40 V PIN 5.5 V 20 kΩ HVRING PIN 40 V HVRING 40 V PIN HVRING PIN BOOT 7 V SW BOOT SW AGND PGNDAGND PGNDGND PGND VOUTVOUT 20 V VOUT SW VINHVRING SW VINHVRING PIN 7 V PIN 40 V HVRING 40 V PIN HVRING PIN VCC VOUT GND, PGNDBOOT SYNCIN FSET ENVIN PGOODSW

40 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current A81805 and A81805-1 Allegro MicroSystems Manchester, NH 03103-3353 U.S.A. www.allegromicro.com PACKAGE OUTLINE DRAWING Figure 11: 20-Pin 4 mm × 4 mm QFN with exposed thermal pad and wettable flank (suffix ES) For Reference Only –N ot for Tooling Use (Reference Allegro DWG-0000222 Rev. 4 or JEDEC MO-220WGGD) Dimensions in millimeters NOT TO SCALE Exact case and lead conﬁguration at supplier discretion within limits shown 0.95 C SEATING PLANE C0.08 21× A B C D D C

4.00 BSC

2.45 ±0.10 2.45 ±0.10 4.10 0.30 0.50 4.100.75 ±0.05

0.50 BSC

0.40 ±0.10 0.25 2.60 2.60 B PCB Layout Reference View Terminal #1 mark area. Exposed thermal pad (reference only, terminal #1 identiﬁer appearance at supplier discretion). Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5). Coplanarity includes exposed thermal pad and terminals.

0.05 REF

+0.03 –0.02 0.40 ±0.10 0.08 REF 0.203 REF Detail A DETAIL A 0.20 0.25 0.10 Standard Branding Reference View Lines 1, 2, 3 = 6 characters Line 1: Part Number Line 2: 4 digit Date Code Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number Pin 1 Dot top left Center align XXXX Date Code Lot Number E Branding scale and appearance at supplier discretion.E C0.15 2× C0.15 2× 0.02 +0.05 –0.07 PCB METAL KEEPOUT OR SOLDERMASK COVER

4 PLACES

Revision History

– February 4, 2022 Initial release

1 February 11, 2022

Updated Features and Benefits (page 1), Terminal Diagram (page 4), VOUT Voltage Accuracy test conditions (page 6), PWM Frequency Dither Range test conditions (page 6), SYNC Voltage Thresholds footnote references (page 7), TSD Hysteresis symbol (page 8); added Startup and Shutdown plots (page 11), Line Regulation plots (page 12); updated EMI/EMC Performance Characteristics plots (page 13), Figure 3 (page 15), Boot Capacitor Protection section (page 18), Table 2 (page 18), Output Inductor section (page 20), Equations 13 and 14 (page 22), Equation 23 (page 23), Power Dissipation section (page 29), and Input/Output Structures (page 28). Copyright 2022, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents.

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0 V, 2.5 A, Synchronous Buck Regulator with Low EMI and 6 µA Quiescent Current February 11, 2022

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