A6841 ALLEGRO
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26185.114B Package LW 18-pin Wide Body SOIC A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers The merging of low-power CMOS logic and bipolar output power drivers permit the A6841 integrated circuits to be used in a wide variety of peripheral power driver applications. Each device has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The 500 mA NPN Darlington outputs, with integral transient-suppression diodes, are suitable for use with relays, solenoids, and other inductive loads. All package variations of the A6841 offer premium performance with a minimum output-breakdown voltage rating of 50 V (35 V sustaining). All drivers can be operated with a split supply where the negative sup- ply is up to –20 V . The CMOS inputs are compatible with standard CMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, drivers can be cascaded for interface appli- cations requiring additional drive lines. The A6841SA devices are furnished in a standard 18-pin plastic DIP. The A6841SLW device is available in an 18-lead SOIC package. A 20-pin SOIC version, A6841SLW-20 has improved thermal characteristics. The SOIC drivers are also available for operation to a temperature of –40°C (part number suffi x ELW). These devices are lead (Pb) free, with 100% matte tin plated leadframes. 3.3 V to 5 V logic supply range Power on reset (POR) To 10 MHz data input rate CMOS, TTL compatible inputs –40°C operation available Low-power CMOS logic and latches Use the following complete part numbers when ordering: AB SO LUTE MAX I MUM RAT INGS Part Number Package Ambient A6841SA-T 18-pin DIP –20ºC to +85ºC A6841SLW-T 18-pin wide body SOIC –20ºC to +85ºC A6841SLW-20-T 20-pin wide body SOIC (enhanced thermals) –20ºC to +85ºC A6841ELW-T 18-pin wide body SOIC –40ºC to +85ºC A6841ELW-20-T 20-pin wide body SOIC (enhanced thermals) –40ºC to +85ºC Output V oltage Continuous Output Current (each output), IOUT ... 500 mA Package Power Dissipation, PD, see chart, page 6 Operating Temperature Range Ambient Temperature, T Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges.
FEATURES
Relays Solenoids Inductive loads
APPLICATIONS
Schmitt trigger inputs for improved noise immunity High-voltage current-sink outputs Internal pull-up/pull down resistors Output transient-protection diodes Single or split supply operation Package LW-20 20-pin Wide Body SOIC
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B Functional Block Diagram MOS BI POLAR LOGIC GROUND STRO BE OUTPUT E NABLE (AC TIVE LOW) SERI A L DATA OUT CLOCK SERI A L DATA IN S E R IAL-P AR ALLE L S HIFT R E G IS TE R LATCHE S V DD LOGIC SU PPL Y OUT 1 OUT 2 OUT 3 OUT 6 OUT 7 OUT 8OUT 4 OUT 5 VEE o r POWER GROUND VEE o r POWER GROUND SU B K Typical Input Circuits Typical Output Driver CLOCK SERIAL DATA IN VDD STROBE OUTPUT ENABLE VDD OUT SUB K VEE
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, Vee = 0 V, logic supply operating voltage Vdd = 3.0 V to 5.5 V Characteristic Symbol Test Conditions Vdd = 3.3 V V dd = 5 V Output Leakage Current I CEX VOUT = 50 V – – 10 – – 10 μA Output Sustaining Voltage V CE(SUS) IOUT = 350 mA, L = 3 mH 35 – – 35 – – V Collector–Emitter Saturation Voltage VCE(SAT) IOUT = 100 mA – – 1.1 – – 1.1 V IOUT = 200 mA – – 1.3 – – 1.3 V IOUT = 350 mA – – 1.6 – – 1.6 V Input Voltage VIN(1) 2.2 – – 3.3 – – V Input Resistance R IN 50 – – 50 – – k Ω Serial Data Output Voltage VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V Maximum Clock Frequency2 fc 10 – – 10 – – MHz Logic Supply Current IDD(1) One output on, OE = L, ST = H – – 2.0 – – 2.0 mA IDD(0) All outputs off, OE = H, ST = H, P1 through P8 = L – – 100 – – 100 μA Clamp Diode Leakage Current I r Vr = 50 V – – 50 – – 50 μA Clamp Diode Forward Voltage V f If = 350 mA – – 2 – – 2 V Output Enable-to-Output Delay tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Strobe-to-Output Delay tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Fall Time t f VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Rise Time t r VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Clock-to-Serial Data Out Delay t p(CH-SQX) IOUT = ±200 μA – 50 – – 50 – ns 1Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin. 2Operation at a clock frequency greater than the specifi ed minimum value is possible but not warranteed. Serial Shift Register Contents Serial Latch Contents Output Output Contents Data Clock Data Strobe Enable R1 R2 R3 ... R 8R 8 XXX. . . X X X L R1 R2 ... R 7LL R1 R2 R3 ... R 8 XXX. . . X L P HHH H H R1 R2 ... R 7HH H... Truth Table L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State OE = Output Enable ST = Strobe
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B Timing Requirements and Specifi cations (Logic Levels are VDD and Ground) CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE OUT N 50%SERIAL DATA OUT DATA DATA 10% 90% 50% 50% 50% C A B D E LOW = ALL OUTP UTS E NABLE D p(STH-QL)t p(CH-SQX)t DATA p(STH-QH)t OUTPUT ENABLE OUT N DATA 10% 50% dis(BQ)t en(BQ)t HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D) rt ft 50% 90% NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specifi ed maxi- mum clock frequency. Powering-on with the inputs in the low state ensures that the registers and latches power-on in the low state (POR). Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUT- PUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applica- tions where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (OFF). The information stored in the latches or shift register is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. Key Description Symbol Time (ns) A Data Active Time Before Clock Pulse (Data Set-Up Time) tsu(D) 25 B Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B Terminal List Table Name Description Pin 18-pin 20-pin VEE Power Ground to substrate 1, 9 1, 9 CLK Clock 2 2 DATA IN Serial Data In 3 3 GND Logic Ground 4 4 VDD Logic Supply 5 5 DATA OUT Serial Data Out, for cascading devices 6 6 ST Strobe 7 7 OE Output Enable (active low) 8 8 K Common to +V L , for inductive loads 10 12 NC Not connected – 10, 11 OUT8 Sink Output 8 11 13 OUT7 Sink Output 7 12 14 OUT6 Sink Output 6 13 15 OUT5 Sink Output 5 14 16 OUT4 Sink Output 4 15 17 OUT3 Sink Output 3 16 18 OUT2 Sink Output 2 17 19 OUT1 Sink Output 1 18 20 Allowable Package Power Dissipation, PD 50 75 100 125 150 2.5 0.5 POWER D I SSI PATI ON ( W) AM BI EN T TEM PERATU RE ( ºC) 2.0 1.5 1.0 18-LE AD S OIC , R θJA=8 0°C/ W 20-LE AD S OIC , R θJA=7 0°C/ W 18-P IN DIP , R θJA=6 0°C/ W
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B SUB VEE SERIAL DATA OUT SERIAL DATA IN OUTPUT ENABLE LOGIC SUPPLY STROBE LOGIC GROUND CLOCK CLK VDD ST OE SHIFT REGISTER LATCHES
18 OUT 1
Package LW[TBD] (20-pin Wide Body SOIC) Package LW (18-pin Wide Body SOIC) DATA OUT V EE DATA IN OUTPUT EN A BL E OUT 1 OUT 2 OUT 3 NO CON N ECT . NO CON N ECT. NCNC LOGI C SUPPLY STRO BE GND CLOCK OUT 6 OUT 7 OUT 8 OUT 5 OUT 4 SU B CLK SU B VDD ST OE K LATCHE S SH I FT REGI STER V EE 181 Package A (18-pin DIP) Note the 18-pin DIP package and the SOIC packages are electrically identical and share common terminal number assignments. SU B SERI A L DATA OUT SERI A L DATA IN OUTPUT EN A BL E STRO BE CLOCK +5 V –15 V +30 V CLK V DD ST OE SH I FT REGI STER LATCHE S SU B Typical Application Relay/solenoid driver using split supply
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B Package A 18-pin DIP 0.355 0.204 7.62 BSC Dwg. MA-001-18A mm 10.92 MAX 1 9 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 23.37 22.35 Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 0.014 0.008 0.300 BSC Dwg. MA-001-18A in 0.430 MAX 1 9 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 0.920 0.880
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B Package LW 18-pin Wide Body SOIC Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-18A in 0.050 BSC 18 10 0.419 0.394 0.2992 0.2914 0.4625 0.44690.0926 0.1043 0° TO 8° 2 30.51 0.33 0.10 MIN. 0.32 0.23 1.27 0.40 Dwg. MA-008-18A mm 1.27 BSC 7.60 7.40 10.65 10.00 11.75 11.35 2.65 2.35
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B Package LW-20 20-pin Wide Body SOIC 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-20 in 0.050 BSC 20 11 0.2992 0.2914 0.419 0.394 0.5118 0.49610.0926 0.1043 0° TO 8° 2 30.51 0.33 0.10 MIN. Dwg. MA-008-20 mm 1.27 BSC 0.32 0.23 1.27 0.40 7.60 7.40 10.65 10.00 13.00 12.602.65 2.35 Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative.
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6841 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.114B The products described here are manufactured under one or Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2004, 2005 AllegroMicrosystems, Inc.