A6833 ALLEGRO
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26185.116B A6833 DABiC-5 32-Bit Serial Input Latched Sink Drivers Designed to reduce logic supply current, chip size, and system cost, the A6833 integrated circuits offer high-speed operation for thermal print- ers. These devices can also be used to drive multiplexed LED displays or incandescent lamps within their 125 mA peak output current rating. The combination of bipolar and MOS technologies gives the A6833 smart power ICs an interface flexibility beyond the reach of standard buffers and power driver circuits. These 32-bit drivers have bipolar open-collector npn Darlington out- puts, a CMOS data latch for each of the drivers, a 32-bit CMOS shift register, and CMOS control circuitry. The high-speed CMOS shift registers and latches allow operation with most microprocessor-based systems. Use of these drivers with TTL may require input pull-up resis- tors to ensure an input logic high. CMOS serial data outputs permit cascading for applications requiring additional drive lines. The A6833 is supplied in a 44-lead plastic chip carrier (quad pack), intended for surface mounting on solder lands with 0.050 in. (1.27 mm) centers. These devices are lead (Pb) free, with 100% matte tin plated leadframes. 3.3 V to 5 V logic supply range To 10 MHz data input rate 30 V minimum output breakdown Darlington current-sink outputs Low-power CMOS logic and latches Schmitt trigger inputs for improved noise immunity Use the following complete part numbers when ordering: AB SO LUTE MAX I MUM RAT INGS Part Number Pins Package A6833SEP-T 44 PLCC Continuous Output Current (each output), IOUT ... 125 mA Package Power Dissipation, PD Operating Temperature Range Ambient Temperature, T *Derate linearly to 0 W at +150ºC. Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges.
FEATURES
Thermal printheads Multiplexed LED displays Incandescent lamps
APPLICATIONS
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.116B Functional Block Diagram 32-BIT S HIFT R E GIS TE R LA TCHE S CLOCK SERI A L DATA IN STROBE OUTPUT EN A BL E V DD SERI A L D A T A OUT MOS BIPOLAR OUT OUT OUT OUT OUT OUT1 2 3 30 31 32 GROUND POWER SU B LOGIC GROUND Typical Input Circuit Typical Output Driver IN VDD SUB OUT
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.116B ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V Characteristic Symbol Test Conditions Vdd = 3.3 V V dd = 5 V Output Leakage Current I CEX VOUT = 30 V – – 10 – – 10 μA Collector–Emitter Saturation Voltage VCE(SAT) IOUT = 50 mA – – 0.7 – – 0.7 V IOUT = 100 mA – – 1.0 – – 1.0 V Input Voltage VIN(1) 2.2 – – 3.3 – – V Input Current IIN(1) VIN = VDD – < 0.01 1.0 – < 0.01 1.0 μA Serial Data Output Voltage VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V Maximum Clock Frequency2 fc 10 – – 10 – – MHz Logic Supply Current IDD(1) One output on, IOUT = 100 mA – – 2.0 – – 2.0 mA IDD(0) All outputs off – – 100 – – 100 μA Output Enable-to-Output Delay tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Strobe-to-Output Delay tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Fall Time t f VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 500 – – 500 ns Output Rise Time t r VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 500 – – 500 ns Clock-to-Serial Data Out Delay t p(CH-SQX) IOUT = ±200 μA – 50 – – 50 – ns 1Positive (negative) current is defined as conventional current going into (coming out of) the specified device pin. 2Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State Serial Shift Register Contents Serial Latch Contents Output Output Contents Data Clock Data Strobe Enable HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN Truth Table
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.116B Timing Requirements and Specifications (Logic Levels are VDD and Ground) CLOCK SERI A L DATA IN STROBE OUTPUT ENABLE OUT N 50%SERI A L DATA OUT DATA DATA 10% 90% 50% 50% 50% C A B D E HIGH = ALL OUTPUTS E NABLE D p(S T H-Q L )t p(C H-S Q X )t DATA p(S T H-Q H)t OUTPUT ENABLE OUT N DATA 10% 50% dis (B Q )t en(BQ)t LOW = ALL OUTPUTS BLANKED (DISABLED) rt ft 50% 90% NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be low during serial data entry. When the OUTPUT ENABLE input is low, the output sink drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input high, the outputs are controlled by the state of their respective latches. Key Description Symbol Time (ns) A Data Active Time Before Clock Pulse (Data Set-Up Time) tsu(D) 25 B Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.116B 618 28 40 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT OUT10 OUT11 OUT NC STROBE POWER GROUND SERIAL DATA IN LOGIC SUPPLY CLOCK SERIAL DATA OUT OUTPUT ENABLE NC OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 NC OUT13 OUT14 OUT15 OUT16 LOGIC GROUND OUT17 OUT18 OUT19 OUT20 NC SUB REGISTER REGISTER LATCHES LATCHES ST CLK OE VDD A6833SEP
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.116B Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.510 1.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 16.662 16.510 8.10 7.39 8.10 7.39 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. A6833SEP
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6833 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.116B The products described here are manufactured under one or Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2003, 2004, 2005 AllegroMicrosystems, Inc.