A6832 ALLEGRO
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Technical content
26185.110F A6832 DABiC-5 32-Bit Serial Input Latched Sink Drivers Intended originally to drive thermal printheads, the A6832 has been optimized for low output-saturation voltage, high-speed operation, and pin confi gurations that are the most convenient for the tight space requirements of high-resolution printheads. These integrated circuits can also be used to drive multiplexed LED displays or incandescent lamps at up to 125 mA peak current. The combination of bipolar and MOS technologies gives the A6832 arrays an interface fl exibility beyond the reach of standard buffers and power driver circuits. The devices each have 32 bipolar npn open-collector saturated driv- ers, a CMOS data latch for each of the drivers, two 16-bit CMOS shift registers, and CMOS control circuitry. The high-speed CMOS shift reg- isters and latches allow operation with most microprocessor-based sys- tems. Use of these drivers with TTL may require input pull-up resistors to ensure an input logic high. MOS serial data outputs permit cascading for interface applications requiring additional drive lines. The A6832 is supplied in a 44-lead plastic leaded chip carrier (package suffi x EP), for surface-mount applications requiring minimum area. These devices are lead (Pb) free, with 100% matte tin plated leadframes. 3.3 V to 5 V logic supply range To 10 MHz data input rate Schmitt trigger inputs for improved noise immunity Low-power CMOS logic and latches 40 V current sink outputs Low saturation voltage –40°C operation available Use the following complete part numbers when ordering: AB SO LUTE MAX I MUM RAT INGS Part Number Pins Package Operating Temperature A6832SEP-T 44 PLCC –20ºC to +85ºC A6832EEP-T 44 PLCC –40ºC to +85ºC Package Power Dissipation, PD, see chart, page 5 Operating Temperature Range Ambient Temperature, T Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges.
FEATURES
Thermal printheads Multiplexed LED displays Incandescent lamps
APPLICATIONS
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.110F Functional Block Diagram 32-BIT S HIFT R E GIS TE R LA TCHE S CLOCK SERI A L DATA IN STROBE OUTPUT EN A BL E V DD SERI A L D A T A OUT MOS BIPOLAR OUT OUT OUT OUT OUT OUT1 2 3 30 31 32GROUND Typical Input Circuit Typical Output Driver IN VDD OUT VDD
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.110F ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V Characteristic Symbol Test Conditions Vdd = 3.3 V V dd = 5 V Output Leakage Current I CEX VOUT = 40 V – – 10 – – 10 μA Collector–Emitter Saturation Voltage VCE(SAT) IOUT = 50 mA – – 275 – – 275 mV IOUT = 100 mA – – 550 – – 550 mV Input Voltage VIN(1) 2.2 – – 3.3 – – V Input Current IIN(1) VIN = VDD – < 0.01 1.0 – < 0.01 1.0 μA Serial Data Output Voltage VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V Maximum Clock Fre- quency2 fc 10 – – 10 – – MHz Logic Supply Current IDD(1) One output on, IOUT = 100 mA – – 6.0 – – 6.0 mA IDD(0) All outputs off – – 100 – – 100 μA Output Enable-to-Output Delay tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Strobe-to-Output Delay tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Fall Time t f VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Rise Time t r VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Clock-to-Serial Data Out Delay t p(CH-SQX) IOUT = ±200 μA – 50 – – 50 – ns 1Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin. 2Operation at a clock frequency greater than the specifi ed minimum value is possible but not warranteed. L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State Serial Shift Register Contents Serial Latch Contents Output Output Contents Data Clock Data Strobe Enable HH R 1 R2 ... R N-2 RN-1 RN-1 LL R 1 R2 ... R N-2 RN-1 RN-1 XR 1 R2 R3 ... R N-1 RN RN Truth Table
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.110F Timing Requirements and Specifi cations (Logic Levels are VDD and Ground) CLOCK SERI A L DATA IN STROBE OUTPUT ENABLE OUT N 50%SERI A L DATA OUT DATA DATA 10% 90% 50% 50% 50% C A B D E HIGH = ALL OUTPUTS E NABLE D p(S T H-Q L )t p(C H-S Q X )t DATA p(S T H-Q H)t OUTPUT ENABLE OUT N DATA 10% 50% dis (B Q )t en(BQ)t LOW = ALL OUTPUTS BLANKED (DISABLED) rt ft 50% 90% NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specifi ed maximum clock frequency. Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be low during serial data entry. When the OUTPUT ENABLE input is low, the output sink drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input high, the outputs are controlled by the state of their respective latches. Key Description Symbol Time (ns) A Data Active Time Before Clock Pulse (Data Set-Up Time) tsu(D) 25 B Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.110F 618 28 40 OUT NC STROBE GROUND SERIAL DATA IN LOGIC SUPPLY CLOCK SERIAL DATA OUT OUTPUT ENABLE NC OUT32 OUT31 OUT21 NC OUT 13 OUT 16 NC OUT 17 OUT 20 NC VDD SHIFT REGISTER LATCHES SHIFT REGISTER LATCHES OUT12 OUT2 A6832SEP/A6832EEP 50 75 100 125 15 0 PACKAGE POWER DISSIPATION (W) AMBIENT TEMPERATURE (º C) 4.0 3.0 3.5 0.5 2.5 2.0 1.5 1.0 4.5 A6832EP, R = 54 °C/WθJA A6832EP, R = 30 °C/WθJA Allowable Power Dissipation, PD* *Additional thermal information is available on the Allegro Web site.
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.110F Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) 1828 Dwg. MA-005-44A in 0.020 MIN 0.050 BSC 144 0.021 0.013 INDEX AREA 2 6 1729 0.695 0.685 0.032 0.026 0.319 0.291 0.319 0.291 0.180 0.165 0.695 0.685 0.656 0.650 0.656 0.650 Dwg. MA-005-44A mm 17.65 17.40 0.51 MIN 4.57 4.20 17.65 17.40 16.662 16.510 1.27 BSC 0.812 0.661 144 0.533 0.331 INDEX AREA 40 6 16.662 16.510 8.10 7.39 8.10 7.39 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. A6832SEP and A6832EEP
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6832 DABiC-5 32-Bit Serial-Input Latched Sink Drivers Data Sheet 26185.110F The products described here are manufactured under one or Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2003, 2004, 2005, 2006 AllegroMicrosystems, Inc.