A6821 ALLEGRO
Document overview
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Technical content
26185.112B Package LW 16-pin Wide Body SOIC A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers A merged combination of bipolar and MOS technology gives these devices an interface fl exibility beyond the reach of standard logic buffers and power driver arrays. Typical applications include driving multiplexed LED displays or incandescent lamps. The A6821 has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The CMOS inputs are compatible with standard CMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, the drivers can be cascaded for interface applications requiring additional drive lines. The A6821SA is furnished in a standard 16-pin plastic DIP. The A6821EA is a 16-pin plastic DIP, capable of operation from -40°C to +85°C. The A6821SLW is a 16-lead wide-body SOIC, for surface- mount applications. These devices are lead (Pb) free, with 100% matte tin plated leadframes. 3.3 V to 5 V logic supply range Power on reset (POR) To 10 MHz data input rate CMOS, TTL compatible –40°C operation available Use the following complete part numbers when ordering: AB SO LUTE MAX I MUM RAT INGS Part Number Package Ambient A6821SA-T 16-pin DIP –20ºC to +85ºC A6821EA-T 16-pin DIP –40ºC to +85ºC A6821SLW-T 16-pin wide body SOIC –20ºC to +85ºC Continuous Output Current (each output), IOUT ... 500 mA Package Power Dissipation, PD Operating Temperature Range Ambient Temperature, T Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges.
FEATURES
Multiplexed LED displays Incandescent lamps
APPLICATIONS
Schmitt trigger inputs for improved noise immunity Low-power CMOS logic and latches High-voltage current-sink outputs Internal pull-up/pull down resistors
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.112B Functional Block Diagram MOS BIPOLAR OUT 1 OUT 2 LOGIC GROUND STROBE OUTPUT ENABLE (ACTIVE LOW) SERI A L DATA OUT OUT 3 CLOCK SERI A L DATA IN S E R IAL-PAR ALLE L S HIFT R E GIS TE R LATCHES V DD LOGIC SUPPLY OUT 6 OUT 7 OUT 8OUT 4 OUT 5 POWER GROUND SUB Typical Input Circuits Typical Output Driver CLOCK SERIAL DATA IN VDD STROBE OUTPUT ENABLE VDD OUT 7.2 k 3 k SUB ΩΩ
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.112B ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V Characteristic Symbol Test Conditions Vdd = 3.3 V V dd = 5 V Output Leakage Current I CEX VOUT = 50 V – – 10 – – 10 μA Collector–Emitter Saturation Voltage VCE(SAT) IOUT = 100 mA – – 1.1 – – 1.1 V IOUT = 200 mA – – 1.3 – – 1.3 V IOUT = 350 mA – – 1.6 – – 1.6 V Input Voltage VIN(1) 2.2 – – 3.3 – – V Input Resistance R IN 50 – – 50 – – k Ω Serial Data Output Voltage VOUT(1) IOUT = –200 μA 2.8 3.05 – 4.5 4.75 – V VOUT(0) IOUT = 200 μA – 0.15 0.3 – 0.15 0.3 V Maximum Clock Frequency2 fc 10 – – 10 – – MHz Logic Supply Current IDD(1) One output on, OE = L, ST = H – – 2.0 – – 2.0 mA IDD(0) All outputs off, OE = H, ST = H, P1 through P8 = L – – 100 – – 100 μA Output Enable-to-Output Delay tdis(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs ten(BQ) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Strobe-to-Output Delay tp(STH-QL) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs tp(STH-QH) VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Fall Time t f VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Output Rise Time t r VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – – 1.0 – – 1.0 μs Clock-to-Serial Data Out Delay t p(CH-SQX) IOUT = ±200 μA – 50 – – 50 – ns 1Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin. 2Operation at a clock frequency greater than the specifi ed minimum value is possible but not warranteed. L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State OE = Output Enable ST = Strobe Serial Shift Register Contents Serial Latch Contents Output Output Contents Data Clock Data Strobe Enable R1 R2 R3 ... R 8R 8 XXX. . . X X X L R1 R2 ... R 7LL R1 R2 R3 ... R 8 XXX. . . X L P HHH H H R1 R2 ... R 7HH H... Truth Table
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.112B Timing Requirements and Specifi cations (Logic Levels are VDD and Ground) CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE OUT N 50%SERIAL DATA OUT DATA DATA 10% 90% 50% 50% 50% C A B D E LOW = ALL OUTP UTS E NABLE D p(STH-QL)t p(CH-SQX)t DATA p(STH-QH)t OUTPUT ENABLE OUT N DATA 10% 50% dis(BQ)t en(BQ)t HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D) rt ft 50% 90% NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specifi ed maxi- mum clock frequency. Powering-on with the inputs in the low state ensures that the registers and latches power-on in the low state (POR). Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUT- PUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applica- tions where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (OFF). The information stored in the latches or shift register is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. Key Description Symbol Time (ns) A Data Active Time Before Clock Pulse (Data Set-Up Time) tsu(D) 25 B Data Active Time After Clock Pulse (Data Hold Time) th(D) 25 C Clock Pulse Width tw(CH) 50 D Time Between Clock Activation and Strobe tsu(C) 100 E Strobe Pulse Width tw(STH) 50
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.112B 8 67% 59% 54% 49% 43% 7 77% 68% 62% 56% 49% 6 90% 79% 72% 65% 57% 5 100% 95% 86% 78% 68% 4 100% 100% 100% 98% 86% 3 100% 100% 100% 100% 100% 2 100% 100% 100% 100% 100% 1 100% 100% 100% 100% 100% A6821SLW A6821SA/A6821EA Number of Outputs ON Ambient Temperature 25°C4 0 °C5 0 °C6 0 °C7 0 °C 8 90% 79% 72% 65% 57% 7 100% 90% 82% 74% 65% 6 100% 100% 96% 86% 76% 5 100% 100% 100% 100% 91% 4 100% 100% 100% 100% 100% 3 100% 100% 100% 100% 100% 2 100% 100% 100% 100% 100% 1 100% 100% 100% 100% 100% Terminal List Table Name Description Pin CLK Clock 1 Serial Data In 2 Logic Ground* 3 VDD Logic Supply 4 Serial Data Out 5 ST Strobe 6 OE Output Enable (active low) 7 SUB Power Ground* 8 OUT8 Serial Data Output 9 OUT7 Serial Data Output 10 OUT6 Serial Data Output 11 OUT5 Serial Data Output 12 OUT4 Serial Data Output 13 OUT3 Serial Data Output 14 OUT2 Serial Data Output 15 OUT1 Serial Data Output 16 * There is an indeterminate resistance between logic ground and power ground. For proper operation, these terminals must be externally connected together. Maximum Allowable Duty Cycle, IOUT = 200 mA, VDD = 5 V
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.112B Package LW 16-pin Wide Body SOIC SERIAL DATA OUT SERIAL DATA IN OUTPUT ENABLE LOGIC SUPPLY STROBE LOGIC GROUND CLOCK CLK V ST OE DD SUB POWER GROUND SHIFT REGISTER LATCHES
16 OUT1
V ST OE DD SUB POWER GROUND S HIFT R E GIS TE R LATCHES
16 OUT 1
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.112B NOTES: 1. Lead thickness is measured at seating plane or below. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor’s option within limits shown. 0.014 0.008 0.300 BSC Dwg. MA-001-16A in 0.430 MAX 1 8 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 0.775 0.735 0.355 0.204 7.62 BSC Dwg. MA-001-16A mm 10.92 MAX 1 8 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 19.68 18.67 Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) Package A 16-pin DIP
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.112B NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor’s option within limits shown. Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) 1 2 3 0.2992 0.2914 0.4133 0.3977 0.419 0.394 0.020 0.013 0.0926 0.1043 0.0040 MIN. 0.0125 0.0091 0.050 0.016 0° TO 8° Dwg. MA-008-16A in 0.050 BSC 16 9 916 1 2 3 7.60 7.40 10.50 10.10 10.65 10.00 0.51 0.33 2.65 2.35 0.10 MIN. 0.32 0.23 1.27 0.40 0° TO 8° Dwg. MA-008-16A mm 1.27 BSC Package LW 16-pin Wide Body SOIC
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Data Sheet 26185.112B The products described here are manufactured under one or Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2004, 2005 AllegroMicrosystems, Inc.