A6801

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26180.110H

Description

The A6800 and A6801 latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (D type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar NPN Darlingtons. This merged technology provides versatile, fl exible interface. These BiMOS power interface ICs greatly benefi t the simplifi cation of computer or microproces- sor I/O. The A6800 ICs each contain four latched drivers. A6801 ICs contain eight latched drivers. The CMOS inputs are compatible with standard CMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small DC motors, and so forth. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transis- tors are capable of sinking 600 mA and can withstand at least 50 V in the off state. Because of limitations on package power dissipation, the simultaneous operation of all driv- ers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. Features and Benefits ▪ 3.3 to 5 V logic supply range ▪ Up to 10 MHz data input rate ▪ High-voltage, high-current outputs ▪ Darlington current-sink outputs, with improved low-saturation voltages ▪ CMOS, TTL compatible inputs ▪ Output transient protection ▪ Internal pull-down resistors ▪ Low-power CMOS latches DABiC-5 Latched Sink Drivers Continued on the next page… Packages Functional Block Diagram Approximate scale 1:1 A6800 and A6801 A6800 14-pin SOICN (L package) A6800 14-pin 7.62 mm DIP (A package) A6801 24-pin SOICW (LW package) A6801 28-pin PLCC (EP package) C OMMON GROUND STROBE OUTPUT ENABLE IN N C OMMON MOS C ONTR OL TYPICAL MOS LATCH TYPICAL BIPOLAR DRIVE OUT N CLEAR SUPPLY V DD

DABiC-5 Latched Sink Drivers 2Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 Selection Guide Part Number Package Packing A6800SA-T* 14-pin DIP 25 per tube A6800SLTR-T 14-pin SOIC 2500 per reel A6801SEPTR-T 28-pin PLCC 800 per reel A6801SLWTR-T 24-pin SOIC 1000 per reel *Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 4, 2009. The A6800SA is furnished in a 14-pin DIP with 7.62 mm (0.300 in.) row centers, the A6800SL and A6801SLW in surface- mountable SOICs; and the A6801SEP in a 28-lead PLCC. These devices are lead (Pb) free, with 100% matte tin plated leadframes. Applications include: ▪ Relays ▪ Lamps ▪ Solenoids ▪ Small DC motors Absolute Maximum Ratings* Characteristic Symbol Notes Rating Units Output Voltage V CE 50 V Supply Voltage V DD 7V Input Voltage Range V IN –0.3 to VDD + 0.3 V Continuous Collector Current I C 600 mA Operating Ambient Temperature T A Range S –20 to 85 ºC Maximum Junction Temperature T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC *Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. Description (continued)

DABiC-5 Latched Sink Drivers 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 Typical Input Circuit IN VDD Allowable Power Dissipation 50 75 100 125 150 2.5 0.5 PACKAGE POWER DISSIPATION (W) AMBIENT TEMPERATURE (ºC) 2.0 1.5 1.0 28-LEAD PLCC, RQJA = 68oC/W 14-PIN DIP, RQJA = 73oC/W 14-LEAD SOIC, RQJA = 120oC/W 24-LEAD SOIC, RQJA = 85oC/W

DABiC-5 Latched Sink Drivers 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage VDD = 3.0 to 5.5 V Characteristic Symbol Test Conditions VDD = 3.3 V V DD = 5 V Output Leakage Current I CEX VOUT = 50 V – – 10 – – 10 μA Output Sustaining Voltage V CE(SUS) IOUT = 350 mA, L = 3 mH 35 – – 35 – – V Collector-Emitter Saturation Voltage VCE(SAT) IOUT = 100 mA – 0.8 1.0 – 0.8 1.0 V IOUT = 200 mA – 0.9 1.1 – 0.9 1.1 V IOUT = 350 mA (See note 2) – 1.0 1.3 – 1.0 1.3 V Input Voltage VIN(1) 2.2 – – 3.3 – – V Input Resistance R IN 50 – – 50 – – k Ω Logic Supply Current IDD(1) One output on, IOUT = 100 mA – – 1.0 – – 1.0 mA IDD(0) All outputs off – 130 150 – 130 150 μA Clamp Diode Leakage Current I r Vr = 50 V – – 50 – – 50 μA Clamp Diode Forward Voltage V f If = 350 mA – – 2.0 – – 2.0 V Output Fall Time t f VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – 80 – – 80 – ns Output Rise Time t r VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF – 100 – – 100 – ns 1Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic 1. 2Because of limitations on package power dissipation, the simultaneous operation of multiple drivers can only be accomplished by reduction in duty cycle. O U T N IN N STROBE CLEAR EN ABLE t - 1 t 01 0 0 X O F F 11 0 0 X O N XX 1 X X O F F XX X 1 X O F F X 0 0 0 ON ON X0 0 0 O F F O F F X = irrelevant t-1 = previous output s tate t = present out put st at e OUTPUT Truth Table

DABiC-5 Latched Sink Drivers 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 *Conditions for output transition testing are: VCC = 50 V , VDD = 5 V , R1 = 500 Ω, C1 ≤ 30 pF. Key Description Time (ns) A Minimum data active time before Strobe enabled (Data Set-Up Time) 25 B Minimum data active time after Strobe disabled (Data Hold Time) 25 C Minimum Strobe pulse width 50 D Maximum time between Strobe activation and transition from output on to output off* 500 E Maximum time between Strobe activation and transition from output off to output on* 500 F Maximum time between Clear activation and transition from output on to output off* 500 G Minimum Clear pulse width 50 H Minimum data pulse width 100 tdis(BQ) Output Enable to output off delay* 500 ten(BQ) Output Enable to output on delay* 500 Timing Requirements and Specifi cations (Logic Levels are VDD and Ground) NOTE: Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output off condition regardless of the data or STROBE input levels. A high CLEAR STROBE INN OUTN A C BC B H D E G A C B H EF OUTPUT ENABLE will set all outputs to the off con- tdition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. OUTPUT ENABLE OUT N DATA 10% 50% HIGH = ALL OUTPUTS DISABLED (OFF) rt ft 50% 90% en(BQ)t tdis(BQ)

DABiC-5 Latched Sink Drivers 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 SUPPLY GROUND CLEAR OUT1 OUT2 OUT3 Dwg. PP-014A OUT4 141 COMMON OUTPUT ENABLE IN1 STROBE IN2 IN 3 IN 4 VDD LATCHES Note: The A6800 SOIC and DIP packages are electrically identical and share a common terminal number assignment. GROUND OUTPUT ENABLE STROBE K ST V DD OE Dwg. PP-037 LATCHES NC NC NC NC NC NC SUPPLY LAMP DIODE COMMON C CLEAR OUT1 IN8 OUT8 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 IN1 IN2 IN3 IN4 IN5 IN6 IN7 22 3 SUPPLY CLEAR 1 OUTPUT ENABLE STROBE VDD

22 OUT1

Dwg. PP-015-1 OUT8 COMMON IN5 IN 6 IN 7 IN 8 LATCHES NO CONNECTION NO CONNECTIONNCNC12 13

DABiC-5 Latched Sink Drivers 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 TYPICAL APPLICATION UNIPOLAR STEPPER-MOTOR DRIVE Dwg. No. B-1537 7 8 OUT 2 OUT 3 OUT 4 OUT 1 +30 V IN 1 IN 2 IN 3 IN 4 STROBE CLEAR OUTPUT EN A BLE ( A CTI VE LOW) LA TCHES A6800S A V DD V DD +30 V STROBE IN 1 IN 2 IN 3 IN 4 OUT 1 OUT 2 OUT 3 OUT 4 Dwg. GP-060 STROBE IN 1 IN 2 IN 3 IN 4 OUT 1 OUT 2 OUT 3 OUT 4 Dwg. GP-060-1 UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE

DABiC-5 Latched Sink Drivers 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 Package A (A6800) 14-pin DIP CSEATING PLANE

5.33 MAX

0.46 ±0.12 6.35 +0.76 –0.25 19.05 +0.64 –0.38 3.30 +0.51 –0.38 10.92 +0.38 –0.25 1.52 +0.25 –0.38 7.62 2.54 0.25 +0.10 –0.05 A For Reference Only Dimensions in millimeters (reference JEDEC MS-001 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area

DABiC-5 Latched Sink Drivers 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 Package EP (A6801) 28-pin PLCC 21 2 8 A Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area For Reference Only (reference JEDEC MS-018 AB) Dimensions in millimeters 12.45±0.13 12.45±0.13

0.51 MIN

PLANEC0.10 28X 11.51±0.08 5.21±0.36 5.21±0.36 0.74±0.08 5.21±0.36 0.43±0.10 5.21±0.36 11.51±0.08 0.51 1.27 4.37 +0.20 –0.18

DABiC-5 Latched Sink Drivers 10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 Package L (A6800) 14-pin SOICN Package LW (A6801) 24-pin SOICW CSEATING PLANE GAUGE PLANE SEATING PLANE For Reference Only Dimensions in millimeters (reference JEDEC MS-012 AB) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A 1.27 A Terminal #1 mark area B PCB Layout Reference View B Reference pad layout (reference IPC SOIC127P600X175-14M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances 3.90 ±0.10 9.90 ±0.10 6.00 ±0.20 0.21 ±0.04 4° ±4 0.25 0.84 +0.43 –0.44

1.75 MAX

1.27 1.75 0.65 5.60 0.18 +0.07 –0.08 C0.10 14X 0.41 ±0.10 1.27 B Reference pad layout (reference IPC SOIC127P1030X265-24M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances B 0.20 ±0.10 0.41 ±0.10 2.20 0.65 9.60 1.27 A 15.40±0.20

2.65 MAX

PLANEC0.10 24X For Reference Only (Reference JEDEC MS-013 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 0.25 GAUGE PLANE SEATING PLANE PCB Layout Reference View 4° ±4 0.27 +0.07 –0.06 0.84 +0.44 –0.43

DABiC-5 Latched Sink Drivers 11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A6800 and A6801 Copyright ©2003-2009, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com