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NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. Recommended Substitutions: For existing customer transition, and for new customers or new appli- cations, refer to your Allegro sales representative. 8-Bit Serial Input DMOS Power Driver A6595 Date of status change: May 3, 2010 These parts are no longer in production The device should not be purchased for new design applications. Samples are no longer available. Discontinued Product
Description
The A6595 combines an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial- data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. The A6595 DMOS open-drain outputs are capable of sinking up to 750 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. The A6595 is furnished in a 20-pin dual in-line plastic package that is lead (Pb) free, with 100% matte tin leadframe plating. Copper leadframe base material, reduced supply current requirements, and low on-state resistance allow the device to sink 150 mA from all outputs continuously, to ambient temperatures to 125°C. 26185.120a Features and Benefits ▪ 50 V minimum output clamp voltage ▪ 250 mA output current (all outputs simultaneously) ▪ 1.3 Ω typical rDS(on) ▪ Low power consumption ▪ Replacements for TPIC6595N and TPIC6595DW 8-Bit Serial Input DMOS Power Driver Package: 20-pin DIP (suffix A) Pin-out Diagram Not to scale A6595 LOGIC GROUND SERIAL DATA OUT SERIAL DATA IN LOGIC SUPPLY V DD STROBE POWER GROUND CLOCKCLK ST OUT 7 OUT 6 OUT 5 OUT 0 OUT 1 OUT 2 OUT 3 OUT 4 10 11 POWER GROUND POWER GROUND OUTPUT ENABLE OE REGISTER CLEAR POWER GROUND LATCHES REGISTER REGISTER LATCHES CLR
8-Bit Serial Input DMOS Power DriverA6595 2Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A. Absolute Maximum Ratings* Characteristic Symbol Notes Rating Units Logic Supply Voltage V DD 7.0 V Input Voltage Range V I –0.3 to 7.0 V Output Voltage V O 50 V Output Drain Current IO Continuous, each output, all outputs on 250 mA IOM Pulsed tw ≤100 μs, duty cycle ≤ 2%; each out- put, all outputs on 750 mA Pulsed tw ≤100 μs, duty cycle ≤ 2%; 2.0 A Single-Pulse Avalanche Energy E AS 75 mJ Operating Ambient Temperature T A Range K –40 to 125 ºC Maximum Junction Temperature T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC *These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. Selection Guide Part Number Packing A6595KA-T 18 pieces per tube Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 32 ºC/W *Additional thermal information available on the Allegro website. 50 75 100 125 150 4.0 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE oC) 3.5 3.0 2.5 2.0 1.0 1.5
8-Bit Serial Input DMOS Power DriverA6595 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. POWER GROUND Dwg. FP-013-5 CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE (ACTIVE LOW) SERIAL DATA OUT SERIAL-PARALLEL SHIFT REGISTER D-TYPE LATCHES V DD LOGIC SUPPLY REGISTER CLEAR (ACTIVE LOW) OUT 0 OUT N LOGIC GROUND POWER GROUND Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally. Functional Block Diagram SRG8 R Device Logic Diagram
8-Bit Serial Input DMOS Power DriverA6595 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. TRUTH TABLE stnetnoC tuptuOstnetnoC hctaLlaireSstnetnoC retsigeR tfihS tuptuOataDkcolCataD HH R 0 R1 …R 5 R6 R6 LL R 0 R1 …R 5 R6 R6 XR 0 R1 R2 …R 6 R7 R7 XXX … XX X — R 0 R1 R2 …R 6 R7 P0 P1 P2 …P 6 P7 P7 P0 P1 P2 …P 6 P7 LP 0 P1 P2 …P 6 P7 XXX … XX H HHH … HH L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous Stat e SERIAL DATA OUT LOGIC INPUTS Dwg. EP-063-2 VDD OUT DMOS POWER DRIVER OUTPUT IN Dwg. EP-010-15 VDD Dwg. EP-063-3 OUT RECOMMENDED OPERATING CONDITIONS over operating temperature range
8-Bit Serial Input DMOS Power DriverA6595 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Limits stinU.xaM.pyT.niMsnoitidnoC tseTlobmyScitsiretcarahC Output Breakdown V (BR)DSX IO V——05Am 1 = Voltage Off-State Output I DSX VO 0.150.0—V 04 = μA Current VO = 40 V, TA = 125°C — 0.15 5.0 μA Static Drain-Source rDS(on) IO = 250 mA, VDD = 4.5 V — 1.3 2.0 Ω On-State Resistance IO = 250 mA, VDD = 4.5 V, TA = 125°C— 2 . 0 3 . 2 Ω IO = 500 mA, VDD = 4.5 V (see note) — 1.3 2.0 Ω Nominal Output I ON VDS(on) = 0.5 V, TA = 85°C— 2 5 0 — m A Current Logic Input Current I IH VI = VDD 0.1——V 5.5 = μA IIL VI = 0, VDD 0.1-——V 5.5 = μA Logic Input Hysteresis V I(hys) —1 . 3— V SERIAL-DATA V OH IOH = -20 μA, VDD = 4.5 V 4.4 4.49 — V Output Voltage IOH = -4 mA, VDD = 4.5 V 4.1 4.3 — V VOL IOL = 20 μA, VDD = 4.5 V — 0.002 0.1 V IOL = 4 mA, VDD = 4.5 V — 0.2 0.4 V Prop. Delay Time t PLH IO = 250 mA, CL = 30 pF — 650 — ns tPHL IO = 250 mA, CL = 30 pF — 150 — ns Output Rise Time t r IO = 250 mA, CL = 30 pF — 7500 — ns Output Fall Time t f IO = 250 mA, CL = 30 pF — 425 — ns Supply Current I DD(OFF) 00151—wol stupni llA μA IDD(ON) VDD = 5.5 V, Outputs on — 150 300 μA IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs off — 0.6 5.0 mA Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration ≤100μs, duty cycle ≤2%. ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise specified). Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration ≤100 μs, duty cycle ≤2%.
8-Bit Serial Input DMOS Power DriverA6595 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) A. Data Active Time Before Clock Pulse B. Data Active Time After Clock Pulse D. Time Between Clock Activation NOTE – Timing is representative of a 12.5 MHz clock. Higher speeds are attainable. Serial data present at the input is transferred to the shift reg- ister on the rising edge of the CLOCK input pulse. On succeed- ing CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. CLOCK SERIAL DATA IN STROBE OUTPUT ENABLE OUT N Dwg. WP-029-2 50%SERIAL DATA OUT DATA DATA 50% 50% 50% C A B D E LOW = ALL OUTPUTS ENABLED pt DATA 50% pt LOW = OUTPUT ON HIGH = OUTPUT OFF OUTPUT ENABLE OUT N Dwg. WP-030-2 DATA 10% 50% PHLt PLHt HIGH = ALL OUTPUTS DISABLED 90% ft rt
8-Bit Serial Input DMOS Power DriverA6595 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. TEST CIRCUITS Single-Pulse Avalanche Energy Test Circuit and Waveforms EAS = IAS x V(BR)DSX x tAV/2 Dwg. EP-066-1 OUT INPUT IO VO tav IAS = 1.0 A V(BR)DSX VO(ON) 0.11Ω100 mH +15 V DUT
8-Bit Serial Input DMOS Power DriverA6595 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. TERMINAL DESCRIPTIONS Terminal No. Terminal Name Function 1 POWER GROUND Reference terminal for output voltage measurements (OUT 0-3). 2 LOGIC SUPPLY (V DD) The logic supply voltage (typically 5 V). 3 SERIAL DATA IN Serial-data input to the shift-register. 4-7 OUT 0-3 Current-sinking, open-drain DMOS output terminals. 8 CLEAR When (active) low, the registers are cleared (set low).
9 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output driv-
ers are turned OFF (blanked).
10 POWER GROUND Reference terminal for output voltage measurements (OUT
0-3). 11 POWER GROUND Reference terminal for output voltage measurements (OUT 0-7). 12 STROBE Data strobe input terminal; shift register data is latched on rising edge. 13 CLOCK Clock input terminal for data shift on rising edge. 14-17 OUT 4-7 Current-sinking, open-drain DMOS output terminals. 18 SERIAL DATA OUT CMOS serial-data output to the following shift register. 19 LOGIC GROUND Reference terminal for input voltage measurements.
20 POWER GROUND Reference terminal for output voltage measurements (OUT
4-7). NOTE — Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
8-Bit Serial Input DMOS Power DriverA6595 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. CSEATING PLANE
5.33 MAX
0.46 ±0.12 6.35 +0.76 –0.25 26.16 +0.76 –1.27 3.30 +0.51 –0.38 10.92 +0.38 –0.25 1.52 +0.25 –0.38 7.62 2.54 0.38 +0.10 –0.05 A Preliminary dimensions, for reference only Dimensions in inches Metric dimensions (mm) in brackets, for reference only (reference JEDEC MS-001 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Package A, 20-Pin DIP Copyright ©2000-2008, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com