A6280 ALLEGRO

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Technical content

Description

The A6280 is a 3 bit constant current LED driver that has a wide range of output currents. The A6280 controls LED luminance with a pulse width modulation (PWM) scheme that gives the application the capability of displaying a billion colors. The overall maximum current is set by an external resistor. The LED luminance is controlled by performing PWM control on the outputs. The luminance data of the PWM signal for each LED is stored in three 10 bit registers. Each LED can be dot corrected by a 7 bit scalar register that scales the maximum current from 100% down to 36.5%. All the internal latched registers are loaded by a 31 bit serial shift register. One bit is used to control the type of data loaded into the registers, either dot correction / clock divider ratio or luminance data. The remaining 30 bits are used for the data. This helps reduce the pin count of the A6280. To further lower the A6280 pin count, the PWM clock and the serial bus clock share the same pin and work concurrently to control LED luminance and to load data. The A6280 is designed to minimize the number of components needed to drive LEDs with large pixel spacing. Several A6280s can be daisy chained together and controlled by just four control signals (Clock, Serial Data, Latch, and Output Enable). Each of these inputs has buffered outputs on chip. Also, the VIN pin A6280-DS, Rev. 1 Features and Benefits ▪ 5 to 17 V operation ▪ Wide output current range (10 to 150 mA per output) ▪ 3 × 7 bit Dot Correction current settings ▪ 31 bit shift register ▪ 3 ×10 bit PWM luminance settings ▪ Buffered output control pins ▪ Up to 5 MHz serial / PWM clock frequency ▪ Thermal Shutdown / UVLO

3 Bit Constant Current LED Driver with PWM Control

Continued on the next page… Packages: 16 pin DIP (suffix A), and 16 pin QFN/MLP (suffix ES) Application Diagram ES, approximate scale 1:1 A6280 Clock Data Strobe Output Enable Microprocessor Control Board Clock Out Data Out Strobe Out OE Out Clock In Data In Strobe In OE In V LED OutBOutGOutRVIN Power Supply Bus A6280 Pixel Board #1 REXTVREG Clock Out Data Out Strobe Out OE Out Clock In Data In Strobe In OE In V LED OutBOutGOutRVIN A6280 Pixel Board #2 REXTVREG Pixel Board #N Cat5 UTP Cat5 UTP Cat5 UTP Figure 1. Functional drawing of daisy chained display application. Additional pixel boards with A6280 ICs can be applied.

3 Bit Constant Current LED Driver with PWM ControlA6280

2Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Part Number Packing* Mounting A6280EA-T 25 pieces/tube 16 pin DIP A6280EESTR-T 1500 pieces/reel 16 pin QFN/MLP *Contact Allegro for additional packing options. Selection Guide can be tied to the LED voltage supply bus, thus eliminating the need for a separate chip supply bus or an external linear regulator. The A6280 is supplied in a 16 pin dual in line (DIP) package (suffix ‘A’) package and in a 16 lead QFN/MLP (suffix ‘ES’) package. The packages are lead (Pb) free with 100% matte-tin leadframe plating. Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Supply Voltage V IN 17 V Output Voltage V O –0.5 to 17 V Output Current I O 170 mA Ground Current I GND 600 mA Logic Input Voltage Range V I –0.3 to 7 V Operating Ambient Temperature T A Range E –40 to 85 ºC Maximum Junction Temperature T J(max) 150 ºC Storage Temperature T stg –40 to 150 ºC Description (continued) Thermal Characteristics Characteristic Symbol Test Conditions* Rating Units Package Thermal Resistance RθJA Package A, 4 layer PCB 38 ºC/W Package ES, 4 layer PCB 40 ºC/W Package ES, 1 layer PCB with 1 in 2. Cu area 70 ºC/W *For additional information, refer to the Allegro website. 0 2 55 07 5 1 0 0 1 2 5 1 5 0 Temperature (°C) Power Dissipation, PD (mW) 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 Power Dissipation versus Ambient Temperature QJA = 38 ºC/W) Package A, 4 la yer PCB QJA = 40 ºC/W) Package ES, 4 layer PCB QJA = 70 ºC/W) Package ES, 1 lay er PCB

3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Terminal List Table Name Number DescriptionA Package ES Package OUT1 1 11 Sinking output terminal OUT0 2 12 Sinking output terminal SDO 3 13 Buffered serial data output after shift registers LO 4 14 Buffered latch output OEO 5 15 Buffered output enable output CO 6 16 Buffered clock output REXT 7 1 An external resistor at this terminal establishes overall output current VREG 8 2 Regulator decoupling LGND 9 3 Logic ground VIN 10 4 Chip power supply voltage CI 11 5 Serial and PWM clock input OEI 12 6 Output enable input; when low (active), the output drivers are enabled; when high (inactive), all output drivers are turned off (blanked) LI 13 7 Latch input terminal; serial data is latched with high-level input SDI 14 8 Serial data input to shift registers OUT2 15 9 Sinking output terminal PGND 16 10 Power ground Pin-out Drawings Package A Package ES OUT2OUT1OUT0 Regulator Current Regulator 0 Current Regulator 1 Current Regulator 2 Shift Registers Latched Registers LI SDI REXT REXT LGNDPGND CI LO SDO CO OEO OEI VIN VREG Functional Block Diagram PGND OUT2 SDI LI OEI CI VIN LGND OUT1 OUT0 SDO LO OEO CO REXT VREG CO OEO LO SDO CI OEI LI SDI OUT0 OUT1 PGND OUT2 REXT VREG LGND VIN

4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com OPERATING CHARACTERISTICS, valid at TA = 25°C, VIN = 4.75 to 17.0 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Units

ELECTRICAL CHARACTERISTICS

Quiescent Supply Current I DD fCLKIN = 0.0 Hz – – 5.0 mA Operating Supply Current I DD fCLKIN = 5 Mhz – – 15.0 mA Undervoltage Lockout V IN(UV) VIN rising 3.5 – 4.5 V VIN falling 3.0 – 4.0 V VREG Voltage Range V REG IO =15 mA, VIN = 17 V 4.6 – 5.4 V VREG Dropout Voltage V DO IO =15 mA, VIN = 4.75 V – 200 600 mV Output Current (any single output) I O REXT = 5 kΩ, scalar = 100% 135 150.0 165 mA REXT = 15 kΩ 44 – 54 mA Output to Output Matching Error* Err Output to output variation—all outputs on, R EXT = 5 kΩ 7– 7 % Output Voltage Range V DS(min) 1.0 – 3.0 V Load Regulation I %Diff / VDS –± 1 ± 3 % Output Leakage Current I DSX VOH = 17 V – – 1.0 μA Logic Input Voltage VIH 2.0 – – V VIL – – 0.8 V Logic Input Voltage Hysteresis All digital inputs – 150 – mV Logic Input Current I IN VIN = 0 to 5 V –20 – 20 μA Logic Output Voltage VOL VIN ≥ 5.0 V, IO = ±2 mA – – 0.4 V VOH 3.8 – – V Input Resistance R I OEI pin, pull-up 150 300 600 k Ω LI pin, pull-down 100 200 400 k Ω Output Dot Correction Error R EXT = 5 kΩ; LSB – ±1 – bit Thermal Shutdown Temperature T JTSD Temperature increasing – 165 – °C Thermal Shutdown Hysteresis T Jhys –1 5– ° C SWITCHING CHARACTERISTICS Clock Hold Time t H(CLK) 20 – – ns Data Setup Time t SU(D) 20 – – ns Data Hold Time t H(D) 20 – – ns Latch Setup Time t SU(LE) 20 – – ns Latch Hold Time t H(LE) 20 – – ns Output Enable Set Up Time t SU(OE) 40 – – ns Output Enable Falling to Outputs Turning ON Propagation Delay Time tP(OE)2 – 200 – ns Clock to Output Propagation Delay Time t P(OUT) VDS = 1.0 V, IO = 150 mA – 200 – ns Logic Output Fall Time t BF COB = 50 pF, 4.5 to 0.5 V – 50 100 ns Logic Output Rise Time t BR COB = 50 pF, 0.5 to 4.5 V – 30 60 ns Output Fall Time (Turn Off) t f CO = 10 pF, 90% to 10% of IO = 10 mA – 10 – ns CO = 10 pF, 90% to 10% of IO = 10 mA – 10 – ns Output Rise Time (Turn On) t r CO = 10 pF, 90% to 10% of IO = 10 mA – 50 – ns CO = 10 pF, 90% to 10% of IO = 10 mA – 100 – ns Clock Falling Edge to Serial Data Out Propagation Delay Time tP(SDO) – 50 100 ns Output Enable In to Output Enable Out Propagation Delay tP(OE) – 50 100 ns Latch In to Latch Out Propagation Delay t P(LE) – 50 100 ns Clock In to Clock Out Propagation Delay t P(CLK) – 50 100 ns Clock Out Pulse Duration t w(CLK) 70 100 130 ns Maximum CLKIN Frequency f CLKIN – – 6 MHz *Err = [IO (min or max) – IO(av)] / IO(av).

Figure 2. Shift Register Timing Figure 3. PWM Counter and Output Timing

Figure 4. Functional Diagram Output Enable In (OEI) signal. data due to duty cycle skewing or signal degradation.

  • Clock In (CI) pin to Clock Out (CO) pin
  • Latch In (LI) pin to Latch Out (LO) pin
  • Output Enable In (OEI) pin to Output Enable Out (OEO) pin
  • Serial Data In (SDI) pin to Serial Data Out (SDO) pin

counter rolls over and begins a new count. edge of OEI, upon recovery from UVLO, or when powering up. CI frequency, the clock period would be 200 ns. remains latched on a rising OEI signal. bus and external voltage regulators. to the V REG pin as possible. Table 1. Clock Divider Configurations Figure 5. Output Current versus External Resistor, REXT

Refer to figure 6 for the bit configurations for the scalar registers. (i.e., displaying all 3 LEDs at 100% DC). supply voltage dropping below a minimum acceptable level. and latches will be set to zero. The voltage on the outputs should be kept in the range 1 to 3 V . *Allegro Test Bit (ATB). Reserved for Allegro internal testing. Always set to zero (0) in the application. Figure 6. Register Configuration

250 LEDs

Figure 7. Application Driving 3 RGB LEDs at 75 mA Peak Figure 8. Application Driving High Power LED at 450 mA

10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A Package, 16 Pin DIP .070 .045 1.78 1.14 .150 .115 3.81 2.92 .195 .115 4.95 2.92 .014 .008 0.36 0.20 .430 MAX 10.92 .015 MIN 0.38 .005 MIN 0.13 .280 .240 7.11 6.10 .775 .735 19.69 18.67 A B CSEATING PLANE .022 .014 .056 .03616X .010 [0.25] M C .100 .2.54 .300 .7.62 .210 MAX 5.33 A Preliminary dimensions, for reference only Dimensions in inches Metric dimensions (mm) in brackets, for reference only (reference JEDEC MS-001 BB) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area

11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2006 AllegroMicrosystems, Inc. 0.30 0.18 .012 .007 0.50 0.30 .020 .012 0.80 0.70 .031 .028 0.05 0.00 .002 .000 3.15 2.85 .124 .112 3.15 2.85 .124 .112 0.20 REF .008 A B CSEATING PLANEC0.08 [.003] 16X 16X 0.10 [.004] M C A B 0.05 [.002] M C 0.50 .020 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) Preliminary dimensions, for reference only (reference JEDEC MO-220WEED-4) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown C Reference land pattern layout (reference IPC7351 QFN50P300X300X80-17W4M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) A B 1.70 NOM .067 1.70 NOM .067 0.23 x 0.23 REF .009 x .009 1.70 NOM .067 1.70 NOM .067 0.30 NOM .012 12X 0.20 MIN .008 16X 0.20 MIN .008 0.50 NOM .0200.90 NOM .035 0.20 MIN .008 3.10 NOM .122 3.10 NOM .122 C