A6273KA

6273 ALLEGRO

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Data Sheet26180.120 8-BIT LATCHED DMOS POWER DRIVER The A6273KA and A6273KLW combine eight (positive-edge- triggered D-type) data latches and DMOS outputs for systems requiring relatively high load power. Driver applications include relays, sole- noids, and other medium-current or high-voltage peripheral power loads. The CMOS inputs and latches allow direct interfacing with microproces- sor-based systems. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. The DMOS output inverts the DATA input. All of the output drivers are disabled (the DMOS sink drivers turned OFF) with the CLEAR input low. The A6273KA/KLW DMOS open-drain outputs are capable of sinking up to 750 mA. Similar devices with reduced r DS(on) will be available as the A6A273. The A6273KA is furnished in a 20-pin dual in-line plastic package. The A6273KLW is furnished in a 20-lead wide-body, small-outline plastic package (SOIC) with gull-wing leads for surface-mount applica- tions. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85 °C.

FEATURES

I 50 V Minimum Output Clamp Voltage I 250 mA Output Current (all outputs simultaneously) I 1.3 Ω Typical rDS(on) I Low Power Consumption I Replacements for TPIC6273N and TPIC6273DW 6273 ADVANCE INFORMATION (Subject to change without notice) January 24, 2000 Note that the A6273KA (DIP) and the A6273KLW (SOIC) are electrically identical and share a com- mon terminal number assignment. IN V DD GROUND OUT8 OUT7 OUT6 Dwg. PP-015-2 OUT 1 OUT2 OUT3 OUT4 OUT5 10 11 CLEAR LOGIC SUPPLY STROBE IN 7 IN 6 IN 5IN 4 IN 3 IN 2 IN 1 LATCHES LATCHES Always order by complete part number: Part Number Package R θJA RθJC A6273KA 20-pin DIP 55 °C/W 25 °C/W A6273KLW 20-lead SOIC 70 °C/W 17 °C/W ABSOLUTE MAXIMUM RATINGS at TA = 25°C Output Drain Current, Single-Pulse Avalanche Energy, Input Voltage Range, Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, * Each output, all outputs on. † Pulse duration ≤ 100 µs, duty cycle ≤ 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges.

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Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2000, Allegro MicroSystems, Inc. LOGIC SYMBOL R 1D 4 Dw g. FP-046-1 1D3 1D8 1D9 1D12 1D13 1D18 1D1950 75 100 125 150 2.5 0.5 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 2.0 1.5 1.0 Dwg. GS-004A SUFFIX 'LW', R = 70 °C/W θJA SUFFIX 'A', R 55°C/W θJA FUNCTION TABLE Inputs CLEAR STROBE IN X OUTX LXX H HH L HL H HLX R L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State DMOS POWER DRIVER OUTPUTLOGIC INPUTS IN Dwg. EP-010-16 VDD Dwg. EP-063 OUT

www.allegromicro.com FUNCTIONAL BLOCK DIAGRAM GROUND Dwg. FP-016-2 CLEAR (ACTIVE LOW) VDD LOGIC SUPPLY OUT 1 D CLR OUT 2 D CLR OUT 3 D CLR OUT 4 D CLR OUT 5 D CLR OUT 6 D CLR OUT 7 D CLR OUT 8 D CLR 1IN 2IN 3IN 4IN 5IN 6IN 7IN 8IN STROBE

Worcester, Massachusetts 01615-0036 (508) 853-5000 Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Logic Supply Voltage V DD Operating 4.5 5.0 5.5 V Output Breakdown V (BR)DSX IO = 1 mA 50 — — V Voltage Off-State Output I DSX VO = 40 V — 0.05 1.0 µA Current VO = 40 V TA = 125°C — 0.15 5.0 µA Static Drain-Source rDS(on) IO = 250 mA, VDD = 4.5 V — 1.3 2.0 Ω On-State Resistance IO = 250 mA, VDD = 4.5 V, TA = 125°C— 2 . 0 3 . 2 Ω IO = 500 mA, VDD = 4.5 V (see note) — 1.3 2.0 Ω Nominal Output I O(nom) VDS(on) = 0.5 V, TA = 85°C — 250 — mA Current Logic Input Current I IH VI = VDD = 5.5 V — — 1.0 µA IIL VI = 0, VDD = 5.5 V — — -1.0 µA Prop. Delay Time t PLH IO = 250 mA, CL = 30 pF — 625 — ns tPHL IO = 250 mA, CL = 30 pF — 150 — ns Output Rise Time t r IO = 250 mA, CL = 30 pF — 675 — ns Output Fall Time t f IO = 250 mA, CL = 30 pF — 400 — ns Supply Current I DD(off) VDD = 5.5 V, Outputs OFF — 15 100 µA IDD(on) VDD = 5.5 V, Outputs ON — 150 300 µA Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%. ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise specified). RECOMMENDED OPERATING CONDITIONS over operating temperature range

www.allegromicro.com TIMING REQUIREMENTS PHLt 90% ft 50% su(D)t PLHt 50% OUTPUTx Dwg. WP-036-1 10% rt INx STROBE h(D)t 50% su(D)t h(D)t Input Active Time Before Strobe Input Active Time After Strobe

Worcester, Massachusetts 01615-0036 (508) 853-5000 TEST CIRCUITS Dwg. EP-066-1 OUT INPUT IO VO tav IAS = 1.0 A V(BR)DSX VO(ON) 0.11 Ω100 mH +15 V DUT Single-Pulse Avalanche Energy Test Circuit and Waveforms EAS = IAS x V(BR)DSX x tAV/2

www.allegromicro.com TERMINAL DESCRIPTIONS Terminal No. Terminal Name Function 1 CLEAR When (active) LOW, all latches are reset and all outputs go HIGH (turn OFF). 2 IN1 CMOS data input to a latch. When strobed, the output then inverts the data input (IN1 = HIGH, OUT1 = LOW). 3 IN2 CMOS data input to a latch. When strobed, the output then inverts the data input (IN2 = HIGH, OUT2 = LOW). 4 OUT 1 Current-sinking, open-drain DMOS output. 5 OUT 2 Current-sinking, open-drain DMOS output. 6 OUT 3 Current-sinking, open-drain DMOS output. 7 OUT 4 Current-sinking, open-drain DMOS output. 8 IN3 CMOS data input to a latch. When strobed, the output then inverts the data input (IN3 = HIGH, OUT3 = LOW). 9 IN4 CMOS data input to a latch. When strobed, the output then inverts the data input (IN4 = HIGH, OUT4 = LOW). 10 GROUND Reference terminal for all voltage measurements. 11 STROBE A CMOS dynamic input to all latches. Data on each IN x terminal is loaded into its associated latch on a low-to-high STROBE transition. 12 IN5 CMOS data input to a latch. When strobed, the output then inverts the data input (IN5 = HIGH, OUT5 = LOW). 13 IN6 CMOS data input to a latch. When strobed, the output then inverts the data input (IN6 = HIGH, OUT6 = LOW). 14 OUT 5 Current-sinking, open-drain DMOS output. 15 OUT 6 Current-sinking, open-drain DMOS output. 16 OUT 7 Current-sinking, open-drain DMOS output. 17 OUT 8 Current-sinking, open-drain DMOS output. 18 IN7 CMOS data input to a latch. When strobed, the output then inverts the data input (IN7 = HIGH, OUT7 = LOW). 19 IN8 CMOS data input to a latch. When strobed, the output then inverts the data input (IN8 = HIGH, OUT8 = LOW). 20 LOGIC SUPPLY (V DD) The logic supply voltage (typically 5 V).

Worcester, Massachusetts 01615-0036 (508) 853-5000 A6273KA Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 0.355 0.204 7.62 BSC Dwg. MA-001-20 mm 10.92 MAX 1 10 7.11 6.10 5.33 MAX 1.77 1.15 0.39 MIN 0.558 0.356 2.54 BSC 0.13 MIN 3.81 2.93 26.92 24.89 0.014 0.008 0.300 BSC Dwg. MA-001-20 in 0.430 MAX 1 10 0.280 0.240 0.210 MAX 0.070 0.045 0.015 MIN 0.022 0.014 0.100 BSC 0.005 MIN 0.150 0.115 1.060 0.980

www.allegromicro.com A6273KLW Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) 0° TO 8° 1 2 30.020 0.013 0.0040 MIN. 0.0125 0.0091 0.050 0.016 Dwg. MA-008-20 in 0.050 BSC 20 11 0.2992 0.2914 0.419 0.394 0.5118 0.4961 0.0926 0.1043 0° TO 8° 2 30.51 0.33 0.10 MIN. Dwg. MA-008-20 mm 1.27 BSC 0.32 0.23 1.27 0.40 7.60 7.40 10.65 10.00 13.00 12.60 2.65 2.35 NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative.

Worcester, Massachusetts 01615-0036 (508) 853-5000 The products described here are manufactured under one or more Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.