A6271-1

A6271-1 ALLEGRO

Document overview

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Technical content

The A6271-1 is a DC-DC converter controller, providing a programmable constant-current output for driving high-power LEDs in series. The controller is based on a programmable fixed-frequency, peak current-mode control architecture. The DC-DC converter can be configured in a myriad of different switching configurations including boost, buck-boost, buck (ground-referenced switch), and SEPIC. The A6271-1 provides a cost-effective solution using an external logic-level MOSFET and minimum additional external components. The maximum LED current is set with a single external sense resistor and can be accurately modulated using a current reference input (analog control). External PWM dimming is possible via the PWMIN input, which also provides a shutdown mode. As an alternative, an internal PWM dimming circuit can be used by programming the PWMIN and DR pins. Either PWM scheme controls the PWMOUT output which drives an external p-channel MOSFET connected in series with the LED string. This MOSFET is also used to isolate the load during certain fault conditions, including output shorts to ground. A6271-1-DS, Rev. 3 MCO-0000277

• Automotive AEC-Q100 qualified
• Constant-current LED drive
• 4.2 to 50 V supply
• 53.3 V maximum LED string voltage
• Boost, buck-boost, buck, and SEPIC switching converters
• Programmable switching frequency 70 to 700 kHz
• PWM-controlled PMOS driver allows accurate LED current control at low duty cycles
• Dimming via external PWM, internal PWM and/or analog dimming
• Frequency dither scheme for effective spread spectrum to reduce EMI
• Comprehensive fault protection and fault flag Automotive, High-Current LED Controller PACKAGE: Not to scale A6271-1 FEATURES AND BENEFITS DESCRIPTION 16-Pin eTSSOP (LP) with Exposed Thermal Pad Continued on next page...

APPLICATIONS

• Automotive high-power LED lighting systems
• Fog lights, reversing lights, daytime running lights, position lights, headlights Figure 1 : Boost Switcher Driving 14 LEDs at 150 mA A6271-1 VBAT 4.7 µF 4.7 µF 4.4 µF 1 µF 22 nF 22 pF 47 nF 680 nF L1 56 µH 1.35 Ω 2.7 kΩ 1.3 kΩ 4.3 k Ω 73.2 kΩ 220 kΩ R11 240 kΩ R10 75 mΩ 39 Ω 150 Ω 12 Ω VREG GND FA ULT n DR PWMIN IREF OSC DITH COMP SP SG OVUV VINL PL N PWMOUT GND LED1 LED14 PWM Control July 9, 2018

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ABSOLUTE MAXIMUM RATINGS [2] Characteristic Symbol Notes Rating Unit VIN VIN –0.3 to 55 V PWMOUT, LP, LN, OVUV –0.3 to 58 V OSC, DITH, COMP, FAULTn, SG, SP, IREF, PWMIN, DR, VREG –0.3 to 6.5 V LP VLP With respect to LN –0.5 to 0.5 V Maximum Continuous Junction Temperature T J(max) 150 °C Storage Temperature Range Tstg –55 to 150 °C [2] With respect to GND. THERMAL CHARACTERISTICS Characteristic Symbol Test Conditions [3] Value Unit eTSSOP Package RθJA 4-layer PCB based on JEDEC standard JESD51-7 34 °C/W 2-layer PCB with 3.8in2 of copper area each side 43 °C/W RθJC Junction to thermal pad 2 °C/W [3] Additional thermal information available on the Allegro website. SELECTION GUIDE Part Number Packing [1] Package A6271KLPTR-T-1 4000 pieces per 13-in. reel 16-pin eTSSOP with exposed thermal pad [1] Contact Allegro™ for additional packing options. The A6271-1 has been carefully designed to minimize electromagnetic emissions through distributed decoupling and an externally programmable frequency dither circuit configured for the EMI specification CISPR 25. It is also possible to program the fundamental switching frequency below 150 kHz where most EMI standards begin. The A6271-1 has a comprehensive set of integrated protection features to protect the IC, the LED driver system, and the LED string against faults. Fixed-output overvoltage protection ensures no maximum voltage rating violations, even under a single point failure of the programmable-output overvoltage protection circuit. Other protection features include: LED overload (boost), output undervoltage (buck or buck-boost), input supply (VIN) undervoltage,

5 V regulator (VREG) output undervoltage, high-side supply (PWM

PMOS) undervoltage, and thermal protection. DESCRIPTION (continued)

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Table of Contents Appendix A: Special Notes on A6271-1 Operating

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Package LP, 16-Pin eTSSOP Pinout Diagram Terminal List Table Symbol Number Function COMP 1 Compensation pin for output of GM error amplifier. IREF 2 Analog dimming input. With a capacitor connected to this pin, provides a soft-start period when coming out of sleep mode. FAULTn 3 Open drain. Logic low indicates detection of a fault. Faults include: LED overload (boost), output undervoltage (buck or buck-boost), output overvoltage, programmable overvoltage, input supply (VIN) undervoltage, 5 V Regulator (VREG) output undervoltage. OSC 4 Oscillator input for setting switching frequency and for external synchronization. DITH 5 Dither frequency range set. Connect resistor from this pin to GND. Connect to VREG if not used. DR 6 A voltage applied to this pin programs the duty cycle of PWM internal mode. PWMIN 7 Used for either putting the device into sleep mode or analog dimming control. Can also be used for external or internal PWM control. VREG 8 5 V regulator output. Connect filter capacitor from VREG to GND. SG 9 Switch gate drive output. SP 10 Switch current sense and slope compensation. GND 11 Ground. OVUV 12 Programmable-output overvoltage and undervoltage protection input. PWMOUT 13 PWM gate drive for external p-channel MOSFET (active low). LN 14 LED current sense -ve. LP 15 LED current sense +ve. VIN 16 Main supply. PAD – Exposed pad provides both electrical contact to the ground and good thermal contact to the PCB. This pad must be soldered to the ground plane preferably by multiple through-hole vias. PAD 161COMP VIN 152IREF LP 143FAULTn LN 134OSC PWMOUT 125DITH OVUV 116DR GND 107PWMIN SP 98VREG SG PINOUT DIAGRAM AND TERMINAL LIST TABLE

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Figure 2: Functional Block Diagram VBAT Internal PWM Dimming Enable VIN OVUV PWMOUT LN LP RSL VREG VREG CB AACACD CF CE AB FAULTn SG SP GND RSLOPE RSS AC DITHOSCCOMP DR PWMIN IREF CG PWM 5 V Linear Reg Internal Linear Reg Analog DIM/ Soft Start Internal PWM Generator Osc Dither R Q S Fault Block Output OV–8 V wrt LP PWM Output UV Prog Output OV Overload VIN UVLO VREG UVLO Prog Output OV Output OV Thermal A6271-1 External Sync Internal PWM Duty Cycle External PWM Dimming External Analog Dimming

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Characteristics Symbol Test Conditions Min. Typ. Max. Unit SUPPLY and REFERENCE VIN Functional Operating Range [2] VIN VIN undervoltage turn off plus VIN undervoltage hysteresis cleared; PWMOUT undervoltage turn- on cleared 4.2 – 50 V VIN Quiescent Current IINQ SG Open Circuit – 3.5 5 mA IINS PWMIN = GND > disable time – 6 20 µA VREG Output Voltage VREG IREG = 0 to 2 mA, VIN ≥ 5.3 V 4.85 5.04 5.15 V IREG = 2 mA, VIN = 5 V 4.65 – – V VREG Output Voltage [3] VREG IREG = 2 mA, VIN = 9 to 45 V, TJ = –40°C to 125°C 4.95 5.05 5.15 V VREG Current Limit IREGCL 70 – – mA GATE OUTPUT DRIVE Turn-On Time tr CLOAD = 1 nF, 20% to 80% – 30 – ns Turn-Off Time tf CLOAD = 1 nF, 80% to 20% – 30 – ns Minimum Off-Time toff(MIN) – 135 165 ns Pull-Up On-Resistance RDS(on)UP TJ = 25°C, IGHx = –100 mA – 1.7 – Ω TJ = 150°C, IGHx = –100 mA – – 3.6 Ω Pull-Down On-Resistance RDS(on)DN TJ = 25°C, IGLx = 100 mA – 0.75 – Ω TJ = 150°C, IGLx = 100 mA – – 2 Ω Output High Voltage VSGH ISG = –100 µA VREG – 0.1 – VREG V Output Low Voltage VSGL ISG = 100 µA – – 0.1 V LOGIC INPUTS AND OUTPUTS FAULTn Output (Open Drain) VOL IOL = 1 mA, fault asserted – – 0.4 V FAULTn Output Leakage Current [1] IOH VO = 5.5 V, fault not asserted –1 – 1 µA PWMIN Low Voltage VPWMINL – – 0.3 V PWMIN High Voltage VPWMINH 2 – – V Input Hysteresis VIhys 150 180 – mV PWMIN Sleep Pull-Up Current [1] IPWMSLEEP – –1.5 – µA OSCILLATOR Oscillator Frequency fOSC ROSC = 51 kΩ – 500 – kHz ROSC = 73.4 kΩ 315 350 385 kHz Oscillator Frequency Range [3] fOSC 70 – 700 kHz OSC Input Low Voltage VOIL – – 0.8 V OSC Input High Voltage VOIH 2 – – V OSC Watchdog Period tOSWD Between successive rising edges 17 – – µs Continued on the next page… ELECTRICAL CHARACTERISTICS: Valid at TJ = –40°C to 150°C, VIN = 5 to 45 V, unless noted otherwise

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Characteristics Symbol Test Conditions Min. Typ. Max. Unit LED CURRENT SENSE Input Bias Current LN ILN VLP = VLN = 12 V – 5 – µA Input Bias Current LP ILP VLP = VLN = 12 V – 200 – µA Differential Sense Voltage VIDL PWMIN = high, VIDL = VLP – VLN, IREF > 1.2 V 200 204 208 mV Input Common-Mode Range VCMLH VLP = VLN 5 – 53.3 V ANALOG DIMMING Disable Time tDISAN PWMIN = low 24.8 29 35 ms Differential Sense Voltage VIDL VIREF = 0.5 V – 102 – mV VIREF = 0.25 V 47 51 55 mV IREF Maximum Voltage VIREFMAX Corresponds to sense voltage = 200 mV – 1 – V IREF Minimum Voltage VIREFMIN Corresponds to sense voltage = 0 mV – 0 – V PWM DIMMING: INTERNAL AND EXTERNAL PWMIN to LED Turn-On Time tDIMON CL = 2 nF between PWMOUT and LN – 270 – ns PWMIN to LED Turn-Off Time tDIMOFF CL = 2 nF between PWMOUT and LN – 210 – ns PWMOUT Low Voltage VPWMLO LED on, PWMOUT wrt LP, VIN = 10 V –9 – –6.5 V Peak Pull-Up Current [1] IPULLUP PWMIN = low, PWMOUT wrt LP = 0 V – –25 – mA Peak Pull-Down Current IPULLDOWN PWMIN = high, PWMOUT wrt LP = –8 V – 50 – mA PWM DIMMING: EXTERNAL Disable Time tDISEPWM PWMIN = low 24.8 29 35 ms PWM DIMMING: INTERNAL Maximum PWM Dimming Frequency fPWM – 1000 – Hz Minimum PWM Dimming Frequency fPWM – 200 – Hz PWM Dimming Frequency fPWM 70 kΩ between PWMIN and GND 180 200 220 Hz PWM Duty Cycle DPWM90 VDR = 3.24 V, fPWM = 200 Hz TJ = 25°C 87 90 93 % DPWM5 VDR = 180 mV, fPWM = 200 Hz TJ = 25°C 4.5 5 5.5 % TJ = 150°C – 5 – % DPWM0 VDR = 0 V, fPWM = 200 Hz TJ = 25°C – 0.3 – % VDRDCMAX Minimum voltage on DR for 100% duty cycle – 3.6 – V Disable Time tDISIPWM PWMIN = low 12.4 14.5 17.5 ms SOFT-START Startup Ramp Up Source Current [1] ISOURCE Coming out of sleep mode – –1 – µA Ramp Up Threshold VRAMPUP Voltage at IREF pin for 100% LED current – 1 – V Ramp Down Threshold VRAMPDOWN Voltage at IREF pin for 10% LED current – 100 – mV SWITCH CURRENT SENSE AND AMPLIFIER Input Bias Current [1] IBIASS VSP = 300 mV, RSLOPE = 1.5 kΩ –20 – – µA Switch Current Overload Threshold Voltage [3] VIDS 370 400 440 mV Voltage Gain ACS – 2.25 – V/V ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VIN = 5 to 45 V, unless noted otherwise Continued on the next page…

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ELECTRICAL CHARACTERISTICS (continued): Valid at TJ = –40°C to 150°C, VIN = 5 to 45 V, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit SLOPE COMPENSATION Peak Current [1] ISLOPE Sawtooth current waveform added to current- sense input (SP) –116 – –93 µA GM AMPLIFIER Open Loop DC Gain AVEA – 62 – dB Transconductance gmCOMP 1100 1500 1900 µA/V COMP Sink Current [1] ICOMP – 290 – µA COMP Source Current [1] ICOMP – –105 – µA COMP Leakage Current [1] ILCOMP – ±200 – nA DITHER GENERATOR Dither Modulation Frequency fDITH 7.9 9.6 11.2 kHz Maximum Switching Frequency fOSCMAX ROSC = 72 kΩ, RDITH = 110 kΩ 348 400 452 kHz Minimum Switching Frequency fOSCMIN ROSC = 72 kΩ, RDITH = 110 kΩ 261 300 339 kHz PROTECTION FEATURES Fault Blank Timer [4] tFB Startup – 3 – ms VIN Undervoltage Turn-Off VINUV Decreasing VIN , IREG = 2 mA 3.9 – 4.2 V VIN Undervoltage Hysteresis DVINUV 250 – 380 mV VREG Undervoltage Turn-Off VREGUV Decreasing VREG 3.25 – 3.5 V VREG Undervoltage Hysteresis DVREGUV – 300 – mV LED Overcurrent Threshold VOCLED LP wrt LN 260 320 380 mV Fixed-Output Overvoltage Threshold VFOOV Monitored at LP pin with respect to GND 53.3 55.5 57 V Programmable-Output Overvoltage Threshold VPOOV OVUV wrt LP –1.24 –1.1 –1 V Output Undervoltage Threshold VOUV OVUV wrt LP –110 –85 –60 mV Switch Current Overload Period tSCOP Inner loop switch current – 64 – clock cycles LED Overcurrent Period tOPI – 2 – clock cycles LED Output Undervoltage Period tOPV – 30 – clock cycles Hiccup Shutdown Period tHIC LED overcurrent, or output undervoltage, or overvoltage, or switch overload 22 26.5 31.75 ms PWMOUT Undervoltage Turn-On V PWMUVON Measured at LP wrt GND – – 6 V PWMOUT Undervoltage Turn-Off VPWMUVOFF Measured at LP wrt GND 3.7 – 5.8 V Overtemperature Shutdown Threshold TJF Temperature increasing 155 170 – °C Overtemperature Hysteresis DTJ Recovery = TJF – DTJ – 20 – °C [1] For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. [2] Function is correct, but some parameters may not meet specification. [3] Parameters guaranteed by design and characterization. [4] Fault blank timer only enabled for either output undervoltage or switch current overload.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com FUNCTIONAL DESCRIPTION The A6271-1 is a DC-DC converter controller designed to drive series-connected high-power LEDs in automotive applica- tions. The A6271-1 can be configured in a variety of switch- ing topologies, including: boost, buck-boost, SEPIC, and buck (ground-referenced switch). For each switching configuration, the appropriate loop compensation (COMP) and slope compensation (SLOPE) passive components are selected for optimal perfor- mance. The A6271-1 integrates all the necessary control elements to provide a cost-effective solution using an external logic-level, n-channel MOSFET (switching device), p-channel MOSFET (PWM device), and minimum additional external passive com- ponents. The maximum LED current is set with a single external sense resistor and can be accurately modulated using a current reference input (analog control). Direct PWM control is possible via the PWMIN input, which also provides a shutdown mode. Circuit Operation CONVERTER The controller is based on a fixed-frequency, peak current-mode control architecture. There are two loops within the controller. The inner loop, formed by the amplifier AC (refer to Functional Block Diagram), the slope generator, the comparator, CF, and the RS bistable, controls the inductor current as measured through the switching MOSFET by the sense resistor R SS. The outer loop, formed by the amplifier AA and the integrating GM amplifier AB, controls the average LED current by providing the current demand signal for the inner loop. The LED current is measured by the sense resistor, R SL, and is averaged and amplified to a level where it is compared to the internal reference current to produce an error signal at the output of the GM amplifier, AB. This error signal is effectively the cur- rent demand signal and determines the amount of energy trans- ferred to the LEDs on a cycle-by-cycle basis via the inner loop. The control loops work together as follows: at the beginning of each oscillator cycle, the bistable is set and the switching MOSFET is on. The switch current builds up due to the volt- age developed across the inductor, and when the corresponding signal produced at the output of amplifier AC reaches the current demand level on the output of amplifier AB, the bistable is reset and the switching MOSFET is turned off. The cycle is repeated on the next oscillator cycle. If the current through the LEDs increases, the output of AA increases, causing the current demand signal to decrease. This reduces the amount of energy transferred to the LED load by ter- minating the switch current sooner and reducing the LED current. EXTERNAL PULSE-WIDTH MODULATION DIMMING An external logic signal can be applied to PWMIN pin to control the on/off of LED current. Average brightness of the LED is directly proportional to the duty cycle of the control signal. This technique is commonly known as PWM dimming. During PWM operation, when PWMIN is pulled low, the LED stack PWMOUT is pulled high with respect to LP, turning off the external p-channel MOSFET, isolating the LED string. In addition, the GM output (amplifier AB) is ‘parked’ (COMP com- ponents disconnected) at the new level and the gate drive (SG) is disabled. As the output capacitance is isolated from the LED string, there is no loss of charge. When PWMIN goes high impedance, or is pulled high, the COMP components are reconnected (with the previous ‘parked’ value’), the gate drive (SG) is enabled, PWMOUT is pulled to around –8 V with respect to LP turning on the external MOSFET and allowing current to flow through the LED string. INTERNAL PULSE-WIDTH MODULATION DIMMING Where an external PWM signal is not available, the internal PWM generator can be used for controlling the LED brightness. A resistor connected between the PWMIN pin and GND sets the PWM frequency according to the following formula: R=FREQ 14,000 fPWM where RFREQ is in kΩ and fPWM is in Hz. The duty cycle is controlled by applying a voltage to the DR pin. The VREG can be used for the supply voltage and a potential divider can be used to set the DR voltage. An additional resistor can be added in parallel via a MOSFET switch between DR and GND to change the duty cycle between two levels. The relationship between the DR voltage and the duty cycle is as follows: PWM Duty cycle (%) = 27.81 × DR voltage So, for example, with a DR voltage = 1.8 V , the programmed duty cycle = 50%. In terms of the control of the external MOSFET via the PWM-

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com OUT pin, the control is identical as the external PWM scheme. If no internal PWM is required, the DR pin should be connected to VREG. Also note that whenever an external PWM signal is applied to the PWMIN pin, it overrides the internal PWM operation. When using the internal PWM scheme, an n-channel MOSFET is required to open the ground connection of the resistor connected between PWMIN and GND to ensure that startup occurs. The gate of the MOSFET is connected to VREG as shown in Figure 11 and Figure 13, or to an external control signal as shown in Fig- ure 12 and Figure 14. As the PWMIN input has a pull-up of only 1.1 µA in sleep mode, it is essential that the zero gate voltage, drain current (leakage) of the MOSFET does not exceed this number at maximum ambient temperatures. ANALOG DIMMING The IREF pin can then be used for full analog control. The LED current can be linearly adjusted from zero to full (100%) LED current (I LED) by changing the IREF pin from 0 to ≥ 1 V . This feature is useful in applications where PWM control is either not required or not available and the LEDs require some dynamic correction for brightness adjustment. Analog dimming can be used along with either pulse-width- modulation technique, internal or external. This is useful for applications where some color correction is required along with brightness control. Soft-start can be provided via the analog dim signal when either coming out of sleep or hiccup mode. The internal 1 µA internal source current on the IREF node can be overridden by applying a ramp signal to IREF. The soft-start duration is controlled by the signal on IREF as it is ramped from 0 to 1 V . If no soft-start is required, the IREF pin should be connected to VREG. SOFT-START When the A6271-1 comes out of sleep mode, soft-start is required to bring the output voltage up in a controlled open-loop fashion. This minimizes the possibility of the control loop saturating dur- ing the startup phase and subsequent output voltage overshoot, which can induce high transient peak currents in the LED string prior to the loop being brought back into linear control. The soft-start period can be programmed by the selection of the appropriate capacitor between IREF pin and GND pin according to the following formula: Csoft = t× 1 × 10soft 1.2 where tsoft is the desired soft-start period. If analog dimming is applied, the equivalent current source from this circuit will add to the internal 1 µA source current on the IREF node. Generally speaking, when using analog dimming via VREG and a potential divider, no soft-start or negligible soft-start is provided as shown in the example below. References are taken from Figure 9 on page 23: 10 kΩ 20 kΩ VREG (5 V) 22 nF IREF Pin 1 µA Figure 3: Charging Of Soft-Start Cap During Power Up From the above diagram, VREG, R5, and R7 can be simplified using Norton’s Theorem. The equivalent resistance can be found: RT = 20 × 10 20 + 10= 6.67 kΩ The current source can be found: Isource= 5 RT = 750 µA RT 6.67 kΩ 22 nF IREF Pin 1 µA 750 µA Figure 4: Equivalent Circuit Of The Previous Diagram From the above schematic, it is clear that the 750 µA current source will dominate and almost no soft-start will be provided. In this particular case, the only option is to resize C6, or increase the values of R5 and R7, or both.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com LED CURRENT-SENSE RESISTOR The LED current is programmed by the LED sense resistor, RSL, according to: ILED= VIDL RSL where the loop typically regulates VIDL to 200 mV when in either internal or external PWM modes. The power loss of the resistor should be taken into account to ensure the correct package size is selected. The power loss of the LED current-sense resistor, RSL is: P = ILED2 × RSL It is advisable to insert a 150 Ω resistor in series with the LN pin, as shown below, to protect the internal ESD structures between LN and LP under certain fault conditions. The 150 Ω value is selected as a balance between limiting the fault current and mini- mizing the LED current error caused by the bias current flow- ing into the LN pin. A small cap (such as 47 nF) may be added between LP and LN pin. It helps to filter switching noises from current sense signal. 150 Ω A 6271-1 LP LN RSL 47 nF Figure 5: Recommended Current Sensing Network SLEEP MODE If PWMIN is held low for longer than the disable time, tDIS1 or tDIS2, then the A6271-1 will shut down and put the majority of the circuitry into a low-power sleep mode. When internal PWM dimming is used, the disable time, tDIS1, is 14.5 ms. When either external PWM dimming or analog dimming is used, the disable time, tDIS2 is 29 ms.

5 V REGULATOR, VREG

To provide a filtered output and to ensure the regulator is stable, a 1 µF ceramic capacitor is required to be connected between VREG and GND. The ceramic type should be a quality type such as X5R, X7R, or X8R. The 5 V regulator is sized for driving the external switching MOSFET. However, it can be used for functions that require minimal current, e.g. pulling up the FAULTn output and provid- ing a reference for the DR, the IREF pin, or both. To check the load that the MOSFET provides, it is necessary to check the total gate charge required for a 5 V drive. This can be derived from the gate charge, QG, versus gate drive voltage, VGS, from the MOSFET datasheet. Once the gate charge is found, the regulator load current can be determined: ILOAD = (QG × fSW )+ Iexternal where Iexternal is the additional circuitry added to the VREG output. The ILOAD should not exceed the VREG external current limit (IREGCL). 05 0 100 150 200 250 300 350 400 100 150 200 250 300 350 400 450 500 550 600 650 700 750 Oscillator Resistor Value, R( kΩ) OSC Oscillator Frequency, F (kHz) OSC Figure 6: ROSC Required for a Particular Oscillator Frequency

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com OSCILLATOR The main oscillator may be configured as a clock source or it may be driven by an external clock signal. The oscillator is designed to run between 70 and 700 kHz. When the oscillator is configured as a clock source, the frequency is programmed via an external resistor between OSC pin and GND pin. The appropriate resistor can be found: ROSC= 25,690 fOSC where ROSC is in kΩ and fOSC is in kHz. Figure 4 shows the resulting ROSC for various frequencies. When the OSC pin is driven by an external clock source, a num- ber of A6271-1s can be synchronized together. If the clock period is greater than or equal to 17 µs, a watchdog circuit causes the running frequency to default to the internal oscillator, which runs at 350 kHz. If the oscillator pin goes either open circuit or short circuits to GND, the running frequency defaults to 350 kHz. FREQUENCY DITHERING To assist in minimizing EMI emissions, the main oscillator can be dithered so that the energy is spread over a defined frequency band. The defined frequency band is effectively the minimum and maximum switching frequency selected. This frequency is varied above and below the selected oscillator frequency and is set via a resistor connected between Dither pin and GND pin. The frequency band can be selected as follows: Δ f= ±22 × ROSC RDITH where Δf is a plus/minus percentage change with respect to the oscillator frequency. For example, if an oscillator frequency of 350 kHz and a dith- ered frequency band of ±50 kHz was selected, given a minimum switching frequency of 300 kHz and a maximum switching frequency of 400 kHz, the ROSC and RDITHER can be found: R=OSC R =OSC = 73.4 kΩ 72 k Ω, say 25,690 25,690 fOSC 350 Δf as a percentage of the delta with respect to the oscillator fre- quency is (50 / 350) × 100% = 14.3%. Therefore, RDITH can be found from: = 110 k72 14.3 f= ±22 × ROSC RDITH RDITH = 22 × The switching frequency is modulated at a rate of 10 kHz via a triangular waveform. This means in one modulation cycle, the switching frequency varies linearly from a minimum to a maxi- mum to a minimum again. If the dither feature is not required, the DITH pin should be tied to VREG. PROTECTION The A6271-1 includes a number of safety features to ensure the controller, the external power components, and the LED string are protected. The Fault Flag becomes active (pulled low) for any fault. When the device recovers from a fault, a soft-start is performed unless analog dimming is selected and the DR pin is tied to VREG. After the LED current has returned to regulation for 1 ms, the FAULT pin is then released. This allows the FAULT flag to be used as a ‘Power Good’ signal. Note: If IREF pin is held below 0.1 V (corresponding to <10% analog dimming) at startup, the IC cannot reliably determine whether LED current has reached regulation. Therefore FAULT flag may remain low even though LED current is being regulated. FAULT Fault occurred (e.g. LED overcurrent) Retry LED current back in regulation 1 msSoft StartCooldown Timer (26.5 ms) Figure 7: Fault Recovery

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com At initial startup, when coming out of sleep mode, or when the hiccup period terminates, a fault blank period, tFB, of 3 ms is applied for two fault conditions: low-side switch current limit (inner loop), and LED overload (caused by an undervoltage), before the fault circuitry becomes active. This period allows steady-state conditions to occur before fault monitoring takes place. Output Overvoltage Protection Two overvoltage protection circuits exist: an internal fixed circuit and an externally programmable circuit. In the majority of applications, the externally programmable circuit will provide the protection. The internal circuit is present in the event that the external feedback resistor chain of the programmable circuit goes open circuit. This feature is particularly desirable in systems that require high levels of reliability and the ability to withstand fail- ure modes. Another advantage is the possibility, in lower voltage applications, to select reduced operating voltages for the switch- ing MOSFET, PWM MOSFET, recirculation diode, and output filter capacitors with confidence. If an overvoltage occurs in either of the two circuits, the high- side MOSFET drive (PWMOUT) and the low-side MOSFET drive (SG) are immediately disabled and FAULTn is active. After one fault mask switching cycle, the hiccup timer, t HIC, is initiated for a period of 26.5 ms. At the beginning of the hiccup period, the IREF node (soft-start) capacitor is discharged immediately. After the hiccup period, an auto-restart is performed under control of the soft-start capacitor. A potential divider is set up between the LP node (output of the converter) and the cathode end of the LED stack. The output of the potential divider is monitored by a comparator referenced to the LP node. Once this voltage decreases below –1 V(max), an overvoltage condition is reported. It is recommended that the impedance of the potential divider is kept relatively high, especially in high-voltage LED strings, to minimize the current draw. It should be noted that there is negli- gible bias current drawn by the comparator monitor circuit. As an example, consider an LED string which has a maximum LED string voltage of 45 V and an output overvoltage (VLEDOV) is to be reported at a minimum of 15% above this value. R2 can be found: VOVUV R2= R1 OV OVUV× (VLED –V ) Assume resistor R1 is selected to be 4.3 kΩ. VLEDOV is 1.15 × 45 = 52 V . VOVUV is a minimum of 1 V . From the above formula: 1R 2= 4.3 × ( 52–1 )= 219 kΩ, select 220 kΩ Switcher Output OVUV VLEDOV Cathode: LED Stack VOVUV = 1 V LED1 LEDn Figure 8: Setting the OVUV Resistor Network

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Overload Protection There are two circuits: 1. LED overcurrent threshold 2. Output undervoltage threshold In the case of a LED overcurrent fault, the high-side MOSFET drive (PWMOUT) and the low-side MOSFET drive (SG) are disabled after two fault mask switching cycles, FAULTn is active, the IREF node (soft-start) capacitor is discharged, then the hiccup timer, t HIC, is initiated for a period of 26.5 ms. After the hiccup period, an auto-restart is performed under control of the soft-start capacitor. In the case of an output undervoltage fault, the high-side MOS- FET drive (PWMOUT) is immediately disabled and FAULTn is active. After thirty fault mask switching cycles, the low-side MOSFET drive (SG) is disabled, IREF node (soft-start) capacitor is discharged, and the hiccup timer, t HIC, is initiated for a period of 26.5 ms. After the hiccup period, an auto-restart is performed under control of the soft-start capacitor. Low-Side Switch Current Limit (inner loop) At startup, a 3 ms blank period is applied before the circuitry becomes active. Cycle-by-cycle current protection is provided through the low-side MOSFET. If an overcurrent occurs for longer than 64 switching clock cycles, the high-side MOSFET drive (PWMOUT) and the low-side MOSFET drive (SG) are disabled, FAULTn is active, and the hiccup timer, t HIC, is initiated for a period of 26.5 ms. During the hiccup period, the IREF node (soft-start) capacitor is discharged immediately. After the hiccup period, an auto-restart is performed under control of the soft-start capacitor. Input Undervoltage or VREG Undervoltage Protection If either condition occurs, the low-side MOSFET drive (SG) is disabled and FAULTn is active (assuming VREG is high enough, if FAULTn is pulled to VREG). In the case of the input undervoltage, the high-side MOSFET drive (PWMOUT) is also disabled. Both the input voltage and the VREG voltage must rise above their respective turn-on thresholds before a restart is possible. In the case of startup through the input voltage turn-on threshold, the system is brought up under control of the soft-start. In the case of startup through the VREG turn-on threshold, no soft-start is provided. PWM Output Undervoltage During startup, the output (LP node) must increase above 6 V to ensure the high-side MOSFET turns on. This is generally not a problem with switching topologies that can boost the output voltage with respect to the input voltage. In the case of the buck topology, the LN/LP node is referenced to VIN; therefore, the input voltage has to be equal to or greater than 6 V to guarantee a successful startup. In SEPIC, the output needs to be at least 6 V , while the input may be as low as 4.2 V . Overtemperature Shutdown If the chip exceeds the overtemperature shutdown threshold, the low-side MOSFET drive (SG) is immediately disabled, FAULTn is active, and the IREF node (soft-start) capacitor is discharged immediately. An auto-restart is performed under control of the soft-start capacitor once the temperature drops below the over- temperature minus the hysteresis level. The table on the following page summarizes the above faults along with other pin specific faults.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Table 1: Fault Table Fault Action Low-Side Switch Current Limit When fault occurs, cycle-by-cycle current limit operates. If fault >64 counts: low-side MOSFET (SG) and PWM MOSFET (PWMOUT) off and FAULTn active, hiccup period, then auto-restart with soft-start. Note: fault blanked for 3 ms during startup. LED Overcurrent Low-side MOSFET (SG) and PWM MOSFET (PWMOUT) immediately off and FAULTn active, hiccup period after 2 counts, then auto-restart with soft-start. Output Undervoltage PWM MOSFET (PWMOUT) immediately off. FAULTn active. Low-side MOSFET (SG) continues switching for 30 cycles. If fault still exist after 30 cycles, IC stops switching and enters hiccup period, then auto-restart with soft-start. Note: this undervoltage fault detection is blanked for 3 ms during startup. Fixed-Output Overvoltage Low-side MOSFET (SG) off and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active, hiccup period after 1 count, then auto-restart with soft-start. Programmable-Output Overvoltage Low-side MOSFET (SG) off and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active, hiccup period after 1 count, then auto-restart with soft-start. Input Undervoltage Low-side MOSFET (SG) and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active assuming there is sufficient drive to the flag. Once input voltage is above the VIN undervoltage threshold, plus hysteresis, auto-restart with soft-start occurs. VREG Undervoltage Low-side MOSFET (SG) immediately turns off and FAULTn active assuming there is sufficient drive to the flag. Once VREG voltage is above the VREG undervoltage threshold, plus hysteresis, then auto-restart. Thermal Shutdown Low-side MOSFET (SG) immediately turns off and FAULTn active. Auto-restart with soft start occurs after the temperature drops below the overtemperature minus hysteresis level. PWMOUT Undervoltage PWM MOSFET (PWMOUT) off immediately and FAULTn active. Low-side MOSFET (SG) continues switching to pump up output voltage. Once LP rises above V PWMUVON, PWMOUT is re-activated. OSC Pin Fault The oscillator will switch to default frequency of 350 kHz. COMP Short to GND Force regulator to minimum duty cycle.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com COMPONENT SELECTION Inductor The main factor in selecting the inductor value is to target a cer- tain ripple current to ensure the peak current-mode control works correctly. A reasonable figure is a peak-to-peak ripple current of around 15% of the average inductor current. The maximum inductor current occurs at minimum input voltage and maximum duty cycle. BOOST INDUCTOR SELECTION The maximum duty cycle can be found: V+ VLED f DMAX = VLED f IN(MIN)+ (V –V ) where VLED is the LED output voltage, Vf is the forward volt- age drop of the recirculation diode, and VIN(MIN) is the minimum input voltage. The maximum average inductor current can be determined: (1 –D MAX IAVE = ILED The ripple current, ΔI = 0.15 × IAVE . The minimum inductance can now be found: ΔI ×fSW L = (VLED fM AX+ V– V × (1–D )IN(MIN)) where fSW is the switching frequency. The peak current in the inductor is: ILPK AVE= I+ 2 ΔI BUCK-BOOST INDUCTOR SELECTION The maximum duty cycle can be found: DMAX = V+ V+ VLED f IN(MIN) V+ VLED f where VLED is the LED output voltage, Vf is the forward volt- age drop of the recirculation diode, and VIN(MIN) is the minimum input voltage. The maximum average inductor current can be determined: IAVE = 1–D MAX ILED The ripple current, ΔI = 0.15 × IAVE . The minimum inductance can now be found: L = ΔI × fSW VIN(MIN) MAX× D where fSW is the switching frequency. The peak current in the inductor is: ILPK AVE= I+ 2 ΔI When selecting an inductor from manufacturers’ datasheets, there are often two current ratings given: 1. Saturation current. This is the current level that causes the inductance to drop by between 10 and 40% depending on the manufacturer. The saturation current should be greater than the peak cur- rent, I LPK, with some margin to allow for overload condi- tions. 2. RMS or average current. This is the current level that deter- mines a certain temperature rise in the inductor with a given ambient temperature. This is normally presented as a single figure: operating temperature. The RMS or average inductor current rating should be greater than the estimated maximum average current, I AV E. Recommended inductor manufacturers:

• Coilcraft: MSS1278T or MSS1078T Range
• TDK: SLF12575 type H SWITCH CURRENT SENSE The switch current sense of the ‘inner loop’ is measured by the external sense resistor, R SS, and the switch sense amplifier, AC. As well as providing the peak current information to determine the duty cycle, it also provides pulse-by-pulse current limiting through the switching MOSFET and slope compensation to pre- vent subharmonic oscillations at duty cycles greater than 50%.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com The current limit of the inner loop is set by the input limit of the sense amplifier, VIDS, the maximum switch current that has been determined, and the effects of the slope compensation have to be taken into account. The operating duty cycle has to be calculated at maximum load and minimum operating input voltage. The amount of slope compensation can be calculated for this operat- ing point and can then be added to the actual current-sense signal to determine the maximum signal amplitude before cycle-by- cycle current limiting takes effect. Refer to Slope Compensation Section to find di L /dt then diSLOPE / dt. R =SS diSLOPE dt ×1.2× 0.32 I+LP ( ) DMAX FSW Note that the minimum value of VIDS is used with an additional 20% to allow for margin. ILP is the peak current in the inductor. The power loss of the switch current-sense resistor, RSS, can be found: Boost RSS Power Loss Using the DMAX and IAV E from the boost part of the inductor sec- tion, the power loss of RSS can be found: Ploss = IAVE2 × DMAX × RSS Buck-Boost RSS Power Loss Using the DMAX and IAV E from the buck-boost part of the induc- tor section, the power loss of RSS can be found: Ploss = IAVE2 × DMAX × RSS Resistor manufacturers typically derate the devices from an ambient temperature of around 70°C. The power rating including derating of the sense resistor should exceed the maximum power loss at maximum ambient temperature. SLOPE COMPENSATION Slope compensation can be added to the MOSFET current-sense signal on pin SP to prevent subharmonic oscillations where the peak-to-average control error becomes increasingly larger at duty cycles in excess of 50%. A current source is provided at the SP pin as a sawtooth from 0 to 100 µA. An external resistor, RSLOPE, connected between the SP pin and the source connection of the MOSFET, is used to program the appropriate voltage level to scale the slope compensation for correct use with the appropriate topology and set up conditions that have been adopted. Boost Slope Resistor The inductor down slope is: = L V+ V– VLED f IN(MIN)diL dt Buck-Boost Slope Resistor The inductor down slope is: = L V+ VLED fdiL dt The optimum down slope as illustrated by Ridley can be found from: = DMAX 0.18diSLOPE dt ×diL dt 1–() The slope compensation resistor can be found: R =SLOPE diSLOPE dt × RSS 100 × 10 × 1 × 10 × –6 –6 fSW where RSLOPE is in ohms (Ω). CONTROL LOOP COMPENSATION The recommended way of closing the control loop is to remove the influence of the right-hand plane zero (RHPZ) in both boost and buck-boost topologies. The reason for this is that the RHPZ increases the gain by 20 dB/decade and at the same time intro- duces a 90-degree phase lag. The minimum frequency that the RHPZ occurs at is: For boost mode: fRHPZ = V× (1–D )LED MAX 2 ×× L× I πLED For buck-boost mode: fRHPZ = V× (1–D )LED MAX 2 ×× L× I πLED MAX× D

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com It is recommended that the 0 dB crossover point is approxi- mately: fCROSS= fRHPZ With effective peak current-mode control, it can be assumed that the second power pole is pushed high enough in the frequency domain to have no influence on the overall loop response. It is reasonable to assume the overall loop response is effectively a single pole set by the GM amplifier (COMP node). The error amp zero is set at the same frequency as the output power pole to ensure the loop is closed at a rate of 20 dB/decade. The open-loop DC gain of the system can be found: Boost: VLED ILED DC Gain = R×SS VLED ILED + (n × R) + R)dyn SL() Buck-Boost: VLED ILED DC Gain = R×SS VLED ILED + D× ((n × R) + R)MAX dyn SL() where n = number of LEDs and Rdyn = LED dynamic resistance. Note that the LED dynamic resistance may be given in the LED datasheet. If it is not, it can be derived by a simple measurement. Set up a power supply with a current limit at the operating point LED1). Apply the current to an individual LED and measure the voltage drop (VLED1). Change the current limit by a small amount, say 5% (ILED2), and measure the voltage drop (VLED2). The dynamic resistance can be estimated: Rdyn = V– VLED1 LED2 I– ILED1 LED2 The RC constant required to achieve 0 dB with a slope of 20 dB/ decade at the crossover frequency, fCROSS: RC = 2 ×× fπ CROS S The frequency of the first GM amplifier pole can be found: fp1 = 1 2 × × RC × DC Gainπ Capacitor on the output of the GM amplifier (COMP node) required to achieve the above pole position: C comp = 750 × 10 2 ×× f × 1,258π p1 The frequency position of the power stage pole and the GM amplifier zero is: Boost: fp2 z1and f= V+ I × ((n × R ) + R)LED LED dyn SL 2 × × VC × ((n × R) + R)π LED OUT dyn SL× Buck-Boost: fp2 z1and f= V+ D × I× ((n × R) + R)LED MAX LED dyn SL 2 × × VC × ((n × R) + R)π LED OUT dyn SL× The resistor (Rcomp) in series with the compensation capacitor (Ccomp) on the COMP node can be found: Rcomp = 1 2 ×× f C πp2 comp× LOW-SIDE SWITCHING MOSFET A logic-level n-channel MOSFET is used as the switch for the DC-DC converter. In the boost configuration, the maximum voltage across the drain-source connection is: VDS = VLED + Vf In the buck-boost configuration, the maximum voltage across the drain-source connection is: V DS = VLED + Vf + VINMAX The actual rating of the MOSFET selected should be greater than the maximum voltage plus some margin. It is recommended that the minimum margin should be no less than 20% of the maxi- mum voltage. In the case of buck-boost mode, the maximum rating should fac- tor in load-dump conditions.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com In terms of the current rating, the MOSFET is generally selected for a low RDS rating to minimize the power dissipation. This means the current rating is well in excess of the actual maximum current used in the application. The power loss in the MOSFET is determined by the static loss and the switching losses. Static Loss Using the D MAX and IAV E from the boost or buck-boost part of the inductor section, the power loss of RDS can be found: Ploss = IAVE2 × DMAX × RDS Note that the RDS figures are generally presented at 25°C room ambients. The actual RDS can be determined by considering the normalized RDS versus temperature graph. Another consideration of the static loss is cold-crank situations. It is important to ensure the gate-drive amplitude (derived from VREG) at the minimum input voltage provides sufficient drive that the R DS does not increase by much, therefore minimizing any increase in losses. A good quality logic-level MOSFET should have good R DS performance at drive voltages of less than 4 V . The VREG load can be determined by estimating the gate losses. From the MOSFET datasheet, the total gate charge can estimated with a gate drive of 5 V using the appropriate graph. In addition, any other circuitry that VREG is powering should also be fac- tored. The current drawn from VREG due to the MOSFET drive can be determined: VREG MOSFETload = QTOTALGate × fSW Switching Losses The switching losses in the MOSFET are determined by the length of time of the Miller region. To minimize conducted and radiated EMI emissions, this region is deliberately extended by adding series resistance between the gate drive (SG) and the gate of the device. It is assumed that the turn-off loss is similar to the turn-on loss. In the case of the boost converter, the switching loss: P switch = (VLED + Vf ) × IAVE × tmiller × fSW In the case of the buck boost converter, the switching loss: Pswitch = (VLED + Vf + VIN(MIN) ) × IAVE × tmiller × fSW RECIRCULATION DIODE The diode should have a low forward voltage to reduce conduc- tion losses and a low capacitance to reduce switching losses and minimize EMI. Schottky diodes can provide both features if carefully selected. The forward voltage drop is a natural advantage for Schottky diodes and reduces as the current rating increases. However, as the current rating increases, the diode capacitance also increases, so the optimum selection is usually the lowest current rating above the required maximum, in this case I LPK. In the boost configuration, the maximum reverse voltage across the diode is: V RRM = VLED + Vf In the buck-boost configuration, the maximum reverse voltage across the diode is: V RRM = VLED + Vf + VIN(MAX) The actual rating of the diode selected should be greater than the maximum voltage plus some margin. It is recommended that the minimum margin should be no less than 20% of the maximum voltage. In the case of buck-boost mode, the maximum rating should factor in load-dump conditions. HIGH-SIDE PWM MOSFET A p-channel MOSFET is used as the PWM switch for the LED stack. In both boost and buck-boost modes, the maximum voltage across the drain-source connection is V LED. The actual rating of the MOSFET selected should be greater than the maximum voltage plus some margin. It is recommended that the minimum margin should be no less than 20% of the maximum voltage. The power loss of this MOSFET is dominated by the static loss. The switching losses can largely be ignored as the PWM frequen- cies are relatively low. The power loss of the MOSFET R DS can be found: Ploss = ILED2 × RDS The gate drive for the PWM MOSFET is derived from the LED output rail (LP pin). In boost and buck-boost modes, this node is boosted with respect to the input voltage (VIN), so there should be sufficient negative gate drive.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com In other operating modes such as buck, where the output volt- age is less than the input voltage, it may be necessary to use low threshold p-channel MOSFETs to ensure adequate overdrive dur- ing cold-crank situations. OUTPUT CAPACITOR There are several points to consider when selecting the output capacitor. Due to the switching topology used, the ripple current for this circuit is high since the output capacitor provides the LED cur- rent when the DC-DC converter switch is active in both boost and buck-boost modes. The capacitor is then recharged each time the inductor passes energy to the output. The ripple current on the output capacitor will be equal to the peak inductor current. The corresponding output ripple can be derived from the amount of charge transferred to the output during the switch on time. To minimize heating effects and voltage ripple, the equivalent series resistance (ESR) and the equivalent series inductance (ESL) should be kept as low as possible. This can be achieved by mul- tilayer ceramic chip (MLCC) capacitors. To reduce performance variation over temperature, low drift types such as X7R and X5R should be used. The value of the output capacitor will typically be in the range of 3.3 to 10 µF, and it should be rated above the maximum LED stack voltage, VLED. There is an E-field effect with ceramic capacitors that causes the capacitance to fall at elevated voltages. It is therefore recommended that a good margin is selected to minimize this effect. One potential issue of ceramic capacitors is audible noise during pulse-width modulation (PWM). This is caused by the piezo- electric effect of the ceramic substrate. To minimize the effects of this, it is recommended to use multiple physically smaller capacitors. If this is still an issue, it is recommended that either low-impedance electrolytic or polymer capacitors be used. INPUT CAPACITOR The function of the input filter capacitor is to provide a low- impedance shunt path for the current drawn by the A6271-1 when the switching MOSFET turns on. The objective is to minimize the ripple current reflected back into the source supply. This approach helps to minimize conducted emissions into the power source. Additional line impedance in the form of chokes can be added to improve the emissions further. In a correctly designed system, with a quality capacitor or capaci- tors positioned adjacent to the power train circuitry, these capaci- tors should supply the ripple current. The amount of capacitance required at the input is dictated by the EMI performance. This is usually distributed with series ferrite beads and either differential-mode chokes, or common-mode chokes, or both. Layout The following layout guidelines should be followed to ensure satisfactory electrical and EMI performance. Ground planes should be used on as many layers as possible. This is essential in minimizing ‘ground bounce’ (differential voltage across the ground connection). ‘Ground bounce’ can lead to radi- ated noise which can then be picked up on both input and output connections and manifest as common-mode noise. Any ground planes on different layers should be connected using multiple vias in an attempt to minimize ground impedances. The ground tab under the A6271-1 should also have multiple vias connecting to the ground plane or planes. The drain connection of the switching MOSFET, PWM MOS- FET, and cathode terminal of the recirculation diode are used for thermal heatsinking. It is advised to use sufficient copper around these connections on the component layer of the PCB only. The areas directly under these connections on the PCB should form part of the ground plane. The reason for restricting the copper area on these nodes is because they can radiate noise due to the nature of the dv/dt and di/dt power signals that appear. The area of the switching power loops should be minimized as much as possible. In addition, the trace connections should be as wide as possible to minimize parasitic leakage inductances, but at the same time not compromising the power loop area. There are two power loops: Loop 1: formed by the input filter, main switching MOSFET, power inductor, and inner loop sense resistor. Loop 2: formed by the power inductor, recirculation diode, LED sense resistor, PWM MOSFET, and the output capacitor or capacitors. Where practical, keep input or output filter magnetics as far away from the power-switching inductor (L1) as possible. This is to avoid or at least minimize the effects of magnetic crosstalk.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com One of the major noise contributors is the switching MOSFET (M1). Slowing down the gate drive without compromising the thermal solution will help to minimize noise. To comply with CISPR 25, a common-mode choke is typically required as part of the input filter. Reducing EMI It is essential that good layout practice as defined in the Layout Section should be adopted. The following techniques are also recommended. SNUBBER Adding a low-loss R-C snubber network between the drain of the main switching MOSFET and ground helps to suppress the resonant ringing on the switching node. The process for selecting these components involves some ‘trial and error’ on the actual printed circuit board. Step 1: Measure the voltage resonance frequency on the LX node. Step 2: Add an additional capacitance between LX and ground until the resonant frequency is halved. Note that this capacitance should be around 1 nF. Step 3: Two equations with two unknowns are now obtained: FRES = 1 2 ××π L× Cleak leak =FRES 1 2 ××π L× Cleak new2 where Cnew = Cleak + Cadd. Cadd = additional capacitance added. Cleak = parasitic capacitance. Lleak = parasitic inductance. Now to halve the frequency, Cleak + Cadd = 4 x Cleak Cleak = Cadd 3Therefore, With Cleak solved, Lleak can also be solved. The characteristic impedance of the parasitic components can be found: RO = Lleak Cleak RO can be selected as the damping resistor. Typically, either an 0805 or 0603 resistor case size is adequate. INPUT FILTER The selection of the components that form the input filter depends on the noise that is present in the system in terms of the frequency and whether it is common mode or differential mode. In addition, the common automotive standards that exist define onerous specification limit lines for the emissions in the AM band (approximately 530 kHz to 1.7 MHz) and the FM band (approxi- mately 70 to 108 MHz). Some consideration must be given to these frequency bands to understand how to filter these regions. At the lower frequencies, below a few 10s of MHz, the noise is generally dominated by differential noise with some common mode noise. At frequencies above a few 10s of MHz, the noise is dominated by common mode noise with some differential noise. To address the differential noise, a differntial inductor can be used along with differential capacitance to form an L-C filter. One problem in using standard differential inductors is that the self-resonance frequency (SRF) is typically in the region of a few 10s of MHz, even with a modest few microhenries (µH) (note: the higher the inductance, the lower the SRF). This means that above the self-resonant frequency points, these components actu- ally amplify the noise and make matters worse. Some differential-mode inductive filtering is always necessary. Ferrite beads can be used for this function. Although ferrite beads are designed to act as a lossy resistor at particular frequency bands, they do have an inherent inductive element which can be in the region of several µH. The inductance of a ferrite bead can be extracted from the reactance information graph (refer to Fig- ure 7). At a particular frequency, the reactance can be found and then the inductance can be derived. As a single ferrite bead may not be effective enough, a two-stage ferrite bead filter approach can be taken. These components, along with input differential-mode capacitors, can form L-C filter stages. For the best result, the first L-C filter should be placed as close to the power stage as possible. At higher frequencies, the majority of the noise problems is associated with common-mode noise. This noise is induced by

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com ground-referenced differential noise radiating through the ground plane. This noise can be picked up on the input stage forming common-mode noise on the positive and negative power supply connections to the battery. Even with excellent layout, this noise is always present. To address this problem, a common-mode inductor is required. This inductor is selected to present a high impedance around the FM region. An example of a common-mode (CM) choke with a high impedance around the FM region is shown below in Figure 9. Another important consideration is the relative positioning of the common-mode choke with respect to the switching inductor. Magnetic crosstalk can occur between these components which can degrade the effectiveness of the CM choke. Even the use of a magnetically-screened switching inductor is not sufficient to avoid this problem. It is important to physically separate these two components as far as possible. Another advantage of a good physical separation is that any ‘ground bounce’ induced CM noise will couple onto the input power traces. The strength of the coupling will reduce with distance. The further the CM choke is away from the switching circuit, the more likely it will be to filter this noise. All filter capacitors should be a quality ceramic: X7R or X8R. FREQUENCY DITHERING Further improvements to the differential-mode performance can be made by the use of frequency dithering techniques. The A6271-1 contains a dither circuit which changes the switch- ing oscillator frequency on a cycle-by-cycle basis across a defined frequency band. As the noise in a switcher is typically narrow-band noise, both the peak and average signals are similar in amplitude. When a frequency dither scheme is introduced, it ‘spreads’ the noise, converting it from narrow band into broad band. While the peak noise reduces across the majority of the spectrum, the reduction in the average measurement is a lot more effective. This effect is particularly helpful in the conducted emissions for the average measurement between 76 and 108 MHz. This region is unusual, as typically the peak and average limit lines track one another, but in this area, while the peak limit line increases, the average limit line reduces (refer to Figure 10 below). Note the red limit lines are peak and the pink limit lines are average. The reason that the average limit line is relatively low (making it challenging to pass) is that average weighted signals have an adverse effect on FM radio signals. 1 10 100 1000 100 1000 10000 Frequency (MHz) Impedance (Ω) Z (comm) Z (diff) Figure 9: Common-Mode (CM) Choke Impedance -10 dBµV 150 kHz 1 MHz 10 MHz 108 MHz Limits 55025 P5 55025 A5 Tr ansducer UniRFPro Traces PK+ AV Figure 10: CISPR 25 Class 5 Limit Lines

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Minimizing the noise at the high end of the conducted emis- sion frequency spectrum also benefits the radiated noise at this frequency band and above. Note that a modulation frequency of 10 kHz was chosen, since this aligns with the resolution bandwidth of the measurement receiver as defined in CISPR 25. The resolution bandwidth is effectively the ‘measurement window’ at each measurement step. Another consideration when optimizing the frequency dithering is the depth of frequency. This is the maximum and minimum switching frequency that the converter operates, effectively the ‘spread range’. The wider the spread range is, the more effective the dithering is. However, there is a trade-off with switching losses and sizing of the power inductor in terms of inductance value and the corresponding physical size.

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com APPLICATION CIRCUITS A6271-1 VBAT 4.7 µF 4.7 µF C10 4.7 µF C11 4.7 µF C12 4.7 µF 1 µF 100 nF 22 nF 22 pFC7 470 nF 100 nF 47 nF L1 12 µH R13 470 mΩ R14 2.7 Ω 2.7 kΩ R17 1.2 kΩ R15 4.3 kΩ 270 kΩ 10 kΩ 68 kΩ 100 kΩ 220 kΩ R21 220 kΩ R18 10 kΩ R12 10 kΩ R19 68 mΩ R20 68 mΩ R10 39 Ω R11 150 Ω R16 0 Ω 10 kΩ 20 kΩ 10 kΩ VREG GND FA ULT n DR PWMIN IREF OSC DITH COMP SP SG OVUV VI NL PL N PWMOUT High = internal PWM ON (5% ) GND LED1 LED12 Analog Control Low = no PWM (100%) Figure 11: Boost Driving 12 LEDs at 500 mA, Switching Frequency 250 kHz Internal PWM (5%) and/or analog dimming, no soft-start, and frequency dither on. Reference Description Manufacturer/Part Number C1,C2,C10,C11,C12 4.7 µF, ceramic capacitor, X7R, 50 V TDK, MuRata C3,C4 100 nF, ceramic capacitor, X7R, 50 V C5 1 µF, ceramic capacitor, X7R, 16 V C6 22 nF, ceramic capacitor, X7R, 50 V C7 470 nF, ceramic capacitor, X7R, 50 V C8 22 pF, ceramic capacitor, X7R, 50 V C9 47 nF, ceramic capacitor, X7R, 16 V D1 200 mA, 40 V Schottky diode ST / BAT54 D2 10 A, 60 V Schottky diode Vishay / SS10P6 L1 22 µH, high current shielded construction Vishay / IHLP-5050FDER220M-5A M1,M2 N-channel signal MOSFET 2N7000 or equivalent M3 N-channel 50 A, 100 V MOSFET Vishay / SQD50N10 Table 2: Application Circuit 1 Bill of Materials Continued on next page...

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Reference Description Manufacturer/Part Number M4 P-channel 15 A, 100 V MOSFET Infineon / SPD15P10PL G Heatsink for M3 (TO-252) AAVID Thermalloy / 573100D00010G R1 2.7 kΩ, 1%, 0603 or 0805 R2 270 kΩ, 1%, 0603 or 0805 R3,R6,R12,R18 10 kΩ, 1%, 0603 or 0805 R4 68 kΩ, 1%, 0603 or 0805 R5 20 kΩ, 1%, 0603 or 0805 R7 10 kΩ, potentiometer R8 100 kΩ, 1%, 0603 or 0805 R9 220 kΩ, 1%, 0603 or 0805 R10 39 Ω, 1%, 0603 or 0805 R11 150 Ω, 1%, 0603 or 0805 R13 470 mΩ, 1%, 0805 or 1206 R14 2.7 Ω, 1%, 0603 or 0805 R15 4.3 kΩ, 1%, 0603 or 0805 R16 0 Ω, 0603 or 0805 R17 1.2 kΩ, 1%, 0603 or 0805 R19,R20 68 mΩ, 1%, 2010 R21 220 kΩ, 1%, 0603 or 0805 Table 2: Application Circuit 1 Bill of Materials (continued)

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A6271-1 VBAT 4.7 µF 4.7 µF C10 2.2 µF C11 2.2 µF C12 2.2 µF 1 µF 100 nF 22 nF 22 pFC7 680 nF 100 nF 47 nF L1 56 µH 2.7 Ω 2.7 Ω 2.7 kΩ R11 1.3 kΩ 4.3 kΩ 73.2 kΩ 220 kΩ R15 240 kΩ R12 10 kΩ R6 10 kΩ R13 150 mΩ R14 150 mΩ 39 Ω 150 Ω R10 12 Ω VREG GND FA ULT n DR PWMIN IREF OSC DITH COMP SP SG OVUV VI NL PL N PWMOUT External PWM Drive Signal GND LED1 LED14 Important Note: If PWMIN pin is left floating, LEDs will turn on at 100% duty cycle. Figure 12: Boost Driving 14 LEDs at 150 mA, Switching Frequency 350 kHz External PWM, no analog dimming, soft-start, and frequency dither on. Reference Description Manufacturer/Part Number C1,C2 4.7 µF, ceramic capacitor, X7R, 50 V TDK, MuRata C3,C4 100 nF, ceramic capacitor, X7R, 50 V C5 1 µF, ceramic capacitor, X7R, 16 V C6 22 nF, ceramic capacitor, X7R, 50 V C7 680 nF, ceramic capacitor, X7R, 50 V C8 22 pF, ceramic capacitor, X7R, 50 V C9 47 nF, ceramic capacitor, X7R, 16 V C10,C11,C12 2.2 µF, ceramic capacitor, X7R, 100 V TDK, MuRata D1 200 mA, 40 V Schottky diode ST / BAT54 D2 2 A, 100 V Schottky diode Vishay, ST / SS2H10 L1 56 µH, power inductor shielded construction Coilcraft / MSS1048T-563ML M1 N-channel, 30 A, 100 V MOSFET NXP / PSMN038-100YLX Table 3: Application Circuit 2 Bill of Materials Continued on next page...

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Reference Description Manufacturer/Part Number M2 P-channel 15 A, 100 V MOSFET Infineon / SPD15P10PL G R1 2.7 kΩ, 1%, 0603 or 0805 R2 73.2 kΩ, 1%, 0603 or 0805 R3 220 kΩ, 1%, 0603 or 0805 R4 39 Ω, 1%, 0603 or 0805 R5 150 Ω, 1%, 0603 or 0805 R6,R12 10 kΩ, 1%, 0603 or 0805 R7,R8 2.7 Ω, 1%, 0805 or 1206 R9 4.3 kΩ, 1%, 0603 or 0805 R10 12 Ω, 1%, 0603 or 0805 R11 1.3 kΩ, 1%, 0603 or 0805 R13,R14 150 mΩ, 1%, 1206 R15 240 kΩ, 1%, 0603 or 0805 Table 3: Application Circuit 2 Bill of Materials (continued)

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A6271-1 VBAT 4.7 µF 4.7 µF C10 4.7 µF C11 4.7 µF C12 4.7 µF 1 µF 100 nF 22 nF 22 pFC7 220 nF 100 nF 47 nF L1 12 µH R11 270 mΩ R12 270 mΩ 2.7 kΩ R15 1 kΩ R13 4.3 kΩ 270 kΩ 10 kΩ 68 kΩ 100 kΩ 220 kΩ R19 84.5 kΩ R16 10 kΩ R10 10 kΩ R17 62 mΩ R18 62 mΩ 39 Ω 150 Ω R14 0 Ω VREG GND FA ULT n DR PWMIN IREF OSC DITH COMP SP SG OVUV VINL PL N PWMOUT GND LED1 LED5 10 kΩ M1High = internal PWM ON (5%) Low = no PWM (100%) Figure 13: Buck-Boost Driving 5 LEDs at 1.5 A, Switching Frequency 250 kHz Internal PWM (5%), no analog dimming, soft-start, and frequency dither on. Reference Description Manufacturer/Part Number C1,C2,C10,C11,C12 4.7 µF, ceramic capacitor, X7R, 50 V TDK, MuRata C3,C4 100 nF, ceramic capacitor, X7R, 50 V C5 1 µF, ceramic capacitor, X7R, 16 V C6 22 nF, ceramic capacitor, X7R, 50 V C7 220 nF, ceramic capacitor, X7R, 50 V C8 22 pF, ceramic capacitor, X7R, 50 V C9 47 nF, ceramic capacitor, X7R, 16 V D1 200 mA, 40 V Schottky diode ST / BAT54 D2 10 A, 60 V Schottky diode Vishay / SS10P6 L1 12 µH, high current shielded construction Vishay / IHLP-5050FDER120M-5A M1,M2 N-channel signal MOSFET 2N7000 or equivalent M3 N-channel 50 A, 100 V MOSFET Vishay / SQD50N10 Table 4: Application Circuit 3 Bill of Materials Continued on next page...

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Reference Description Manufacturer/Part Number M4 P-channel 15 A, 100 V MOSFET Infineon / SPD15P10PL G Heatsink for M3 (TO-252) AAVID Thermalloy / 573100D00010G R1 2.7 kΩ, 1%, 0603 or 0805 R2 270 kΩ, 1%, 0603 or 0805 R3,R5,R10,R16 10 kΩ, 1%, 0603 or 0805 R4 68 kΩ, 1%, 0603 or 0805 R6 100 kΩ, 1%, 0603 or 0805 R7 220 kΩ, 1%, 0603 or 0805 R8 39 Ω, 1%, 0603 or 0805 R9 150 Ω, 1%, 0603 or 0805 R11, R12 270 mΩ, 1%, 0805 or 1206 R13 4.3 kΩ, 1%, 0603 or 0805 R14 0 Ω, 0603 or 0805 R15 1 kΩ, 1%, 0603 or 0805 R17,R18 62 mΩ, 1%, 2010 R19 84.5 kΩ, 1%, 0603 or 0805 Table 4: Application Circuit 3 Bill of Materials (continued)

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A6271-1 VBAT 4.7 µF 4.7 µF C10 4.7 µF C11 4.7 µF C12 4.7 µF 1 µF 100 nF 22 nF 22 pFC7 470 nF 100 nF 47 nF L1 47 µH 2.7 kΩ R12 1 kΩ R10 4.3 kΩ 20 kΩ 10 kΩ R4 100 kΩ R16 68 kΩ R13 10 kΩ R7 10 kΩ R14 180 mΩ R15 180 mΩ 27 Ω 150 Ω 1 Ω 1 Ω R11 24 Ω VREG GND FA ULT n DR PWMIN IREF OSC DITH COMP SP SG OVUV VI NL PL N PWMOUT External PWM Drive Signal GND LED1 LED4 Analog Control Figure 14: Buck-Boost Driving 4 LEDs at 400 mA, Switching Frequency 250 kHz External PWM and/or analog dimming, no soft-start, and frequency dither off. Reference Description Manufacturer/Part Number C1,C2,C10,C11,C12 4.7 µF, ceramic capacitor, X7R, 50 V TDK, MuRata C3,C4 100 nF, ceramic capacitor, X7R, 50 V C5 1 µF, ceramic capacitor, X7R, 16 V C6 22 nF, ceramic capacitor, X7R, 50 V C7 470 nF, ceramic capacitor, X7R, 50 V C8 22 pF, ceramic capacitor, X7R, 50 V C9 47 nF, ceramic capacitor, X7R, 16 V D1 200 mA, 40 V Schottky diode ST / BAT54 D2 2 A, 60 V Schottky diode ON Semiconductor / MBRS260T3 L1 47 µH, power inductor shielded construction Coilcraft / MSS1048T-473ML M1 N-channel, 30 A, 100 V MOSFET NXP / PSMN038-100YLX M2 P-channel 15 A, 100 V MOSFET Infineon / SPD15P10PL G Table 5: Application Circuit 4 Bill of Materials Continued on next page...

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Table 5: Application Circuit 4 Bill of Materials (continued) Reference Description Manufacturer/Part Number R1 2.7 kΩ, 1%, 0603 or 0805 R2 20 kΩ, 1%, 0603 or 0805 R3 10 kΩ, potentiometer R4 100 kΩ, 1%, 0603 or 0805 R5 27 Ω, 1%, 0603 or 0805 R6 150 Ω, 1%, 0603 or 0805 R7, R13 10 kΩ, 1%, 0603 or 0805 R8, R9 1 Ω, 1%, 0805 or 1206 R10 4.3 kΩ, 1%, 0603 or 0805 R11 24 Ω, 1%, 0603 or 0805 R12 1 kΩ, 1%, 0603 or 0805 R14, R15 180 mΩ, 1%, 1206 R16 68 kΩ, 1%, 0603 or 0805

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A6271-1 Park 4.7 µF 4.7 µF C10 4.7 µF C11 4.7 µF C12 4.7 µF 1 µF 100 nF 22 nF 22 pFC7 470 nF 100 nF 47 nF L1 22 µH 2.7 kΩ R17 1.2 kΩ R15 4.3 kΩ 20 kΩ 10 kΩ R8 100 kΩ R21 220 kΩ R18 10 kΩ R12 10 kΩ R19 68 mΩ R20 68 mΩ R10 39 Ω R11 150 Ω R13 470 mΩ R14 2.7 Ω R16 0 Ω VREG GND FAULTn DR PWMIN IREF OSC DITH COMP SP SG OVUV VINL P LN PWMOUT GND LED1 LED12 Analog Control D1DRL 220 kΩ 68 kΩ 270 kΩ 10 kΩ R22 20 kΩ 10 kΩ Figure 15: Park / DRL Application (Park-Dominant) Boost Driving 12 LEDs at 500 mA, Switching Frequency 250 kHz. Park Mode: Internal PWM (5%) and analog dimming, no soft start, and frequency dither on. Daylight Running Light (DRL) Mode: 100% LED current and analog dimming, no soft start, and frequency dither on. Battery voltage applied either at Park terminal or DRL terminal. Note that Park Mode is dominant. Table 6: Application Circuit 5 Bill of Materials Continued on next page... Reference Description Manufacturer/Part Number C1,C2,C10,C11,C12 4.7 µF, ceramic capacitor, X7R, 50 V TDK, MuRata C3,C4 100 nF, ceramic capacitor, X7R, 50 V C5 1 µF, ceramic capacitor, X7R, 16 V C6 22 nF, ceramic capacitor, X7R, 50 V C7 470 nF, ceramic capacitor, X7R, 50 V C8 22 pF, ceramic capacitor, X7R, 50 V C9 47 nF, ceramic capacitor, X7R, 16 V D1, D3 3 A, 100 V Schottky diode ON Semiconductor / NRVBS3100T3G D2 10 A, 60 V Schottky diode Vishay / SS10P6 L1 22 µH, high current shielded construction Vishay / IHLP-5050FDER220M-5A M1, M2 N-channel signal MOSFET 2N7000 or equivalent

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Table 6: Application Circuit 5 Bill of Materials (continued) Reference Description Manufacturer/Part Number M3 N-channel, 50 A, 100 V MOSFET Vishay / SQD50N10 M4 P-channel, 15 A, 100 V MOSFET Infineon / SPD15P10PL G Heatsink for M3 (TO-252) AAVID Thermalloy / 573100D00010G R1 2.7 kΩ, 1%, 0603 or 0805 R2 270 kΩ, 1%, 0603 or 0805 R3,R6,R12,R18 10 kΩ, 1%, 0603 or 0805 R4 68 kΩ, 1%, 0603 or 0805 R5, R22 20 kΩ, 1%, 0603 or 0805 R7 10 kΩ, potentiometer R8 100 kΩ, 1%, 0603 or 0805 R9 220 kΩ, 1%, 0805 or 1206 R10 39 Ω, 1%, 0603 or 0805 R11 150 Ω, 1%, 0603 or 0805 R13 470 mΩ, 1%, 0805 or 1206 R14 2.7 Ω, 1%, 0603 or 0805 R15 4.3 kΩ, 1%, 0603 or 0805 R16 0 Ω, 0603 or 0805 R17 1.2 Ω, 1%, 0603 or 0805 R19, R20 68 mΩ, 1%, 2010 R21 220 kΩ, 1%, 0603 or 0805

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A6271-1 DRL 4.7 µF 4.7 µF C10 4.7 µF C11 4.7 µF C12 4.7 µF 1 µF 100 nF 22 nF 22 pFC7 470 nF 100 nF 47 nF L1 22 µH 2.7 kΩ R16 1.2 kΩ R14 4.3 kΩ 100 kΩ R20 220 kΩ R17 10 kΩ R11 10 kΩ R18 68 mΩ R19 68 mΩ 39 Ω R10 150 Ω R12 470 mΩ R13 2.7 Ω R15 0 Ω VREG GND FAULTn DR PWMIN IREF OSC DITH COMP SP SG OVUV VI NL P LN PWMOUT GND LED1 LED12 D1Park 220 kΩ 68 kΩ 130 kΩ R21 20 kΩ M1 M2 10 kΩ 100 kΩ IREF 10 kΩR22 100 kΩ 5.1 V Figure 16: Park / DRL Application (DRL-Dominant) Boost Driving 12 LEDs at 500 mA, Switching Frequency 250 kHz. Park Mode: Internal PWM (10%) and analog dimming at 45% of target level, no soft start, and frequency dither on. Daylight Running Light (DRL) Mode: 100% LED current, no analog dimming, no soft start, and frequency dither on. Battery voltage applied either at Park terminal or DRL terminal. Note that DRL Mode is dominant. Table 7: Application Circuit 6 Bill of Materials Continued on next page... Reference Description Manufacturer/Part Number C1,C2,C10,C11,C12 4.7 µF, ceramic capacitor, X7R, 50 V TDK, MuRata C3,C4 100 nF, ceramic capacitor, X7R, 50 V C5 1 µF, ceramic capacitor, X7R, 16 V C6 22 nF, ceramic capacitor, X7R, 50 V C7 470 nF, ceramic capacitor, X7R, 50 V C8 22 pF, ceramic capacitor, X7R, 50 V C9 47 nF, ceramic capacitor, X7R, 16 V D1, D3 3 A, 100 V Schottky diode ON Semiconductor / NRVBS3100T3G D2 10 A, 60 V Schottky diode Vishay / SS10P6 D4 5.1 V, Zener diode ON Semiconductor / SZBZX84C5V1 D5 Signal diode 1N4148WS L1 22 µH, high current shielded construction Vishay / IHLP-5050FDER220M-5A

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Table 7: Application Circuit 6 Bill of Materials (continued) Reference Description Manufacturer/Part Number M1, M2 N-channel signal MOSFET ON Semiconductor, IR / NTR4003N M3 N-channel, 50 A, 100 V MOSFET Vishay / SQD50N10 M4 P-channel, 15 A, 100 V MOSFET Infineon / SPD15P10PL G Heatsink for M3 (TO-252) AAVID Thermalloy / 573100D00010G R1 2.7 kΩ, 1%, 0603 or 0805 R2 130 kΩ, 1%, 0603 or 0805 R3,R6,R11,R17 10 kΩ, 1%, 0603 or 0805 R4 68 kΩ, 1%, 0603 or 0805 R5, R7, R22 100 kΩ, 1%, 0603 or 0805 R8 220 kΩ, 1%, 0805 or 1206 R9 39 Ω, 1%, 0603 or 0805 R10 150 Ω, 1%, 0603 or 0805 R12 470 mΩ, 1%, 0805 or 1206 R13 2.7 Ω, 1%, 0603 or 0805 R14 4.3 kΩ, 1%, 0603 or 0805 R15 0 Ω, 0603 or 0805 R16 1.2 kΩ, 1%, 0603 or 0805 R18, R19 68 mΩ, 1%, 2010 R20 220 kΩ, 1%, 0603 or 0805 R21 110 kΩ, 1%, 0603 or 0805

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com PACKAGE OUTLINE DRAWING Figure 17: Package LP, 16-Pin eTSSOP with Exposed Thermal Pad A

1.20 MAX

0.15 0.00 0.30 0.19 0.20 0.09 0.60 ±0.15

1.00 REF

C SEATING PLANE C0.10 16X

0.65 BSC

0.25 BSC

5.00 ±0.10 GAUGE PLANE SEATING PLANE A B B C D Exposed thermal pad (bottom surface); dimensions may vary with device 6.10 0.650.45 1.70 3.00 3.00 2 1 C D Branded Face

3 NOM

For Reference Only – Not for Tooling Use (Reference MO-153 ABT) Dimensions in millimeters. NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown PCB Layout Reference View Terminal #1 mark area Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Branding scale and appearance at supplier discretion Standard Branding Reference View YYWW NNNNNNN LLLL = Device part number = Supplier emblem = Last two digits of year of manufacture = Week of manufacture = Characters 5-8 of lot number N Y W L

Automotive, High-Current LED ControllerA6271-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com For the latest version of this document, visit our website: www.allegromicro.com Revision Table Number Date Description – May 5, 2017 Initial release

1 January 2, 2018 Updated Figures 1, 11, 12, 13, 15, 16, and A-2; added Table of Contents

2 January 24, 2018 Updated Ramp Up and Ramp Down Threshold test conditions (page 7), and Protection section (page 12-13) 3 July 9, 2018 Note added to Figure 12 (page 26). Copyright ©2018, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents.

Automotive, High-Current LED ControllerA6271-1 A-1 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com APPENDIX A: SPECIAL NOTES ON A6271-1 OPERATING IN SEPIC MODE In automotive lighting applications, SEPIC (Single-Ended Primary-Inductor Converter) is an attractive alternative to the tra- ditional Boost and Buck-Boost topologies. As can be seen in the following comparison diagram, the SEPIC configuration looks very similar to the Boost configuration, except for the additional inductor L2 and DC-blocking capacitor C FLY. VIN LP LN PWMOUT SG SP Battery A6271-1 GND RSS COUT RSL D L CIN VIN PWMIN LP LN PWMOUT SG SP Battery A6271-1 GND RSS COUT RSL CIN CFLY VOUT CREG L1 & L2 can be either separate or integrated PWMIN VOUT VINVIN VOUT VREG CREG VREG Boost Configuration SEPIC Configuration VOUT = VIN × [ 1/(1-D)] VOUT = V IN × [ D/(1-D)] Figure A-1: Comparison of A6271-1 in Boost and SEPIC configurations The main advantages of using SEPIC configuration are:

• VOUT (VLED) can be either higher or lower than VIN. This allows the converter to handle both Cold-Crank (VIN down to ~5 V) and Load-Dump (VIN up to 40 V) situations.
• There is a DC-blocking capacitor between VIN and VOUT. This naturally protects the power supply against Output-Shorted-to- GND fault. On the other hand, several limitations of SEPIC must be consid- ered, namely:
• Need to use either two inductors, or one dual-winding coupled inductor.
• The switching MOSFET and diode are subjected to higher voltage stress of V IN + VLED. This means higher switching loses compared to Boost configuration. Note that in Buck- Boost configuration the same voltage stress applies.
• At power up, a ‘bleeder’ circuit is needed to help the IC bypass undervoltage protection (since initially the output is at 0 V).
• A minimum output voltage of around 6 V (two WLEDs in series) is required, for the PWMOUT gate driver to turn on the external PMOS.

Automotive, High-Current LED ControllerA6271-1 A-2 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com The next application diagram shows the A6271-1 configured in SEPIC mode, for driving 5 LEDs at 1.5 A. A6271-1 VBAT 4.7 µF 4.7 µF C10 4.7 µF C11 4.7 µF C12 4.7 µF 1 µF 100 nF 22 nF 22 pFC7 220 nF 100 nF 47 nF R11 270 mΩ R12 270 mΩ 2.7 kΩ R15 1 kΩ R13 4.3 kΩ 270 kΩ 10 kΩ 68 kΩ 100 kΩ 220 kΩ R19 84.5 kΩ R16 10 kΩ R10 10 kΩ R17 62 mΩ R18 62 mΩ 39 Ω 150 Ω R14 0 Ω VREG GND FAULTn DR PWMIN IREF OSC DITH COMP SP SG OVUV VINL P LN PWMOUT GND LED1 LED5 10 kΩ M1High = internal PWM ON (5% ) Low = no PWM (100%) D3 R20 1 kΩ VOUT L1 & L2 can be either separate or integrated C13 4.7 µF L2 12 µH L1 12 µH VOUT Figure A-2: SEPIC Driving 5 LEDs at 1.5 A, Switching Frequency 250 kHz Internal PWM (5%), no analog dimming, soft-start, and frequency dither on. Table 8: Application Circuit 7 Bill of Materials Reference Description Manufacturer/Part Number C1,C2,C10,C11,C12,C13 4.7 µF, ceramic capacitor, X7R, 50 V TDK, MuRata C3,C4 100 nF, ceramic capacitor, X7R, 50 V C5 1 µF, ceramic capacitor, X7R, 16 V C6 22 nF, ceramic capacitor, X7R, 50 V C7 220 nF, ceramic capacitor, X7R, 50 V C8 22 pF, ceramic capacitor, X7R, 50 V C9 47 nF, ceramic capacitor, X7R, 16 V D1, D3 200 mA, 40 V Schottky diode ST / BAT54 D2 10 A, 60 V Schottky diode Vishay / SS10P6 L1, L2 12 µH, high-current shielded construction Vishay / IHLP-5050FDER120M-5A M1,M2 N-channel signal MOSFET 2N7000 or equivalent M3 N-channel 50 A, 100 V MOSFET Vishay / SQD50N10 Continued on next page...

Automotive, High-Current LED ControllerA6271-1 A-3 Allegro MicroSystems, LLC Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Reference Description Manufacturer/Part Number M4 P-channel 15 A, 100 V MOSFET Infineon / SPD15P10PL G Heatsink for M3 (TO-252) AAVID Thermalloy / 573100D00010G R1 2.7 kΩ, 1%, 0603 or 0805 R2 270 kΩ, 1%, 0603 or 0805 R3,R5,R10,R16 10 kΩ, 1%, 0603 or 0805 R4 68 kΩ, 1%, 0603 or 0805 R6 100 kΩ, 1%, 0603 or 0805 R7 220 kΩ, 1%, 0603 or 0805 R8 39 Ω, 1%, 0603 or 0805 R9 150 Ω, 1%, 0603 or 0805 R11,R12 270 mΩ, 1%, 0805 or 1206 R13 4.3 kΩ, 1%, 0603 or 0805 R14 0 Ω, 0603 or 0805 R15 1 kΩ, 1%, 0603 or 0805 R17,R18 62 mΩ, 1%, 2010 R19 84.5 kΩ, 1%, 0603 or 0805 R20 1 kΩ, 1%, 0603 or 0805 Table 8: Application Circuit 7 Bill of Materials (continued)