A4983

A4983 ALLEGRO

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

0.22 μF0 . 1 μF0 . 1 μF CP2 VBB VBB A4983

Description

The A4983 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, eighth, and sixteenth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A4983 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. The translator is the key to the easy implementation of the A4983. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A4983 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. The chopping control in the A4983 automatically selects the current decay mode (Slow or Mixed). When a signal occurs at the STEP input pin, the A4983 determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to Slow decay. If the change is to a lower current, then the current decay is set to Mixed (set initially to a fast decay for a period amounting to 31.25% of the fixed off-time, then to a 4983DS Features and Benefits ▪ Low R DS(ON) outputs ▪ Automatic current decay mode detection/selection ▪ Mixed and Slow current decay modes ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO ▪ Crossover-current protection ▪ 3.3 and 5 V compatible logic supply ▪ Very thin profile QFN package ▪ Thermal shutdown circuitry DMOS Microstepping Driver with Translator Continued on the next page… Package: 28-pin QFN (suffix ET) Typical Application Diagram A4983 Approximate size

DMOS Microstepping Driver with TranslatorA4983 2Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com slow decay for the remainder of the off-time). This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power- on sequencing is not required. The A4983 is supplied in a 5 mm × 5 mm × 0.90 nominal surface mount QFN package with exposed thermal pad (suffix ET). The package is lead (Pb) free (suffix –T), with 100% matte tin plated leadframe. Description (continued) Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage V BB 35 V Output Current I OUT ±2 A Duty Cycle < 20% ±2.5 A Logic Input Voltage V IN –0.3 to 7 V Sense Voltage V SENSE 0.5 V Reference Voltage V REF 4V Operating Ambient Temperature T A Range S –20 to 85 ºC Maximum Junction T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC Selection Guide Part Number Pb-free Package Packing A4983SET-T Yes 28-pin QFN with exposed thermal pad 73 pieces per tube A4983SETTR-T Yes 28-pin QFN with exposed thermal pad 1500 pieces per 7-in. reel

DMOS Microstepping Driver with TranslatorA4983 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Functional Block Diagram SENSE1 SENSE2 VREG VCP CP2 Control Logic DAC VDD PWM Latch Blanking Mixed Decay DAC STEP DIR RESET MS1 PWM Latch Blanking Mixed Decay Current Regulator CP1 Charge Pump RS2 RS1 VBB1 OUT1A OUT1B VBB2 OUT2A OUT2B 0.1 MF VREF Translator Gate Drive DMOS Full Bridge DMOS Full Bridge 0.1 MF0.22 MF OSC ROSC MS2 REF ENABLE SLEEP MS3

DMOS Microstepping Driver with TranslatorA4983 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) 1Negative current is defined as coming out of (sourcing from) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3errI = (ITrip – IProg ) ⁄ IProg , where IProg = %ITripMAX× ITripMAX. Characteristics Symbol Test Conditions Min. Typ.2 Max. Units Output Drivers Load Supply Voltage Range V BB Operating 8 – 35 V During Sleep Mode 0 – 35 V Logic Supply Voltage Range V DD Operating 3.0 – 5.5 V Output On Resistance R DSON Source Driver, IOUT = –1.5 A – 0.350 0.450 Ω Sink Driver, IOUT = 1.5 A – 0.300 0.370 Ω Body Diode Forward Voltage V F Source Diode, IF = –1.5 A – – 1.2 V Sink Diode, IF = 1.5 A – – 1.2 V Motor Supply Current I BB fPWM < 50 kHz – – 4 mA Operating, outputs disabled – – 2 mA Sleep Mode – – 10 μA Logic Supply Current I DD fPWM < 50 kHz – – 8 mA Outputs off – – 5 mA Sleep Mode – – 10 μA Control Logic Logic Input Voltage VIN(1) VDD×0.7 ––V VIN(0) –– VDD×0.3 V Logic Input Current IIN(1) VIN = VDD×0.7 –20 <1.0 20 μA IIN(0) VIN = VDD×0.3 –20 <1.0 20 μA Microstep Select 2 R MS2 – 100 – k Ω Microstep Select 3 R MS3 – 100 – k Ω Input Hysteresis V HYS(IN) 150 300 500 mV Blank Time tBLANK 0.7 1 1.3 μs Fixed Off-Time tOFF OSC > 3 V 20 30 40 μs ROSC = 25 kΩ 23 30 37 μs Reference Input Voltage Range V REF 0–4V Reference Input Current I REF –3 0 3 μA Current Trip-Level Error3 errI VREF = 2 V, %ITripMAX = 38.27% – – ±15 % VREF = 2 V, %ITripMAX = 70.71% – – ±5 % VREF = 2 V, %ITripMAX = 100.00% – – ±5 % Crossover Dead Time t DT 100 475 800 ns Protection Thermal Shutdown Temperature T J – 165 – °C Thermal Shutdown Hysteresis T JHYS –1 5–° C UVLO Enable Threshold UV LO VDD rising 2.35 2.7 3 V UVLO Hysteresis UV HYS 0.05 0.10 – V

DMOS Microstepping Driver with TranslatorA4983 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA Package ET; 4-layer PCB, based on JEDEC standard 32 ºC/W *In still air. Additional thermal information available on Allegro Web site. 20 40 60 80 100 120 140 160 180 Temperature (°C) Power Dissipation, PD (W) 0.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 Maximum Power Dissipation, PD(max) θJA = 32 ºC/W)

Figure 1. Logic Interface Timing Diagram Table 1. Microstep Resolution Truth Table

DMOS Microstepping Driver with TranslatorA4983 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Functional Description Device Operation. The A4983 is a complete microstepping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar step- per motors in full-, half-, quarter-, and sixteenth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PWM (pulse width modulated) control circuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (R S1 and RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in figures 2 through 6), and the current regulator to Mixed Decay Mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of inputs MS1, MS2, and MS3, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode for the active full-bridge is set to Mixed. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back EMF of the motor. If the logic circuits are pulled up to V DD, it is good practice to use a high value pull-up resistor in order to limit current to the logic inputs, should an overvoltage event occur. Logic inputs include: MSx, SLEEP, DIR, ENABLE, RESET, and STEP. RESET Input (RESET). The RESET input sets the trans- lator to a predefined Home state (shown in figures 2 through 6), and turns off all of the FET outputs. All STEP inputs are ignored until the RESET input is set to high. Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the combined state of inputs MS1, MS2, and MS3. Microstep Select (MS1, MS2, and MS3). Selects the microstepping format, as shown in table 1. MS2 and MS3 have a 100 kΩ pull-down resistance. Any changes made to these inputs do not take effect until the next STEP rising edge. If the MSx pins are pulled up to V DD, it is good practice to use a high value pull-up resistor in order to limit current to these pins, should an overvoltage event occur. Direction Input (DIR). This determines the direction of rotation of the motor. When low, the direction will be clockwise and when high, counterclockwise. Changes to this input do not take effect until the next STEP rising edge. Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, I TRIP . Initially, a diagonal pair of source and sink FET outputs are enabled and current flows through the motor winding and the current sense resistor, R Sx. When the voltage across RSx equals the DAC out- put voltage, the current sense comparator resets the PWM latch. The latch then turns off either the source FETs (when in Slow Decay Mode) or the sink and source FETs (when in Mixed Decay Mode). The maximum value of current limiting is set by the selection of R Sx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting, I TripMAX (A), which is set by ITripMAX = VREF / ( 8 × RS) where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V). The DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX / 100) × ITripMAX (See table 2 for %ITripMAX at each step.) Functional Description

DMOS Microstepping Driver with TranslatorA4983 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded. Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The one shot off-time, t OFF, is deter- mined by the selection of an external resistor connected from the ROSC timing pin to ground. If the ROSC pin is tied to an external voltage > 3 V , then t OFF defaults to 30 μs. The ROSC pin can be safely connected to the VDD pin for this purpose. The value of t OFF (μs) is approximately tOFF ≈ ROSC ⁄ 825 Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, t BLANK (μs), is approximately tBLANK ≈ 1 μs Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side FET gates. A 0.1 μF ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 μF ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side FET gates. VREG (VREG). This internally-generated voltage is used to operate the sink-side FET outputs. The VREG pin must be decoupled with a 0.22 μF ceramic capacitor to ground. VREG is internally monitored. In the case of a fault condition, the FET outputs of the A4983 are disabled. Enable Input (ENABLE). This input turns on or off all of the FET outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, MS1, MS2, and MS3, as well as the internal sequencing logic, all remain active, indepen- dent of the ENABLE input state. Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the FET outputs of the A4983 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state. Sleep Mode (SLEEP). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A4983 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4983 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. If the SLEEP pin is pulled up to V DD, it is good practice to use a high value pull-up resistor in order to limit current to the pin, should an overvoltage event occur. Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 3 through 6. As the trip point is reached, the A4983 initially goes into a fast decay mode for 31.25% of the off-time. tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. A tim- ing dagram for this feature appears on the next page. Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed–off-time cycle, load current recir- culates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET R DS(ON). This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Synchronous rectification turns off when the load current approaches zero (0 A), preventing reversal of the load current. A timing dagram for this feature appears on the next page.

DMOS Microstepping Driver with TranslatorA4983 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com VPHASE IOUT IOUT t See Enlargement A Enlargement A tSDtFD toff Slow Decay Mixed Decay Fast Decay IPEAK Symbol Characteristic toff Device fixed off-time IPEAK Maximum output current tSD Slow decay interval tFD Fast decay interval IOUT Device output current Current Decay Modes Timing Chart

DMOS Microstepping Driver with TranslatorA4983 10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Application Layout Layout The printed circuit board should use a heavy ground- plane. For optimum electrical and thermal performance, the A4983 must be soldered directly onto the board. On the under- side of the A4983 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. Thermal vias should not have any thermal relief and should be connected to internal layers, if available, to maximize the dissipation area. Grounding In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single- point ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the groundplane directly under the A4983, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path. PCB Thermal Vias Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.) Solder A4983 VBB VDD PAD A4983 C1 C8 C9C7 RS2RS1 OUT1B NC DIR GND REF STEP VDD OUT2B ENABLE GND CP1 CP2 VCP NC VREG MS1 MS2 MS3 RESET ROSC SLEEP VBB2 SENSE2 OUT2A NC OUT1A SENSE1 VBB1

11Allegro MicroSystems, Inc. Figure 4. Decay Modes for Quarter-Step Increments Figure 3. Decay Modes for Half-Step IncrementsFigure 2. Decay Mode for Full-Step Increments

12Allegro MicroSystems, Inc. Figure 5. Decay Modes for Eighth-Step Increments

13Allegro MicroSystems, Inc. Figure 6. Decay Modes for Sixteenth-Step Increments

14Allegro MicroSystems, Inc. Table 2. Step Sequencing Settings

DMOS Microstepping Driver with TranslatorA4983 15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Terminal List Table Name Number Description CP1 4 Charge pump capacitor terminal CP2 5 Charge pump capacitor terminal VCP 6 Reservoir capacitor terminal VREG 8 Regulator decoupling terminal MS1 9 Logic input MS2 10 Logic input MS3 11 Logic input RESET 12 Logic input ROSC 13 Timing set SLEEP 14 Logic input VDD 15 Logic supply STEP 16 Logic input REF 17 G m reference voltage input GND 3, 18 Ground* DIR 19 Logic input OUT1B 21 DMOS Full Bridge 1 Output B VBB1 22 Load supply SENSE1 23 Sense resistor terminal for Bridge 1 OUT1A 24 DMOS Full Bridge 1 Output A OUT2A 26 DMOS Full Bridge 2 Output A SENSE2 27 Sense resistor terminal for Bridge 2 VBB2 28 Load supply OUT2B 1 DMOS Full Bridge 2 Output B ENABLE 2 Logic input NC 7, 20, 25 No connection PAD – Exposed pad for enhanced thermal dissipation* *The GND pins must be tied together externally by connecting to the PAD ground plane under the device. PAD VBB2 SENSE2 OUT2A NC OUT1A SENSE1 VBB1 VREG MS1 MS2 MS3 RESET ROSC SLEEP OUT1B NC DIR GND REF STEP VDD OUT2B ENABLE GND CP1 CP2 VCP NC Pin-out Diagram

DMOS Microstepping Driver with TranslatorA4983 16Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4X0.20 MIN .008 0.30 NOM .012 1.09 REF .043 0.50 NOM .020 4.96 NOM .195 4.96 NOM .195 3.15 NOM .124 3.15 NOM .124 3.15 NOM .124 0.30 0.18 .012 .007 1.00 0.80 .039 .031 0.05 0.00 .002 .000 5.15 4.85 .203 .191 5.15 4.85 .203 .191 0.20 REF .008 A B CSEATING PLANEC0.08 [.003] 28X 28X 0.10 [.004] M C A B MIN .008 4X0.20 MIN .008 R0.25 REF .010 3.15 NOM .124 5.0 NOM .197 5.0 NOM .197 0.56 REF .022 A Terminal #1 mark area B Exposed thermal pad (terminal #1 identifier appearance at supplier discretion) All dimensions reference, not for tooling use (reference JEDEC MO-220VHHD except contact length and exposed pad length and width) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown C C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V3M) except heel extended; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) A B Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system.The in for ma tion in clud ed herein is be- lieved to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright ©2007, Allegro MicroSystems, Inc. For the latest version of this document, visit our website: www.allegromicro.com