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The A4933 is a 3-phase controller for use with N-channel external power MOSFETs and is specifically designed for automotive applications. A unique charge pump regulator provides full (>10 V) gate drive for battery voltages down to 7 V and allows the A4933 to operate with a reduced gate drive, down to 5.5 V . A bootstrap capacitor is used to provide the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high-side drive allows DC (100% duty cycle) operation. Full control over all six power FETs in the 3-phase bridge is provided, allowing motors to be driven with block commutation or sinusoidal excitation. The power FETs are protected from shoot-through by integrated crossover control and resistor- adjustable dead time. Bridge current can be measured using an integrated current sense amplifier. This is an uncommitted differential amplifier with a below-ground common mode range allowing it to be used in low-side current sense applications. Gain and offset are defined by external resistors. 4933-DS Features and Benefits ▪ High current 3-phase gate drive for large N-channel MOSFETs ▪ Pin compatible with Allegro® A4935KJP ▪ Cross-conduction protection with adjustable dead time ▪ Top-off charge pump for 100% PWM ▪ Charge pump for low supply voltage operation ▪ Uncommitted current sense amplifier ▪ 5.5 to 50 V supply voltage range ▪ Compatible with 3.3 V and 5 V logic ▪ Extensive diagnostic outputs ▪ Low-current sleep mode Automotive 3-Phase MOSFET Driver Continued on the next page… Package: 48-pin LQFP with exposed thermal pad (suffix JP) Typical Application Not to scale A4933 VBAT VBAT A4405 Regulator Current Sense 3-Phase BLDC Motor A4933 DSP or Micro- controller Control Diagnostics

Automotive 3-Phase MOSFET DriverA4933 2Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. Integrated diagnostics provide indication of undervoltage, overtemperature, and power bridge faults. They can be configured to protect the power FETs under most short circuit conditions. Detailed diagnostics are available as a serial data word. The A4933 is supplied in a 48-pin LQFP with exposed thermal pad, (suffix JP). This is a small footprint (81 mm 2) power package. It is lead (Pb) free with 100% matte tin leadframe plating. Description (continued) Selection Guide Part Number Packing A4933KJPTR-T 1500 pieces per reel THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA 4-layer PCB based on JEDEC standard 23 ºC/W 2-layer PCB with 3 in.2 of copper area each side 44 ºC/W RθJP 2 ºC/W *Additional thermal information available on Allegro website. Absolute Maximum Ratings* Characteristic Symbol Notes Rating Units Load Supply Voltage V BB –0.3 to 50 V Logic Supply Voltage V DD –0.3 to 7 V VREG –0.3 to 16 V CP1 and CP2 –0.3 to 16 V Logic Inputs and Outputs –0.3 to 6.5 V CSP and CSN –4 to 6.5 V LSS –4 to 6.5 V CSO and VDSTH –0.3 to 6.5 V SA, SB, and SC –5 to 55 V RDEAD –0.3 to 6.5 V VDRAIN –5 to 55 V GHA, GHB, and GHC Sx to Sx+15 V GLA, GLB, and GLC –5 to 16 V CA, CB, and CC –0.3 to Sx+15 V Operating Temperature Range T A Range K –40 to 150 ºC Junction Temperature T J(max) 150 ºC Transient Junction Temperature T tJ Overtemperature event not exceeding 10 s, lifetime duration not exceeding 10 h, guaranteed by design characterization 175 ºC Storage Temperature Range T stg –55 to 150 ºC ESD Rating, Human Body Model AEC-Q100-002, all pins 2000 V ESD Rating, Charged Device Model AEC-Q100-011, all pins 1050 V *With respect to AGND.

Automotive 3-Phase MOSFET DriverA4933 3Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Functional Block Diagram Battery + Charge Pump Regulator High Side Drive Bootstrap Monitor Charge Pump VBAT CP2CP1 ALO BHI BLO CHI CLO FF1 AGND CSP LSS GLA GHA SA CA VREG AHI VREG Phase A (repeated for B & C) VBB VDD PWML Phase C Phase B RGATE RGATE CBOOTA CREG CP FF2 PWMH COAST RDEAD VDSTH Low Side Drive CSN VDRAIN RESET ESF Logic Supply CCEN Diagnostics and Protection UVLO, OTF Short to Supply Short to Gnd Short Load Control Logic CSOUT

Automotive 3-Phase MOSFET DriverA4933 4Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Characteristics Symbol Test Conditions Min. Typ. Max. Units Supply and Reference Load Supply Voltage Functional Operating Range1 VBB 5.5 – 50 V Load Supply Quiescent Current IBBQ RESET = high, outputs = low, VBB = 12 V – 10 14 mA IBBS RESET = low, Sleep mode, VBB = 12 V – – 10 μA Logic Supply Voltage V DD 3.0 – 5.5 V Logic Supply Quiescent Current IDDQ RESET = high, outputs = low – 4 6 mA IDDS RESET = low – – 10 μA VREG Output Voltage V REG VBB > 9 V, IREG = 0 to 50 mA 9 13 13.80 V 7.5 V < VBB ≤ 9 V, IREG = 0 to 30 mA 9 13 13.80 V 6 V < VBB ≤ 7.5 V, IREG = 0 to 17 mA 8.5 – – V 5.5 V < VBB ≤ 6 V, IREG < 13 mA 7.5 9.5 – V Bootstrap Diode Forward Voltage V fBOOT ID = 10 mA 0.4 0.7 1.0 V ID = 100 mA 0.6 1.0 1.2 V Bootstrap Diode Resistance r D rD(100mA) = (VfBOOT(150mA) – VfBOOT(50mA)) / 100 mA 248 Ω Bootstrap Diode Current Limit I DBOOT 500 1000 1500 mA Top-off Charge Pump Current Limit I TOCPM – 400 – μA High-Side Gate Drive Static Load Resistance R GSH 250 – – k Ω Gate Output Drive Turn-On Time t r CLOAD = 10 nF, 20% to 80% – 175 – ns Turn-Off Time t f CLOAD = 10 nF, 80% to 20% – 100 – ns Pullup On Resistance R DS(on)UP TJ = 25°C, IGHx = –300 mA 3 4 6 Ω TJ = 150°C, IGHx = –300 mA 5 6.5 8 Ω Pulldown On Resistance R DS(on)DN TJ = 25°C, IGLx = 300 mA 1 1.5 2 Ω TJ = 150°C, IGLx = 300 mA 1.5 2 3 Ω GHx Output Voltage V GHX Bootstrap capacitor fully charged VCx – 0.2 ––V GLx Output Voltage V GLX VREG – 0.2 ––V Turn-Off Propagation Delay2 tP(off) Input change to unloaded gate output change 60 90 130 ns Turn-On Propagation Delay2 tP(on) Input change to unloaded gate output change 60 90 130 ns Propagation Delay Matching, Phase-to-Phase ∆tPP Measured between corresponding transition points on two sequential phases –1 0–n s Propagation Delay Matching, On-to-Off ∆tOO Measured across one phase – 10 – ns ELECTRICAL CHARACTERISTICS valid at TJ = –40°C to 150°C, VDD = 3 to 5.5 V, VBB = 7 to 50 V, unless noted otherwise Continued on the next page…

Automotive 3-Phase MOSFET DriverA4933 5Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Characteristics Symbol Test Conditions Min. Typ. Max. Units Dead Time2 tDEAD RDEAD tied to GND – 0 – ns RDEAD = 3 kΩ – 180 – ns RDEAD = 30 kΩ 815 960 1110 ns RDEAD = 240 kΩ – 3.5 – μs RDEAD tied to VDD – 6 – μs Logic Inputs and Outputs FF1 and FF2 Fault Output V FF(L) IFF = 1 mA, fault not present – – 0.4 V FF1 and FF2 Fault Output Leakage Current3 IFF(H) VFF = 5 V, fault present –1 – 1 μA RDEAD Input Low Voltage V DEAD(L) – – 0.2 V RDEAD Current3 IDEAD RDEAD = GND –200 – –70 μA Input Low Voltage V IN(L) –– 0.3 × VDD V Input High Voltage V IN(H) 0.7 × VDD ––V Input Hysteresis V INhys 300 500 – mV Input Current (Except RESET and CCEN)3 IIN 0 V < VIN < VDD –1 – 1 μA Input Pulldown Resistor (RESET and CCEN) R PD –5 0–k Ω RESET Pulse Time4 tRES 0.1 – 3.5 μs RESET Delay4 tDR – – 200 ns FF2 Clock Input High Voltage V ILC –– 0.3 × VDD V FF2 Clock Input Low Voltage V IHC 0.7 × VDD ––V FF2 Clock Input Hysteresis V IChys 300 500 – mV FF2 Clock Low to Valid Data Delay4 tDF – – 100 ns FF2 Clock Low to Fault Reset Delay4 tRF – – 100 ns FF2 Clock High Time4 tHF 500 – – ns FF2 Clock Low Time4 tLF 500 – – ns Current Sense Differential Amplifier Differential Input Voltage V ID VID = CSP – CSN, –1.3 V < VCM < 4 V –V DD –V DD mV Input Bias Current3 IBIAS CSP = CSN = 0 V –100 0 100 nA Input Offset Current3 IOS CSP = CSN = 0 V –100 0 100 nA Input Offset Voltage V IOS CSP = CSN = 0 V –10 – +10 mV Input Offset Voltage Drift ∆VIOS CSP = CSN = 0 V – 10 – μV/°C Input Common Mode Range CMR CSP = CSN –1.5 – 4 V Open Loop Gain A Vopn 40 mV< VID < 175 mV, VCM in range 100 – – dB Closed Loop Gain A Vclos 40 mV< VID < 175 mV, VCM in range 5 – – V/V Continued on the next page… ELECTRICAL CHARACTERISTICS (continued) valid at TJ = –40°C to 150°C, VDD = 3 to 5.5 V, VBB = 7 to 50 V, unless noted otherwise

Automotive 3-Phase MOSFET DriverA4933 6Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Characteristics Symbol Test Conditions Min. Typ. Max. Units Small Signal –3 dB Frequency Bandwidth BW G VID = 10 mVpp, G = 5 V/V – 1.6 – MHz Settling Time t SETTLE To within 10% of steady state, VCSOUT = 1 Vpp square wave – 400 – ns Output Dynamic Range V CSOUT –100 μA < ICSOUT < 100 μA 0.1 – VDD – 0.3 V Output Current Sink I CSsink VID = –400 mV, VCSOUT = 1.5 V 1 – – mA Output Current Source I CSsource VID = 400 mV, VCSOUT = 1.5 V – – –1 mA VREG Supply Ripple Rejection PSRR CSP = CSN = AGND, 0 to 300 kHz – 45 – dB DC Common Mode Rejection CMRR CSP = CSN = 0 to 200 mV step – 38 – dB AC Common Mode Rejection CMRR V CM = 200 mVpp, 0 to 1 MHz – 28 – dB Common Mode Recovery Time t CMrec To within 100 mV of steady state, VCM = +4 V step within CMR –1– μs Output Slew Rate SR 10% to 90%, V ID = 0 to 175 mV step – 20 – V/ μs Input Overload Recovery t IDrec To within 10% of steady state, VID = 250 mV to 0 V step – 500 – ns Protection VREG Undervoltage Lockout Threshold VREGUVon VREG rising 7.5 8 8.5 V VREGUVoff VREG falling 6.75 7.25 7.75 V Bootstrap Undervoltage Threshold V BOOTUV Cx with respect to Sx 59 – 69 %V REG Bootstrap Undervoltage Hysteresis V BOOTUVhys –1 3– % V REG VDD Undervoltage Turn-Off Threshold V DDUV VDD falling 2.45 2.7 2.85 V VDD Undervoltage Hysteresis V DDUVhys 50 100 150 mV VDSTH Input Range V DSTH 0.1 – 2 V VDSTH Input Current I DSTH 0 V < VDSTH < 2 V – 10 30 μA VDRAIN Input Voltage V DRAIN 7V BB 50 V VDRAIN Input Current I DRAIN VDSTH = 2 V, VBB = 12 V, 0 V < VDRAIN < VBB – – 250 μA Short-to-Ground Threshold Offset5 VSTGO High-side on, VDSTH ≥ 1 V – ±100 – mV High-side on, VDSTH < 1 V –150 ±50 150 mV Short-to-Battery Threshold Offset6 VSTBO Low-side on, VDSTH ≥ 1 V – ±100 – mV Low-side on, VDSTH < 1 V –150 ±50 150 mV Overtemperature Fault Flag Threshold T JF Temperature increasing 150 170 – ºC Overtemperature Fault Hysteresis T JFhys Recovery = TJF – TJFhys –1 5–º C 1Functions correctly, but parameters are not guaranteed, below the general limits (7 V). 2See Gate Drive Timing diagrams. 3For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 4See Fault Output Timing diagram. 5As VSx decreases, fault occurs if VBAT –VSx > VSTG. STG threshold, VSTG = VDSTH + VSTGO . 6As VSx increases, fault occurs if VSx – VLSS > VSTB . STB threshold, VSTB = VDSTH+VSTBO . ELECTRICAL CHARACTERISTICS (continued) valid at TJ = –40°C to 150°C, VDD = 3 to 5.5 V, VBB = 7 to 50 V, unless noted otherwise

Automotive 3-Phase MOSFET DriverA4933 7Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. xHI xLO GHx GLx xHI xLO GHx GLx xHI xLO GHx GLx tDEAD tP(off) tDEADtP(off) tP(on) tP(off) tP(on) tP(off) Synchronous Rectification High-Side PWM Low-Side PWM PWMH GLx GHx tDEAD tDEADtP(off) tP(off) xHI = 1, xLO = 0, PWML = 1 PWML GLx GHx tDEAD tP(off) tDEADtP(off) xHI = 0, xLO = 1, PWMH = 1 COAST GLx GHx tP(off) tP(on) xHI = 1, xLO = 0, PWMH = PWML = 1 COAST xHI = 0, xLO = 1, PWMH = PWML = 1 GLx GHx tP(off) tP(on) FF1 FF2 Gate Drive RESET FF1 FF2 Gate Drive RESET tDF tDRtLF tRES Fault Register Read tHF tRF delbanE delbasiD EnabledDisabled Simple Fault Reset (A) Gate Drive Timing, Phase Control Inputs (B) Gate Drive Timing, PWM Inputs (C) Gate Drive Timing, COAST Inputs Timing Diagrams (D) Fault Output Timing

Automotive 3-Phase MOSFET DriverA4933 8Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. The A4933 is a three-phase MOSFET driver (pre-driver) with separate supplies for the logic, and for the analog and drive sec- tions. This permits operation with a regulated logic supply from 3 to 5.5 V and with an unregulated main supply of 7 to 50 V . The six high current gate drives are capable of driving a wide range of N-channel power MOSFETs, and are configured as three high-side drives and three low-side drives. Each drive can be con- trolled with a logic level input compatible with 3.3 or 5 V logic. The A4933 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external FETs are above 10 V , at supply voltages down to 7 V . For extreme battery voltage drop conditions, correct functional operation is guaranteed at supply voltages down to 5.5 V , but with a reduced gate drive voltage. The control inputs to the A4933 provide a very flexible solution for many motor control applications. For full sinusoidal excita- tion, each phase can be driven with an independent PWM signal. For less complex drive solutions, the two PWM inputs, PWML and PWMH, allow simple high-side, low-side, or fast-decay con- trol with a single PWM signal. A current sense amplifier allows motor current to be sensed by a low-value sense resistor in the ground connection to the power bridge. The A4933 includes a number of protection features against undervoltage, overtemperature, and power bridge faults. Fault states enable responses by the device or by the external controller, depending on the fault condition and logic settings. Two fault flag outputs, FF1 and FF2, are provided to signal detected faults to an external controller. Diagnostics include an internal fault register, which can be accessed by serial read out using the fault flag pins. Power Supplies Two power supply voltages are required, one for the logic interface and one for the analog and output drive sections. Both supplies should be decoupled with ceramic capacitors connected close to the supply and ground pins. The logic supply, connected to VDD, allows the flexibility of a 3.3 or 5 V logic interface. The main power supply should be con- nected to VBB through a reverse voltage protection circuit. The A4933 operates within specified parameters with a VBB supply from 7 to 50 V and functions correctly with a supply down to 5.5 V . This provides a very rugged solution for use in the harsh automotive environment. Gate Drives The A4933 is designed to drive external, low on-resistance, power N-channel MOSFETs. It supplies the large transient cur- rents necessary to quickly charge and discharge the external FET gate capacitance in order to reduce dissipation in the external FET during switching. The charge and discharge rate can be controlled using an external resistor in series with the connection to the gate of the FET. Gate Drive Voltage Regulation The gate drives are powered by an internal regulator which limits the supply to the drives and therefore the maximum gate voltage. When the VBB supply greater than about 16 V , the regulator is a simple linear regulator. Below 16 V , the regulated supply is maintained by a charge pump boost converter, which requires a pump capacitor connected between the CP1 and CP2 pins. This capacitor must have a mini- mum value of 470 nF, and is typically 680 nF. The regulated voltage, nominally 13 V , is available on the VREG pin. A sufficiently large storage capacitor must be connected to this pin to provide the transient charging current to the low-side drives and the bootstrap capacitors. Top-off Charge Pump An additional top-off charge pump is provided for each phase. The charge pumps allow the high-side drives to maintain the gate voltage on the external FETs indefi- nitely, ensuring so-called 100% PWM if required. This is a low current trickle charge pump, and is operated only after a high-side FET has been signaled to turn on. The floating high-side gate drive requires a small bias current (<20 μA) to maintain the high- level output. Without the top-off charge pump, this bias current would be drawn from the bootstrap capacitor through the Cx pin. The charge pump provides sufficient current to ensure that the bootstrap voltage and thereby the gate-source voltage is main- tained at the necessary level. Note that the charge required for initial turn-on of the high-side gate is always supplied by the bootstrap capacitor. If the bootstrap capacitor becomes discharged, the top-off charge pump will not provide sufficient current to allow the FET to turn on. Functional Description

Automotive 3-Phase MOSFET DriverA4933 9Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. In some applications a safety resistor is added between the gate and source of each FET in the bridge. When a high-side FET is held in the on-state, the current through the associated high-side gate-source resistor (R GSH) is provided by the high-side drive and therefore appears as a static resistive load on the top-off charge pump. The minimum value of R GSH for which the top-off charge pump can provide current is shown in the Electrical Characteris- tics table. GLA, GLB, and GLC Pins These are the low-side gate drive outputs for the external N-channel MOSFETs. External resistors between the gate drive output and the gate connection to the FET (as close as possible to the FET) can be used to control the slew rate seen at the gate, thereby providing some control of the di/dt and dv/dt of the SA, SB, and SC outputs. GLx going high turns on the upper half of the drive, sourcing current to the gate of the low- side FET in the external power bridge, turning it on. GLx going low turns on the lower half of the drive, sinking current from the external FET gate circuit to the LSS pin, turning off the FET. SA, SB, and SC Pins Directly connected to the motor, these terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drives. The discharge current from the high-side FET gate capacitance flows through these connections, which should have low impedance circuit connections to the FET bridge. GHA, GHB, and GHC Pins These terminals are the high-side gate drive outputs for the external N-channel FETs. External resistors between the gate drive output and the gate connection to the FET (as close as possible to the FET) can be used to control the slew rate seen at the gate, thereby controlling the di/dt and dv/dt of the SA, SB, and SC outputs. GHx going high turns on the upper half of the drive, sourcing current to the gate of the high-side FET in the external motor-driving bridge, turning it on. GHx going low turns on the lower half of the drive, sinking current from the external FET gate circuit to the corresponding Sx pin, turning off the FET. CA, CB, and CC Pins These are the high-side connections for the bootstrap capacitors and are the positive supply for the high-side gate drives. The bootstrap capacitors are charged to approximately VREG when the associated output Sx terminal is low. When the Sx output swings high, the charge on the bootstrap capacitor causes the voltage at the corresponding Cx terminal to rise with the output to provide the boosted gate voltage needed for the high-side FETs. LSS Pin This is the low-side return path for discharge of the capacitance on the FET gates. It should be tied directly to the common sources of the low-side external FETs through an inde- pendent low impedance connection. RDEAD Pin This pin controls internal generation of dead time during FET switching.

  • When a resistor greater than 3 kΩ is connected between RDEAD and AGND, cross-conduction is prevented by the gate drive circuits, which introduce a dead time, t DEAD , between switching one FET off and the complementary FET on. The dead time is derived from the resistor value connected between the RDEAD and AGND pins.
  • When RDEAD is connected directly to VDD, cross-conduction is prevented by the gate drive circuits. In this case, t DEAD defaults to a value of 6 μs typical.
  • When RDEAD is connected directly to AGND, internal dead time generation is disabled. This allows dead times of any duration to be determined by the external controller through the relative timing of the phase logic control inputs, xHI and xLO. Note that when using an external controller to determine the dead time, care must be taken to ensure that unintentional shorts across the supply are avoided. Logic Control Inputs Low voltage-level digital inputs provide control for the gate drives. The input logic is shown in table 1. These logic inputs can be driven from either 3.3 or 5 V logic. All have a nominal hysteresis of 500 mV to improve noise perfor- mance. AHI, BHI, CHI, ALO, BLO, and CLO Pins These are the phase control inputs. The xHI inputs control the high-side drives and the xLO inputs control the low-side drives. Internal lockout logic ensures that the high-side output drive and low-side output drive cannot be active simultaneously, except when RDEAD is connected to AGND and at the same time CCEN is set high, as described in the CCEN pin section. PWMH and PWML Pins These inputs can be used to externally control motor torque and speed.
  • Setting PWMH low turns off active high-side drives and turns on the complementary low-side drives. This provides high- side–chopped slow-decay PWM with synchronous rectification.

Worcester, Massachusetts 01615-0036 U.S.A.

  • Setting PWML low turns off active low-side drives and turns on the complementary high-side drives. This provides low-side– chopped slow-decay PWM with synchronous rectification.
  • PWMH and PWML may also be connected together and driven with a single PWM signal. This provides fast-decay PWM with synchronous rectification. COAST Pin An active-low input, which forces low all gate drive outputs, GHx and GLx, and turns off all external FETs. This can be used to protect the FETs and the motor in the case of a short circuit. Using COAST does not clear any faults, so the fault flags can still be decoded and the fault register data word can be read. Because COAST turns off all the external FETs, it can also be used to provide fast-decay PWM without synchronous rectification. RESET Pin This is an active-low input, and when active it allows the A4933 to enter sleep mode. When RESET is held low for longer than the reset pulse time, t RES, the regulator and all internal circuitry are disabled and the A4933 enters sleep mode. During sleep mode, current consumption from the VBB and VDD supplies is reduced to a minimal level. In addition, latched faults and the corresponding fault flags are cleared. When the A4933 is coming out of sleep mode, the protection logic ensures that the gate drive outputs are off until the charge pump reaches its correct operating condition. The charge pump stabilizes in approximately 3 ms under nominal conditions. RESET can be used also to clear latched fault flags without entering sleep mode. To do so, hold RESET low for less then the reset pulse time, t RES. This clears any latched fault that disables the outputs, such as short circuit detection or bootstrap capacitor undervoltage, and also clears the fault register. Note that the A4933 can be configured to start without any exter- nal logic input. To do so, pull up the RESET pin to V BB by means of an external resistor. The resistor value should be between 20 and 33 kΩ. CCEN Pin This input provides an override to allow both the high- side and the low-side external FETs of any phase to be active at the same time, enabling cross-conduction. As an extra level of safety, cross-conduction can only occur when RDEAD is tied to AGND and CCEN is set high. If the CCEN input is inadvertently disconnected from the controller, an internal pull-down resistor ensures that the outputs revert to a safe condition. ESF Pin This is the Enable Stop on Fault input. It determines the action that is taken when certain faults are detected. See the Fault Protection and Diagnostics section for details.

Table 1. Phase Control Truth Table

Worcester, Massachusetts 01615-0036 U.S.A. PWM motor control during switching transients. and offset are provided in the Applications Information section. fault outputs as a serial data word. does not affect undervoltage fault condition actions. latched until RESET goes low or a serial read is completed. COAST input or all of the xHi and xLO phase control inputs. sients, the comparison is delayed by an internal blanking timer. the power bridge FETs at the positive supply connection point. VDSTH is the voltage on the VDSTH pin, in V . flag states for all detected faults. Table 2. Fault Definitions *Yes indicates all gate drives low, and all FETs off. when the fault is present, and the flag state will not be latched.

Automotive 3-Phase MOSFET DriverA4933 12Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. switching. Any short faults detected will always be latched in the fault register. When a short or undervoltage fault is present, a clock can be applied to FF2 and detailed fault information can be read from FF1 as a serial word. This can be used to determine on which of the six external FETs a short is being detected, or which of the monitored voltages have gone below their undervoltage threshold level. Fault register serial access operation is detailed in the Fault Register Serial Access section. Fault States Overtemperature If the junction temperature exceeds the over- temperature threshold, typically 165°C, the A4933 will enter the overtemperature fault state and FF1 will go high. The overtem- perature fault state, and FF1, will only be cleared when the tem- perature drops below the recovery level defined by T JF – TJFhys . Note that an overtemperature fault does not permit access to the fault register because FF2 is pulled low. If ESF is set high when an overtemperature is detected, the out- puts will be disabled automatically while the fault state is present. If ESF is set low, then no circuitry will be disabled. In this case external control circuits must take action to limit the power dis- sipation in some way so as to prevent overtemperature damage to the chip and unpredictable device operation. VREG Undervoltage VREG supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are sufficiently high before enabling any of the outputs. If the voltage at VREG, V REG , drops below the falling VREG undervoltage lockout threshold, VREGUV off , then the A4933 will enter the VREG undervoltage fault state. In this fault state, both FF1 and FF2 will be high, and the outputs will be disabled. The VREG undervoltage fault state and the fault flags will be cleared when V REG rises above the rising VREG undervoltage lockout threshold, VREGUV on. The VREG undervoltage monitor circuit is active during power-up, and the A4933 remains in the VREG undervoltage fault state until V REG is greater than the rising VREG undervolt- age lockout threshold, VREGUV on. Any time the A4933 enters the VREG undervoltage fault state, bit 7 in the fault register will be set and will remain set until cleared by a register reset (see the Fault Register Serial Access section). Bootstrap Capacitor Undervoltage The A4933 monitors the voltage across the individual bootstrap capacitors to ensure they have sufficient charge to supply the current pulse for the high- side drive. Before a high-side drive can be turned on, the voltage across the associated bootstrap capacitor must be higher than the turn-on voltage limit. If this is not the case, then the A4933 will start a bootstrap charge cycle by activating the complementary low-side drive. Under normal circumstances, this will charge the bootstrap capacitor above the turn-on voltage in a few microsec- onds and the high-side drive will then be enabled. The bootstrap voltage monitor remains active while the high-side drive is active and if the voltage drops below the turn-off voltage a charge cycle is initiated. In either case, if there is a fault that prevents the bootstrap capaci- tor charging, then the charge cycle will timeout, the fault flags (indicating an undervoltage) will be set, and the outputs will be disabled. In addition, the appropriate bit in the fault register will be set. This allows the specific phase giving the bootstrap under- voltage to be determined by reading the serial data word. The bootstrap undervoltage fault state remains latched until RESET is set low or a serial read of the fault register is com- pleted. VDD Undervoltage The logic supply voltage at VDD is moni- tored to ensure correct logical operation. If an undervoltage on VDD is detected, the outputs will be disabled. In addition, because the state of other reported faults cannot be guaranteed, all fault states, fault flags, and the fault register are reset and replaced by the fault flags corresponding to a VDD undervoltage fault state. For example, a VDD undervoltage will reset an exist- ing short circuit fault condition and replace it with a VDD under- voltage fault. When the VDD undervoltage condition is removed, all flags will be cleared and the outputs enabled. Short Fault Operation Shorts in the power bridge are determined by monitoring the drain-souce voltage, VDS , of each active FET and comparing it to the fault threshold voltage at the VDSTH pin. Because power MOSFETs take a finite time to reach the rated on- resistance, the measured drain-source voltages will show a fault as the phase switches. To avoid such false short fault detections,

Automotive 3-Phase MOSFET DriverA4933 13Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. the output from the comparators are ignored under two condi- tions: ▪ while the external FET is off, and ▪ until the end of the period, referred to as the fault blank time, after the FET is turned on. When the FET is turned on, if the drain-source voltage exceeds the voltage at the VDSTH pin at any time after the fault blank time, then a short fault will be detected. If also ESF is set high, then this fault will be latched and the FET disabled until reset. In some applications, the fault blank time may be insufficient to avoid detecting false faults during the switching time of the exter- nal FET. In these cases, the external controller driving the A4933 may be used to determine the correct fault condition by setting ESF low. This will prevent latching of the fault flag when a short fault is detected, and will not disable the FET. With ESF low, FF2 will remain high only while the measured V DS exceeds the fault threshold. The external controller can then monitor the fault flags and use its own timers to validate a fault condition. Note that any fault thus detected by the A4933 will still be latched in the fault register and remain there until cleared. When ESF is set low, the external FETs are not disabled by the A4933 when a short fault is detected. To avoid permanent dam- age to the external FETs or to the motor under this condition, the A4933 can either be fully disabled by the RESET input or all FETs can be switched off by pulling low the COAST input or all the phase control inputs. Short to Supply A short from any of the motor phase connec- tions to the battery or VBB connection is detected by monitoring the voltage across the low-side FETs in each phase, using the appropriate Sx pin and the LSS pin. This drain-source voltage, V DS, is continuously compared to the voltage on the VDSTH pin. The result of this comparison is ignored if the FET is not active. It is ignored also for one fault blank time interval after the FET is turned on. If, when the comparator is not being ignored, its output indicates that VDS exceeds the voltage at the VDSTH pin, then FF2 will be high. If also ESF is set high, then FF2 will be latched high and the outputs will be disabled. Alternatively, if also ESF is set low, then the outputs will not be disabled and FF2 will only be high while the output of the comparator indicates that VDS exceeds the voltage at the VDSTH pin. Short to Ground A short from any of the motor phase connec- tions to ground is detected by monitoring the voltage across the high-side FETs in each phase, using the appropriate Sx pin and the voltage at VDRAIN. This drain-source voltage, V DS , is con- tinuously compared to the voltage on the VDSTH pin. The result of this comparison is ignored if the FET is not active. It is ignored also for one fault blank time interval after the FET is turned on. If, when the comparator is not being ignored, its output indicates that V DS exceeds the voltage at the VDSTH pin, FF2 will be high. If also ESF is set high, FF2 will be latched high and the outputs will be disabled. Alternatively, if also ESF is set low, the outputs will not be disabled and FF2 will only be high while the output of the comparator indicates that V DS exceeds the voltage at the VDSTH pin. Shorted Load The short-to-ground and short-to-supply monitor circuits will also detect a short across a motor phase winding. In most cases, a shorted winding will be indicated by a high-side and low-side fault being detected at the same time. In some cases the relative impedances may permit only one of the shorts to be detected. Differentiating Short Fault Conditions The distinction between short-to-ground, short-to-supply, and shorted load can only be made by examining the contents of the fault register. It is not possible to determine where a short fault has occurred when using the state of the fault flags, FF1 and FF2, alone. The flag combination FF1 low and FF2 high simply indicates the presence of a probable short circuit. As described above, shorts are detected by monitoring the drain- source voltage, V DS , of each of the six FETs in the power bridge. The different short fault conditions are defined as follows: ▪ A short-to-ground is likely to be present if the VDS of any active high-side FET is greater than the threshold defined by VDSTH (fault bits AH, BH, or CH = 1) ▪ A short-to-supply is likely to be present if the VDS of any active low-side FET is greater than the threshold defined by VDSTH (fault bits AL, BL, or CL = 1) ▪ A shorted load or phase is likely to be present if, at the same time, the V DS of an active high-side and an active low-side are both greater than the threshold defined by VDSTH.

Worcester, Massachusetts 01615-0036 U.S.A. but all the bits in the fault register will be reset. Table 3. Fault Register Bit Definitions undervoltage or short fault state. status register, bit-by-bit, on the other fault flag, FF1. undervoltage fault has been detected.

  1. The external controller takes any necessary additional action to
  2. The external controller pulls FF2 low.
  3. The A4933 outputs on FF1 the fault register first bit, AH.
  4. The external controller reads the fault bit, and then cycles FF2

high then low for the next bit, BH.

  1. Steps 3 and 4 alternate until all of the 10 bits in the fault regis-
  2. After the final bit, VC, is output, the external controller cycles
  3. The A4933 resets the fault register and pulls FF1 and FF2 low

to indicate no fault present.

  1. The external controller releases FF2.

Worcester, Massachusetts 01615-0036 U.S.A. Figure 1. Fault flag sequence diagrams

Worcester, Massachusetts 01615-0036 U.S.A. provide synchronous rectification. side FETs, as shown in figure 2B. held high and the PWM signal is applied to PWML.

11 PWML

Figure 2. Power bridge current paths

Worcester, Massachusetts 01615-0036 U.S.A. a PWM duty cycle of 50% results in zero effective motor torque. and greater than 50% causes positive effective torque. DEAD) between the RDEAD and AGND pins. of RDEAD between 6 and 60 kΩ, which are shown in figure 3. 6 μs typical, can be set by connecting the RDEAD and VDD pins. tance, and the on-resistance of the A4933 internal drives. Figure 3. Dead time versus RDEAD

Automotive 3-Phase MOSFET DriverA4933 18Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. is set to zero by connecting RDEAD to AGND, the fault blank time typically defaults to 2 μs. Cross-Conduction In some circumstances it is desirable to allow activation of both high-side and low-side FETs in a single phase of the power bridge. This can be used, with care, to reduce diode conduction during synchronous rectification, which improves overall effi- ciency and reduces electromagnetic emissions. This mode of operation is also useful for independently control- ling each phase of a VR motor or to turn on all high-side and low- side FETs together, to cause a supply short circuit for blowing a safety fuse. Cross-conduction can occur only when the internally-generated dead time is set to zero by connecting RDEAD to AGND and, at the same time, CCEN is high. If zero internally-generated dead time is required, but cross-conduction is to be prevented, then CCEN can be tied to AGND. When the dead time is set to zero it is still possible for some overlap to be present at the switching instants due to the relative switching time of the FETs. Bootstrap Capacitor Selection The bootstrap capacitors, C BOOTx, must be correctly selected to ensure proper operation of the A4933. If the capacitances are too high, time will be wasted charging the capacitor, resulting in a limit on the maximum duty cycle and the PWM frequency. If the capacitances are too low, there can be a large voltage drop at the time the charge is transferred from C BOOTx to the FET gate, due to charge sharing. To keep this voltage drop small, the charge in the bootstrap capacitor, QBOOT, should be much larger than the charge required by the gate of the FET, QGATE. A factor of 20 is a reasonable value, and the following formula can be used to calculate the value for C BOOT : QBOOT CBOOT × VBOOT = QGATE × 20 , = therefore: QGATE × 20 , VBOOT CBOOT = (3) where VBOOT is the voltage across the bootstrap capacitor. The voltage drop across the bootstrap capacitor as the FET is being turned on, ∆V , can be approximated by: QGATE . CBOOT ∆V ≈ (4) So, for a factor of 20, ∆V would be approximately 5% of VBOOT . The maximum voltage across the bootstrap capacitor under normal operating conditions is VREG(max). However, in some circumstances the voltage may transiently reach 18 V , the clamp voltage of the Zener diodes between the Cx and Sx pins. In most applications, with a good ceramic capacitor the working voltage can be limited to 16 V . Bootstrap Charging It is good practice to ensure the high-side bootstrap capacitor is completely charged before a high-side PWM cycle is requested. The time required to charge the capacitor, t CHARGE (μs), is approximated by: CBOOT × ∆V , 500=tCHARGE (5) where CBOOT is the value of the bootstrap capacitor, in nF, and ∆V is the required voltage of the bootstrap capacitor. At power-up and when the drives have been disabled for a long time, the bootstrap capacitor can be completely discharged. In this case ∆V can be considered to be the full high-side drive voltage, 12 V . Otherwise, ∆V is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the Sx pin is pulled low and current flows from VREG through the internal bootstrap diode circuit to C BOOT. Bootstrap Charge Management The A4933 provides automatic bootstrap capacitor charge management. The bootstrap capacitor voltage for each phase is continuously checked to ensure that it is above the bootstrap under-voltage threshold, V BOOTUV. If the bootstrap capacitor volt- age drops below this threshold, the A4933 will turn on the neces- sary low-side FET, and continue charging until the bootstrap capacitor exceeds the undervoltage threshold plus the hysteresis, V BOOTUV + VBOOTUVhys. The minimum charge time is typically 7 μs, but may be longer for very large values of bootstrap capaci-

Automotive 3-Phase MOSFET DriverA4933 19Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. tor (>1000 nF). If the bootstrap capacitor voltage does not reach the threshold within approximately 200 μs, an undervoltage fault will be flagged. VREG Capacitor Selection The internal reference, VREG, supplies current for the low-side gate drive circuits and the charging current for the bootstrap capacitors. When a low-side FET is turned on, the gate-drive circuit will provide the high transient current to the gate that is necessary to turn on the FET quickly. This current, which can be several hundred milliamperes, cannot be provided directly by the limited output of the VREG regulator, and must be supplied by an external capacitor connected to VREG. The turn-on current for the high-side FET is similar in value to that for the low-side FET, but is mainly supplied by the boot- strap capacitor. However the bootstrap capacitor must then be recharged from the VREG regulator output. Unfortunately the bootstrap recharge can occur a very short time after the low- side turn-on occurs. This requires that the value of the capacitor connected between VREG and AGND should be high enough to minimize the transient voltage drop on VREG for the combina- tion of a low-side FET turn-on and a bootstrap capacitor recharge. A value of 20 × C BOOT is a reasonable value. The maximum working voltage will never exceed VREG , so the capacitor can be rated as low as 15 V . This capacitor should be placed as close as possible to the VREG pin. Supply Decoupling Because this is a switching circuit, there are current spikes from all supplies at the switching points. As with all such circuits, the power supply connections should be decoupled with a ceramic capacitor, typically 100 nF, between the supply pin and ground. These capaci- tors should be connected as close as possible to the device supply pins VBB and VDD, and the power ground pin, PGND. Power Dissipation In applications where a high ambient temperature is expected, the on-chip power dissipation may become a critical factor. Careful attention should be paid to ensure the operating conditions allow the A4933 to remain in a safe range of junction temperature. The power consumed by the A4933, P D, can be estimated by: PD PBIAS + PCPUMP + PSWITCHING ,= (6) given: PBIAS VBB × IBB ;= (7) PCPUMP or [( 2 VBB) – VREG] IAV , for VBB < 15 V , = [VBB – VREG] IAV , for VBB ≥ 15 V , = (8) PSWITCHING QGATE × VREG × N × fPWM × Ratio ; = (9) where: IAV QGATE × N × fPWM , = N is the number of FETs switching during a PWM cycle, and Ratio RGATE + 10 .10= Braking The A4933 can be used to perform dynamic braking by either forcing all low-side FETs on and all high-side FETs off or, con- versely, by forcing all low-side FETs off and all high-side FETs on. This will effectively short-circuit the back EMF of the motor, creating a breaking torque. During braking, the load current can be approximated by: VBEMF , RL IBRAKE = (10) where VBEMF is the voltage generated by the motor and RL is the resistance of the phase winding. Care must be taken during braking to ensure that the maximum ratings of the power FETs are not exceeded. Dynamic braking is equivalent to slow decay with synchronous rectification and all phases enabled.

Worcester, Massachusetts 01615-0036 U.S.A. The A4933 can also be used to perform regenerative braking. current to a battery or capacitor. impedances seen from either end of the sense resistor match.

  • The A4933 analog ground, AGND, and power ground, PGND, should be connected together at the package pins. This common point, and the high-current return of the external FETs, should return separately to the negative side of the motor supply filtering capacitor. This will minimize the effect of switching noise on the device logic and analog reference.
  • The exposed thermal pad and all NC pins of the package should be connected to the common point of AGND and PGND.
  • Minimize stray inductance by using short, wide copper traces at the drain and source terminals of all power FETs. This includes motor lead connections, the input power bus, and the common source of the low-side power FETs. This will minimize voltages induced by fast switching of large load currents.
  • Consider the use of small (100 nF) ceramic decoupling capacitors across the sources and drains of the power FETs to limit fast transient voltage spikes caused by the inductance of the circuit trace.
  • Keep the gate discharge return connections Sx and LSS as short as possible. Any inductance on these traces will cause negative transitions on the corresponding A4933 pins, which may exceed the absolute maximum ratings. If this is likely, consider the use of clamping diodes to limit the negative excursion on these pins with respect to AGND. CSN CSP CSOUT 80 kΩ 4 kΩ 4 kΩ 4 kΩ 76 kΩ RS G = 20 VOS= 250 mV CSN CSP CSOUT A4933 A4933 RF RP RN RG RS G = RF / RN RG = RF RP = RN 5 V 76 kΩ (A) Basic configuration

Figure 4. Current sense amplifier configurations

Worcester, Massachusetts 01615-0036 U.S.A.

  • Sensitive connections such as RDEAD and VDSTH, which have very little ground current, should be connected to the Quiet ground (refer to figure 5), which is connected independently, closest to the AGND pin. These sensitive components should never be connected directly to the supply common or to a common ground plane. They must be referenced directly to the AGND pin.
  • The supply decoupling for VBB, VREG, and VDD should be connected to the Controller Supply ground, which is connected independently, close to the PGND pin. The decoupling capacitors should also be connected as close as practicable to the relevant supply pin.
  • If layout space is limited, then the Quiet ground and the Controller Supply ground may be combined. In this case, ensure that the ground return of the dead time resistor is close to the AGND pin.
  • Check the peak voltage excursion of the transients on the LSS pin with reference to the AGND pin, using a close grounded (tip and barrel) probe. If the voltage at LSS exceeds the absolute maximum shown in this datasheet, add additional clamping and capacitance between the LSS pin and the AGND pin as shown in figure 5.
  • Gate charge drive paths and gate discharge return paths may carry a large transient current pulse. Therefore, the traces from GHx, GLx, Sx, and LSS should be as short as possible to reduce the circuit trace inductance.
  • Provide an independent connection from LSS to the common point of the power bridge. It is not recommended to connect LSS directly to an xGND pin, as this may inject noise into sensitive functions such as the timer for dead time. The LSS connection should not be used for the CSP connection.
  • The inputs to the sense amplifier, CSP and CSN, should have independent circuit traces. For best results, they should be matched in length and route.
  • A low-cost diode can be placed in the connection to VBB to provide reverse battery protection. In reverse battery conditions, it is possible to use the body diodes of the power FETs to clamp the reverse voltage to approximately 4 V . In this case, the additional diode in the VBB connection will prevent damage to the A4933 and the VDRAIN input will survive the reverse voltage. Note that the above are only recommendations. Each application is different and may encounter different sensitivities. A driver running a few amps will be less susceptible than one running with

150 A, and each design should be tested at the maximum current

to ensure any parasitic effects are eliminated. Figure 5. Supply routing suggestions

Automotive 3-Phase MOSFET DriverA4933 22Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. VDRAIN 19 V 19 V 20 V VBB 18 V 18 V 18 V VDD 6 V CP1 18 V CP2 VREG 1 kΩ 8.5 V ESF COAST PWMx xHI xLO 3 kΩ FF2 ESD RESET 3 kΩ

6 V 6 V

50 kΩ50 kΩ CSN CSP

22 V 22 V

CSOUT 4 kΩ 4 kΩ 8.5 V 8.5 V VDSTHRDEAD 100 Ω 8.5 V 1.2 V ESD CCEN 3 kΩ 10 Ω 3 kΩ 8.5 V ESD ESD ESD ESD ESD FF1 ESD 10 Ω Cx 18 V GHx Sx GLx LSS 20 V 18 V 18 V 18 V 18 V 18 V VREG Input and Output Structures (A) Gate drive outputs (B) Supply protection structures (C) Fault output (D) Fault input/output (E) Logic inputs, no pulldown (F) Logic input, with pulldown (I) RDEAD (H) Current sense amplifier (G) RESET input (J) VDS monitor threshold input

Automotive 3-Phase MOSFET DriverA4933 23Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. NC RESET ESF FF2 FF1 ALO AHI BHI BLO CLO CHI PWML SA GLA PAD CB GHB SB GLB CC GHC SC NC NC NC CCEN PWMH COAST CSOUT VDD CSN CSP VDSTH LSS GLC AGND NC RDEAD AGND VBB PGND CP1 CP2 NC VDRAIN VREG CA GHA NC Pin Pin Name Pin Description 1, 24, 25, 35, 36, 37, 42 NC No internal connection; connect to AGND

2 RESET Standby mode control

3 ESF Enable Stop on Fault input

4 FF2 Fault Flag 2 and serial clock input

5 FF1 Fault Flag 1 and serial data output

6 ALO Control input phase A low-side

7 AHI Control input phase A high-side

8 BHI Control input phase B high-side

9 BLO Control input phase B low-side

10 CLO Control input phase C low-side

11 CHI Control input phase C high-side

12 PWML Low-side PWM input

13 CCEN Cross-conduction enable

14 PWMH High-side PWM input

15 COAST Coast input

16 CSOUT Current sense output

17 VDD Logic supply

18 CSN Current sense negative input

19 CSP Current sense positive input

20 VDSTH Fault threshold voltage

21 LSS Low-side source

Pin Pin Name Pin Description

22 GLC Low-side gate drive phase C

23 AGND Analog ground

26 SC Motor connection phase C

27 GHC High-side gate drive phase C

28 CC Bootstrap capacitor phase C

29 GLB Low-side gate drive phase B

30 SB Motor connection phase B

31 GHB High-side gate drive phase B

32 CB Bootstrap capacitor phase B

33 GLA Low-side gate drive phase A

34 SA Motor connection phase A

38 GHA High-side gate drive phase A

39 CA Bootstrap capacitor phase A

40 VREG Gate drive supply output

41 VDRAIN High-side drain voltage sense

43 CP2 Pump capacitor

44 CP1 Pump capacitor

45 PGND Power ground

46 VBB Main power supply

47 AGND Analog ground

48 RDEAD Dead time setting

– PAD Exposed thermal pad; connect to AGND

Automotive 3-Phase MOSFET DriverA4933 24Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package JP 48-Pin LQFP with Exposed Thermal Pad A Exposed thermal pad (bottom surface) Terminal #1 mark area B B A CSEATING PLANEC0.08 48X GAGE PLANE SEATING PLANE 5.00±0.04 5.00±0.04

1.60 MAX

0.50 5.00 8.60 0.30 1.70 8.60 5.00 For Reference Only (reference JEDEC MS-026 BBCHD) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown1.40 ±0.05 0.10 ±0.05 0.22 ±0.05 9.00 ±0.20 7.00 ±0.20 0.50 PCB Layout Reference ViewC 0.25 (1.00) 0.60 ±0.15 4° ±4 0.15 +0.05 –0.06 C Reference land pattern layout (reference IPC7351 QFP50P900X900X160-48M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C

Automotive 3-Phase MOSFET DriverA4933 25Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Copyright ©2010-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com