A4490

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Description

Designed to provide the power supply requirements of printers, office automation, industrial, and portable equipment, the A4490 provides three high current, high performance, switching regulator outputs with independent soft start. High frequency switching allows selection of inexpensive inductors and small ceramic output capacitors. The turn-on cycles of the regulators are interleaved to minimize stresses on the input capacitors and to reduce EMI. A charge pump is used to provide the supply for driving the power switches, ensuring operation at very wide operating duty cycles and avoiding the need for power-draining clamp circuits. A power-on-reset circuit with user configurable delay indicates when enabled regulators are in specification. The power-on- reset flag also indicates when the input voltage drops below specification, giving the system controller advance warning while the switchers continue to operate down to the shutdown level. Internal diagnostics provide comprehensive protection against overloads, input undervoltages, and overtemperatures. 4490-DS, Rev. 9 Features and Benefits ▪ Three buck converters ▪ 4.5 to 34 V input voltage range ▪ 550 kHz fixed frequency ▪ Multiphase switching ▪ Independent control of each converter ▪ Power-on-reset flag ▪ Internal compensation ▪ 4 × 4 mm QFN Package, small PCB footprint Triple Output Step-Down Switching Regulator Package: 20-contact QFN (suffix ES) A4490 Approximate size Continued on the next page… Microcontroller or Controller Logic VBB GND CP1 CP2 VCP PGND PORZ ENB1 ENB2 ENB3 CPOR V REG1 VREG2 VREG3 VDD A4490 VBB2 LX2 FB2 VBB3 LX3 FB3 VBB1 LX1 FB1 Typical Application

Triple Output Step-Down Switching RegulatorA4490 2Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. The A4490 is provided in a 20-contact, 4 mm × 4 mm, 0.75 mm nominal overall height QFN, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. Applications include the following: ▪ Photo, inkjet, and portable printers ▪ Industrial ▪ Hand-held devices ▪ Portable applications Description (continued) Selection Guide Part Number Packing Operating Temperature Range (°C) A4490EESTR-T 1500 pieces per 7-in. reel –40 to 85 Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 37 ºC/W *Additional thermal information available on the Allegro website. Absolute Maximum Ratings (reference to GND) Characteristic Symbol Notes Rating Units Load Supply Voltage V BB 36 V LX1, LX2, and LX3 Pins V LXn –1 to 36 V PORZ and VDD Pins V IN –0.3 to 7 V ENBx Pin Input Current I ENBx Driven by a current-limited voltage source 1 mA Operating Ambient Temperature T A Range E –40 to 85 ºC Maximum Junction Temperature T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC Recommended Operating Conditions Characteristic Symbol Conditions Min. Typ. Max. Units Load Supply Voltage V BB To operate at VBB < 6 V, connect VDD supply to the VBB supply. See Powering Configurations section. 4.5 – 34 V LX1, LX2, and LX3 Pins V LXn –0.7 – 34 V Operating Ambient Temperature T A –40 – 85 ºC Junction Temperature T J –40 – 125 ºC

Triple Output Step-Down Switching RegulatorA4490 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Functional Block Diagram ENB2 FB2 GND Switcher #2 PWM Control LX2 5 V / 1.5 A VBB3 FB3 LX3 3.3 V / 1.5 A Switcher #3 PWM Control ENB1 4.7 μH 10 μF 10 μH ENB3 PORZ VBB1 FB1 Switcher #1 PWM Control LX1 VCP VBB Bias Supply PGND VCP VCP SS SS SS CP1 CP2 Charge Pump VCP RegulatorVDD Switch POR Block CPOR VBB C10 C14 10 μF 10 μF C11 10 μF C12 10 μF C13 10 μF 15 μH 100 nF 47 nF 47 nF 470 nF 10 μF VREG1 VREG2 VREG3 1.0 V / 1.5 A 10 μF 10 μF VBB2 10 μF VBB VDD 100 k Ω Note: All capacitors ceramic X5R.

Triple Output Step-Down Switching RegulatorA4490 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Terminal List Number Name Function

1 FB1 Feedback REG1

2 VDD Bias supply

3 GND

1 Ground

4 FB2 Feedback REG2

5 ENB2 Enable REG2, logic input, active high

6 LX2 Switch node REG2

7 VBB2

2 Input supply for REG2

8 CPOR POR delay adjustment

9 PORZ Power on reset output, active low

10 VCP Charge pump reservoir

11 CP2 Charge pump capacitor terminal

12 CP1 Charge pump capacitor terminal

13 PGND

1 Ground for charge pump circuitry

14 FB3 Feedback REG3

15 ENB3 Enable REG3, logic input, active high

16 LX3 Switch node REG3

17 VBB3

2 Input supply for REG3

18 VBB1 2 Input supply for REG1

19 LX1 Switch node REG1

20 ENB1 Enable REG1, logic input, active high

–P A D 3 Exposed pad for enhanced thermal dissipation 1GND and PGND should be connected externally. 2The three VBBx pins should be connected together externally. 3Thermal pad should be connected to the ground (0 V) plane using thermal vias. PAD ENB1 LX1 VBB1 VBB3 LX3 LX2 VBB2 CPOR PORZ VCP ENB3 FB3 PGND CP1 CP2 FB1 VDD GND FB2 ENB2 Pin-out Diagram

Triple Output Step-Down Switching RegulatorA4490 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VBB = 6.0 to 34 V, VDD supplied externally, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit General VBB Quiescent Current IBBON ENBx = high, ILOAD = 0 mA, VBB = 12 V, current drawn by feedback resistors ignored – 1 2 mA IBBOFF ENBx = 0 V – 1 – μA VDD Supply Range V DD 3.3 – 5.5 V VDD Quiescent Current I DD ENBx = high – – 5 mA ENBx = 0 V – 1 – μA REG1, REG2, and REG3 Feedback Input Bias Current I BIAS –400 –100 100 nA Feedback Voltage V FB With respect to 0.8 V target voltage – ±1.5 – % Output Voltage Regulation3 VOUT VREGx = 5 V, IOUT = 0 to 1.5 A, TA = –20°C to 85°C –2.5 – 2.5 % VREGx = 5 V, IOUT = 0 to 1.5 A, TA = –40°C to 85°C –3.5 – 3.5 % PWM Frequency f SW 470 550 630 kHz Maximum Duty Cycle D max 90 – – % Minimum Duty Cycle D min – 5 – % Buck Switch On-Resistance R DS(on) TJ = 25°C, ILOAD = 1.5 A, VBB = 6.0 V – 450 – m Ω TJ = 125°C, ILOAD = 1.5 A, VBB = 6.0 V – 700 – m Ω TJ = 25°C, ILOAD = 1.5 A, VBB = 4.5 V – 560 – m Ω TJ = 125°C, ILOAD = 1.5 A, VBB = 4.5 V – 870 – m Ω Current Limit Threshold I LIM Peak current through switch with D = 0.9 2.0 A Soft Start Duration t ss 0.625 1.25 1.875 ms Logic Inputs and Outputs ENBx Input Voltage VIL – – 0.8 V VIH 2.0 – – V ENBx Input Hysteresis V I(hys) 300 500 – mV ENBx Input Current I IL V IH ≤ 5 V –1 – 1 μA PORZ Output (Open Drain) V PORZL I PORZL = 1 mA, fault asserted – – 0.4 V PORZ Output Leakage Current I PORZH V PORZ = 5 V, fault not asserted –1 – 1 μA Power-On Reset Duration t POR C POR = 470 nF 75 115 155 ms Continued on the next page…

Triple Output Step-Down Switching RegulatorA4490 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Protection VREGx Undervoltage Lockout Startup V REGUV(su) FB1, FB2, and FB3 rising – 85 – %V FB VREGx Undervoltage Lockout Shutdown V REGUV(sd) FB1, FB2, and FB3 falling – 80 – %V FB VREGx Undervoltage Lockout Startup Hysteresis VREGUV(suhys) –5 – % VBB Undervoltage Lockout Startup VBBUV(su) No external VDD supply, V BB rising 3.9 4.3 4.6 V VBBCPUV(su) External VDD supply, V BB rising 3.9 4.2 4.4 V VBB Undervoltage Lockout Shutdown VBBUV(sd) No external VDD supply, V BB falling 3.7 4.1 4.5 V VBBCPUV(sd) External VDD supply, V BB falling 3.0 3.5 4.1 V VBB Undervoltage Lockout Shutdown Hysteresis VBBUV(sdhys) No external VDD supply – 500 – mV VBBCPUV(sdhys) External VDD supply – 600 – mV VBB Undervoltage Warning Threshold V BBUV(por) VBB falling (forces PORZ low); switchers continue to operate – 3.6 – V Junction Overtemperature Shutdown T JTSD Temperature rising – 165 – °C Junction Overtemperature Shutdown Hysteresis TJTSD(hys) Recovery = T JTSD –TJTSD(hys) – 15 – °C 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin. 2Specifications over the junction temperature range of –40°C to 125°C are assured by design and characterization. 3Average value of VOUT relative to target voltage. The effects of the feedback resistors are not taken into account. ELECTRICAL CHARACTERISTICS1,2 (continued) at TA = 25°C, VBB = 6.0 to 34 V, VDD supplied externally, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Triple Output Step-Down Switching RegulatorA4490 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Basic Operation The A4490 contains three fixed frequency, buck switching con- verters with peak current-mode control, including slope compen- sation. Each converter can be independently turned on and off via the enable inputs (EN1, EN2, and EN3), which are active high. When enabled, the corresponding output is brought-up under the control of a soft start routine, which avoids output voltage over- shoot and minimizes input inrush current. The output voltage is typically divided down by an external potential divider, and is compared against an internal reference voltage to produce an error signal, also known as the current demand signal. The current signal through the buck switch is converted into a voltage. This signal is then compared against the current demand signal to create the required duty cycle. At the beginning of each switching cycle, the buck switch is turned on. When the current signal through the switch reaches the level of the current demand signal, the on-time of the switch is terminated. On the next switching cycle, the switch is turned on again and the cycle is repeated. One shared clock is used to define the switching frequency for each regulator. Each of the three switching cycles (REG1, REG2, and REG3) are phase shifted with respect to one another by 120° in an attempt to minimize the pulsed current drawn from the input filter capacitors. Under certain conditions, for example at low V BB conditions and relatively high user-set output voltages, switching overlap between channels is inevitable. Under conditions, such as light loads or high VBB voltages, that cause duty cycles (DC) of less than the minimum value, the converter enters a pulse-skipping mode to ensure regulation is maintained. A charge pump regulator is provided to ensure a sufficient gate drive is available for all three power switches across the full input voltage range. This regulator allows operation even at very wide operating duty cycles. On initial power-up, an internal regulator is used to provide the bias supply for on-chip control functions. Each regulator channel utilizes pulse-by-pulse current limiting in the event of either a short circuit or an overload. If the overload is applied long enough, the IC temperature may rise sufficiently to cause the thermal shutdown circuit to operate. The part will auto-restart under control of the soft start circuit after the thermal disable condition is removed, and assuming all other conditions are met. See the Shutdown section for more information. Power Configuration The A4490 supports alternative schemes for providing logic sup- ply voltage on the VDD pin. In addition, the IC can be powered up and down using either the VBB or ENB pins. Powering VDD To minimize power dissipation, especially at high input voltages, it is recommended that an external sup- ply be applied to the VDD input pin. Typically, this voltage is derived from one of the three regulated outputs that are set-up for between 3.3 and 5 V (V REGx). Another advantage of powering the VDD externally is that the VBB undervoltage lockout level is lowered. To maximize the run time of the switchers during a VBB power-down condition, two alternative undervoltage shutdown conditions are supported, depending on which VDD-powering configuration has been implemented. When no external VDD is applied, the minimum V BB, VBBUV(sd) , is 4.1 V typical. When an external VDD is applied, the minimum VBB, VBBCPUV(sd) , is 3.5 V typical. One note of caution when deriving VDD from a VREG output: during initial application of VBB, the internal bias supply auto- matically starts from the internal regulator because VREG has not yet reached regulation. This means the startup threshold is deter- mined by V BBUV(su) (4.3 V typical) because there is no external VDD. When VREG has begun to supply VDD externally, the shutdown threshold reduces to V BBCPUV(sd) (3.5 V typical). This assumes that VREG is present. Powering Up and Down with VBB Referring to figure 1, each of the enable inputs (ENBx) are held high by being tied to the V BB rail via a 100 kΩ resistor and the VDD is supplied from one of the regulator outputs. When the VBB voltage reaches the minimum threshold, VBBUV(su) , the charge pump supply (VCP) ramps up. When VBB + VCP has reached the minimum thresh- old VBBCPUV(su), the soft start routines are initiated (tSS) for all three regulator channels (VREGx). When all three regulators have reached the 85% FBx threshold, the power-on-reset timer is initiated. After the power-on-reset period, t POR , has elapsed, PORZ goes high, indicating that all the regulators and VBB are in specification. Functional Description

Worcester, Massachusetts 01615-0036 U.S.A. Figure 1. Timing diagram for powering up and down using the VBB pin Figure 2. Timing diagram for powering up and down using the ENB pin

Triple Output Step-Down Switching RegulatorA4490 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. When the VBB voltage starts to fall below the undervoltage warn- ing level, VBBUV(por) , of 3.6 V typical, the PORZ flag resets. This gives advance warning to the system controller that the VBB voltage is falling. Note that this feature is only guaranteed when VDD is supplied externally. During this interval, the three switch- ers continue to operate. While V BB falls further, the VCP supply also tends to fall, which degrades the drive voltage to the series switches. In addition, the higher voltage rails start to fall out of regulation first, as the corresponding maximum duty cycle (D max) for these particular converters is reached. The regulators that have the lower output voltages achieve some level of steady state, before the A4490 powers down when all of the corresponding V BB undervoltage thresholds have been reached. For example, it may be possible for a 1 V output to continue to operate down to a V BB of 3.4 V typical, if the VDD supply is derived externally. The extent of this effect depends on a myriad of factors, including input and output filter capacitance, output loads, gate drive amplitude, MOSFET R DS(on), and so forth. Powering Up and Down with Enable Referring to figure 2, VBB is present and the UVLO start-up thresholds, VBBUV(su) and VBBCPUV(su) have been reached. Each of the regulators are enabled in turn. Initially, VREG1 is enabled and is brought-up under the control of the soft start circuit (t SS). Before VREG1 reaches 85% FB1, VREG2 is enabled and is brought-up under a separate soft start control. When both regulators have reached their respective 85% FB thresholds, the power-on-reset (POR) timer is initiated. Note that the POR timer is only enabled after all of the enabled regulators reach their corresponding 85% FB levels. After the power-on- reset time, t POR , has elapsed, if the FB levels of VREG1 and VREG2 are not below their respective 80% FB levels, then the PORZ signal will go high. At some point later, if VREG3 is enabled, then the PORZ is reset and VREG3 is brought-up under the control of the soft start circuit. When the 85% FB3 threshold is reached, the POR timer is initiated. After t POR has elapsed, if all the FB levels are above their respective 80% FB levels, then the PORZ signal will go high. Note that if any regulator channel is not enabled, the channel will not influence PORZ. To avoid multiple signal changes of the PORZ signal, it is recommended that the system be designed such that all three regulator channels are within specification before t POR has elapsed. If any regulator channel drops below 80% FB, the PORZ signal will be reset. If the voltage then recovers to within 85% FB, the POR timer is initiated again. Note that a soft start is not initiated when the feedback voltage drops below the 80% FB level. This is to allow a rapid auto-restart in the event of an overload or similar fault. If a soft start is required, it is recommended that on receipt of the PORZ reset signal, the system controller disables and then re-enables the relevant regulator channels again. As soon as the last regulator is disabled the PORZ signal is reset. Power on Reset The power-on-reset duration, t POR , is deter- mined by selecting an appropriate capacitor connected to the CPOR pin. The value of t POR can be determined by the following formula: tPOR = 2.131 ×105 × CPOR . (1) The PORZ output goes high when both VBB is above the under- voltage warning levels, and the FB pins of the regulators that are enabled are > 85% of the V REG voltage. Because the external capacitor is charged via a 5 μA current source, care must be taken in the layout to avoid additional leak- age paths. The capacitor should be positioned adjacent to the CPOR pin, and the ground connection to the A4490 GND pin should be as short as possible. It is recommended that the t POR period be set to exceed the start-up phases of all three regulators, to avoid the possibility of multiple triggerings of the PORZ output. Output Voltage Selection The output voltage on each of the three regulators is set by the following relationship, shown here for the VREG1 channel: R1 R2=, ⎟⎟ VFB VREG1 – 1 (2) where R2 (connected between GND and the FB1 pin) should be a value between 4.7 and 12 kΩ. R1 is connected between the output rail and the FB1 pin. VREG1 is the set output regulator voltage. VFB is the reference voltage. The tolerances of the feedback resistors influence the voltage set- point. It is therefore important to consider the tolerance selection when targeting an overall regulation figure.

10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. introduce a small voltage offset to the output. cause a soft start cycle, unless a thermal shutdown event occurs. to increase in a linear fashion. will auto-restart under control of the soft start. possible to operate with a load current greater than 2.0 A. limit of 3.75 A with a duty cycle of 0.3. Thermal Considerations section. Inductor The inductance value, L, determines the ripple current. perhaps some margin to allow for overloads, and so forth. Figure 3. Current limit versus duty cycle

Triple Output Step-Down Switching RegulatorA4490 11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. The maximum peak-to-peak ripple current, IRIPPLE , occurs at the maximum input voltage. Therefore the duty cycle, D, should be found under these conditions (for the VREG1 channel): D(min) = .VREG1+Vf VBB(max)+Vf (3) where Vf is the forward voltage drop of the recirculation diode. The required inductance can be found: L (min) D(min)= , IRIPPLE VBB(max) – VREG1 fSW(min) (4) Note that the manufacturers inductance tolerance should also be taken into account. This value may be as high as ±20%. The peak-to-peak current should not exceed 1 A, to avoid instability in the innermost circuit loops due to insufficient slope compensa- tion. The maximum peak current can be found from to ensure that the saturation current level of the chosen inductor is not exceeded: Isat ILOAD += .IRIPPLE (5) Recommended inductor manufacturers and ranges are:

• Taiyo Yuden: NR6045 series for 1.5 A outputs
• Taiyo Yuden: NRG4026 series for 1.0 A outputs
• Sumida: CDH74 series for 1.5 A outputs Output Capacitor In the interests of size, cost and perfor- mance, it is highly recommended that ceramic X5R or X7R capacitor types be used. When using ceramic capacitors another important consideration is the E-field effects on the actual value of the capacitor. To minimize the effects of the capacitance reducing with output voltage, it is recommended that the working voltage of the capacitor be considerably more than the set output voltage. As a suggestion, it is recommended that 6.3 V-rated capacitors should be used for output voltages of 3.3 V and below. For output voltages of 5 V , a 10 V-rated capacitor should be used. The output capacitor determines the output voltage ripple and is used to close the control loop. To guarantee stability, the capaci- tance has to increase as the output voltage is reduced. This is actually reasonable from a ripple voltage point of view, as the ripple voltage is typically specified as a percentage of output voltage. The following table outlines what the minimum output capaci- tance should be for a given output voltage: Output Voltage (V) Minimum Output Capacitance (μF) 15 3.3 12 4.7 51 0 3.3 20 1.8 to 2.5 30 <1.8 40 Capacitance values with greater than the above values can be used with the effect of reducing the bandwidth. This may be nec- essary in systems that have extremely low ripple/noise require- ments. The output ripple is largely determined by the output capacitance and the effects of ESR and ESL can largely be ignored assuming good layout practice is observed. The output voltage ripple can be approximated to: VRIPPLE ≈ ,IRIPPLE 8 × fSW × COUT (6) When using ceramic capacitors, there is generally no need to con- sider the current carrying capability due to the negligible heating effects of the ESR. Also, the rms current flowing into the output capacitor is extremely low. Input Capacitor Again it is highly recommended that ceramic, X5R or X7R capacitors be used. The value of the input capacitance determines the amount of current ripple (EMI) that appears at the source (V BB supply) terminals. The amounts of current flowing in and out of the input capacitor depend on the relative impedances between the input capacitor impedance and the source impedance. To achieve a low impedance filter solution it is recommended to place at least two capacitors in parallel.

Triple Output Step-Down Switching RegulatorA4490 12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Again, there is generally no need to consider the heating effects of the rms current flowing through the ESR. Also, the phase- shifting of the input current drawn by each of the regulators helps to reduce the overall rms current. Flyback Diode This diode conducts during the switch off-time. A Schottky diode is recommended to minimize both the forward drop and switching losses. The worst case dissipation occurs at maximum V BB , when the duty cycle, D, is a minimum. The average current through the diode can be found: IDIODE(av) = ILOAD × (1 – D(min)) . (7) The forward voltage drop, Vf , can be found from the diode characteristics by using the actual load current (not the average current). The static power dissipation can be found: P STAT = ILOAD(av) × Vf . (8) It is also important to take into account the thermal rating of the package, RθJA , and the ambient temperature, to ensure that enough heatsinking is provided to maintain the diode junction temperature within the safe operating area for the device. To minimize the heating effects from the A4490 on the diode and vice-versa, it is recommended that the diode be mounted on the reverse side of the printed circuit board. Support Components POR capacitor (C11), charge pump capacitor (C1), reservoir capacitor (C2) and VDD filter capacitor (C12) should be ceramic X5R or X7R. Thermal Considerations To ensure the A4490 operates in the safe operating area, which effectively means restricting the junction temperature to less than 150°C, several checks should be made. The general approach is to work out what thermal impedance (R JA) is required to maintain the junction temperature at a given level, for a particular power dissipation. Another factor worth considering is that other power dissipating components on the system PCB may influence the thermal per- formance of the A4490. For example, the power loss contribution from the recirculation diode and the sense resistor may cause the junction temperature of the A4490 to be higher than expected. The following steps can be used as a guideline for determining a suitable thermal solution. It should be noted that this process is usually an iterative one to achieve the optimum solution. These factors can be considered as follows: Step 1. Estimate the maximum ambient temperature, T A(max) , of the application. Step 2. Define the maximum junction temperature, TJ(max). Note that the absolute maximum is 150°C. Step 3. Determine the worst case power dissipation, PD(max). The evaluation should consider these at maximum load and mini- mum VBB. Contributors are switch static and dynamic losses, and control losses. These are described in the following sections Switch Static Losses The following steps can be used to determine switch static losses: Estimate the maximum duty cycle: D(max) = ,VREG + Vf VBB (min) + Vf (9) where Vf is the forward voltage drop of the Schottky diode under the given load current. Estimate the RDS(on) of the each regulator switch at the given junction temperature: RDS(on)TJ RDS(on)25C 1+= .⎟⎟ 200 TJ – 25 (10) Note that if the VBB range is restricted to between 4.5 and 5.5 V , the RDS(on) increases. For example, the RDS(on) at 25°C with a VBB greater than 6 V is 450 mΩ typical, as stated in the Electri- cal Characteristics table. Under the same temperature conditions, with the VBB = 4.5 V , the RDS(on) is 560 mΩ typical. For VBB voltages between 4.5 and 6 V , the RDS(on) can be found by linear approximation. For more information on operating the A4490 between a VBB voltage of 4.5 and 5.5 V , see the Power Configu- rations section. The static loss for each switch can be determined: PSTAT = ILOAD2 × D(max) × RDS(on)TJ , (11) where ILOAD is the load for that particular regulator channel.

Triple Output Step-Down Switching RegulatorA4490 13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Switch Dynamic Losses The following can be used to deter- mine switch dynamic losses: Both turn on and turn off losses can be estimated: PDYN VBB (min) fSW 30 10–9 = ,ILOAD (12) where fSW is the switching frequency. Control Losses The following steps can be used to determine control losses: PVBB = IBBON × VBB , (13) where IBBON is the quiescent current assuming all three regulators are on. PVDD = IVDD × VDD , (14) where IVDD and is the quiescent current on VDD. Total Losses The total losses can now be estimated: PTOTAL = PSTAT1 + PSTAT2 + PSTAT2 +PDYN1 +PDYN2 + PDYN3 +PVBB + PVDD . (15) Thermal Impedance The thermal impedance required for the solution can now be determined: RQJA = .TJ – TA PTOTAL (16) Example Selected parameters: VBB(min) = 6 V VREG1 = 5 V at 1 A VREG2 = 3.3 V at 1 A VREG3 = 1.8 V at 800 mA TA= 70°C TJ = 115°C Vf = 0.4 V (a) Switch static losses VREG1 duty cycle, D1 0.84== 5+0.4 6+0.4 VREG2 duty cycle, D2 0.58==3.3+0.4 6+0.4 VREG3 duty cycle, D3 0.34==1.8+0.4 6+0.4 The RDS(on) of each switch can be found: 200 115 – 25 The static loss of each switch can be found: P STAT1 = 12 × 0.84 × 0.653 = 0.55 W PSTAT2 = 12 × 0.58 × 0.653 = 0.379 W PSTAT3 = 0.82 × 0.34 × 0.653 = 0.14 W (b) Switch dynamic losses PDYN1 0.045 W== 1 2 30 10–9 6 500 103 PDYN2 0.045 W== 1 2 30 10–9 6 500 103 PDYN3 0.036 W== 0.8 2 30 10–9 6 500 103 (c) Control losses P VBB = 0.005 × 6 = 0.03 W P VDD = 0.001 × 3.3 = 0.003 W (d) The total power dissipation can now be found: P TOTAL = 0.55 + 0.379 + 0.14 + 0.045 (e) The thermal impedance required for the solution can be found: RQJA 36.6 °C/W==115 – 70 1.228 For this particular solution a high thermal efficiency board is required to ensure the junction temperature is kept below 115°C. For maximum effectiveness, the PCB pad area underneath the thermal pad of the A4490 should be exposed copper. Several thermal vias (say between 4 and 8) should be used to connect the thermal pad to the internal ground plane. If possible, an additional thermal copper plane should be applied to the bottom side of the PCB and connected to the thermal pad of the A4490 through the vias.

14Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. by the thermal requirements described in the previous section. mize interference effects of ground noise from the power circuitry. Figure 4 illustrates the recommended grounding architecture. impedance connection to the star connection of the power stages. around high impedance nodes such as: FBx, ENBx and CPOR.

• The capacitor C IN should be placed as close as possible to the VBB terminals. The capacitance should be split between the VBB terminals for VREG1 and VREG3 and the VBB terminal for VREG2. Q L RLOAD VBB VREG D COUTCIN LX Star Connection

Figure 5. FET on-cycle current conduction paths Figure 6. FET off-cycle current conduction paths Figure 4. Ground plane configurations

Triple Output Step-Down Switching RegulatorA4490 15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. The VBB terminals for VREG1 and VREG2 should be connected via short and wide traces to the VBB terminal for VREG3.

• Each inductor should be connected as close as possible to the respective switching FET (LX1, LX2, and LX3) and output capacitors. Figure 6 shows the current conduction path during the off-cycle of the switching FET. The following points should be noted:
• The diode D should be placed as close as possible to both the switching FET and the inductor.
• Support components: POR capacitor (C11), charge pump ca- pacitor (C1), reservoir capacitor (C2), and VDD filter capacitor (C12) should be located as close as possible to their respective terminal connections. The ground referenced capacitors should be connected as close to the GND terminal as possible. Powering Configurations The following three diagrams show typical configurations for providing power to the application. The middle diagram corresponds to the typical application shown on the front page. VBB VDD Only VBB supplied 6 to 34 V LX L VREG D C Comments: - Simple configuration, only one supply required - Increased power losses at higher VBB voltages - VBB start-up = 4.3 V (typical), shutdown = 4.1 V (typical) VBB VDD VDD applied externally (first option) 6 to 34 V LX L VREG D C Comments: - Reduced power losses at higher VBB voltages - VBB start-up = 4.3 V (typical), shutdown = 3.5 V (typical). In this case, the start-up threshold (VBBUV(su) ) is higher because VREG is not present VBB VDD VDD applied externally (second option) 4.5 to 5.5 V LX L VREG D C Comments: - Power restricted as VBB < 6 V, due to increase in RDS(on) of buck switches - VBB start-up = 4.2 V (typical), shutdown = 3.5 V (typical)

Triple Output Step-Down Switching RegulatorA4490 16Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Package ES, 20-Pin QFN 0.95 CSEATING PLANEC0.08 21X A Terminal #1 mark area Coplanarity includes exposed thermal pad and terminals B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) For Reference Only (reference JEDEC MO-220WGGD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C D D C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 4.10 0.30 0.50 4.10 0.50 0.75 ±0.05 2.60 2.60 0.25 +0.05 –0.07 0.40 +0.15 –0.10 4.00 ±0.15 4.00 ±0.15 2.60 2.60 B PCB Layout Reference View For the latest version of this document, visit our website: www.allegromicro.com Copyright ©2008-2010, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.