A4481 ALLEGRO

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

A4481-DS, Rev. 1 FEATURES AND BENEFITS

  • Automotive AEC-Q100 qualified
  • 5.25 to 40 VIN operating range, 50 V load dump rating
  • 5 V ±1% internal LDO regulator
  • Foldback short-circuit protection
  • Short-to-battery protection (to 32 V , independent of VIN) for harness faults
  • Power OK (POK) flag
  • High-voltage logic level enable input (ENB) for microprocessor control or connection directly to battery
  • Pin-to-pin and pin-to-ground tolerant at every pin

5 VOUT , 50 mA Automotive Linear Regulator

Load Dump and Short-to-Battery Protection Typical Application Circuit Package: 8-pin SOIC with exposed thermal pad (suffix LJ)

DESCRIPTION

The A4481 is a single low-dropout linear regulator with complete control, diagnostics, and protection features that address many requirements of automotive applications. It regulates input voltages from 5.25 to 40 V , down to 5 V ±1% output voltage and is able to supply up to 50 mA of load current. Diagnostic output from the A4481 includes Power OK (POK) output to alert the microprocessor that a fault has occurred. Protection features include input undervoltage lockout (UVLO), foldback overcurrent protection, output undervoltage and overvoltage protections (UV/OVP), and thermal shutdown (TSD). In addition, the output is protected from a short-to- battery event up to 32 V . The A4481 device is available in an 8-pin SOIC package with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte-tin leadframe plating.

APPLICATIONS

Power supplies for: Microcontrollers

  • Transceivers (CAN, LIN, etc.)
  • Sensors A4481 VIN ENB VOUT GND POK VOUT = 5 V, IOUT = 50 mA VCC VIN Enable

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. ABSOLUTE MAXIMUM RATINGS* Characteristic Symbol Notes Rating Unit VIN, ENB Pins VIN, VENB –0.3 to 50 V VOUT Pin VOUT Independent of VIN –0.3 to 32 V All other pins –0.3 to 7 V Junction Temperature Range TJ(max) –40 to 165 °C Storage Temperature Range Tstg –40 to 150 °C *Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Char- acteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability SELECTION GUIDE Part Number Temperature Range (°C) Package Packing* A4481KLJTR-T –40 to 150 8-pin eSOIC with exposed thermal pad 3000 pieces per 7-in. reel *Contact Allegro for additional packing options. THERMAL CHARACTERISTICS:* May require derating at maximum conditions; see application section for optimization Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance (Junction to Ambient) RθJA eSOIC-8 (LJ) package 35 °C/W *Additional thermal information available on the Allegro website.

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Functional Block Diagram 5 V LDO VOUT UV/OV OCP TSD Short to VBAT Protection LDO VCC Foldback VIN ENB GND POK VOUT Pinout Diagram PAD VIN VIN NC ENB VOUT GND GND POK Terminal List Table Number Name Function

1 VIN Input voltage pin

2 VIN Input voltage pin

3 NC No connect

4 ENB Logic enable input from a microcontroller or

5 POK Open-drain regulator fault detection output

6 GND Ground

7 GND Ground

8 VOUT 5

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Characteristics Symbol Test Conditions Min. Typ. Max. Units INPUT VOLTAGE Operating Input Voltage VIN ENB high 5.25 5.35 40 V VIN UVLO Start Voltage VIN(START) VIN rising, ENB high 4.75 – 5.2 V VIN UVLO Stop Voltage VIN(STOP) VIN falling, ENB high 4.55 – 5 V VIN UVLO Hysteresis VIN(HYS) VIN(START) – VIN(STOP) – 0.2 – V INPUT CURRENT Input Quiescent Current 1 IQ VIN = 5.25 V, ENB high – 3.4 – mA Input Sleep Supply Current 1 IQ(SLEEP) VIN = 5.25 V, ENB low – 1 10 µA

5 V LINEAR REGULA

IOUT = 25 mA, VIN = 5.25 V 4.95 5 5.05 V Load Regulation 5 mA < IOUT < 50 mA, VIN = 5.25 V –1 – +1 % Output Capacitance Range 2 COUT 3 4.7 10 µF Startup Time 2 tSTART COUT ≤ 4.7 µF, Load = 100 Ω ±5% (50 mA) 0.7 1.5 2.3 ms LOGIN ENABLE (ENB) INPUT ENB Threshold VENB(H) VENB rising – – 2 V VENB(L) VENB falling 0.8 – – V ENB Resistance RENB – 100 – kΩ ENB Filter/Deglitch Time td(EN,FILT) 10 15 25 µs OVERCURRENT PROTECTION (OCP) Current Limit 1 ILIM VOUT = 5 V −55 −80 −140 mA Foldback Current 1 IFBK VOUT = 0 V −13 −23 −35 mA THERMAL PROTECTION (TSD) Thermal Shutdown Threshold 2 TTSD TJ rising 165 − − °C Thermal Shutdown Hysteresis 2 THYS − 15 − °C VOUT OV/UV PROTECTIONS VOUT OV Thresholds VOV(H) VOUT rising 5.15 5.33 5.5 V VOV(L) VOUT falling – 5.3 – V VOUT OV Hysteresis VOV(HYS) VOV(H) – VOV(L) 15 30 50 mV VOUT UV Thresholds VUV(H) VOUT rising – 4.71 – V VUV(L) VOUT falling 4.5 4.68 4.85 V VOUT UV Hysteresis VUV(HYS) VUV(H) – VUV(L) 15 30 50 mV VOUT Output Disconnect Threshold V DISC VOUT rising – 7.2 – V POK OUTPUTS POK Output Low Voltage VPOK(L) ENB high, VIN ≥ 5.25 V, IPOK = 4 mA – 150 400 mV POK Leakage Current 1 IPOK(LKG) VPOK = 3.3 V – – 2 µA OV and UV Filter/Deglitch T imes 2 td(FILT) Applies to undervoltage of the VOUT voltages 10 15 20 µs 1 For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 2 Ensured by design and characterization, not production tested. ELECTRICAL CHARACTERISTICS1: Valid at 5.25 V ≤ VINx ≤ 40 V, −40°C ≤ TA = TJ ≤ 150°C, unless otherwise specified

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. TYPICAL PERFORMANCE CHARACTERISTICS 4.95 4.96 4.97 4.98 4.99 5.01 5.02 5.03 5.04 5.05 -50 -25 0 25 50 75 100 125 150 Output Voltage (V) Temperature (°C) Output Voltage vs. Temperature 100 120 140 160 0 10 20 30 40 50 Input/Output Differential (mV) Output Current (mA) Dropout Voltage vs. Output Current 102 103 104 105 106 107 PSRR (dB) Frequency (Hz) Ripple Rejection Load Transient Response (VIN = 12 V, IOUT = 5 mA to 50 mA, COUT = 4.7 µF) Load Dump Characteristics (VIN = 12 to 50 V, IOUT = 50 mA, COUT = 4.7 µF) Foldback Current Limit Output Current (mA) Output Voltage (V) 0 10 20 30 40 50 60 70 80 90 6.00 5.00 4.00 3.00 2.00 1.00

0.00 IOUT

(20 mA/div) VOUT (20 mV/div) Time (µs) 0 100 200 300 400 500 600 700 800 900 1000 0 A 5 V Time (ms) VIN (20 V/div) VOUT (20 mV/div) 0 100 200 300 400 500 600 700 800 900 1000 0 V 5 V

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. FUNCTIONAL DESCRIPTION Enable (ENB) Input The A4481 has an enable (ENB) logic level input pin. To get the A4481 to operate, the ENB pin must be a logic high (>2 V). The ENB pin is rated to 50 V , allowing the ENB pin to be connected directly to VIN if there is no suitable logic signal available to wake up the A4481. When ENB transitions low, the A4481 waits approximately 15 µs before shutting down. This delay provides plenty of filtering to prevent the A4481 from prematurely shut- ting down because of any small glitch coupling onto the PCB trace or ENB pin. VIN ENB VOUT POK VENB(H) VUV(H) VUV(L) td(EN,FILT) VIN(STOP) VIN(START) VENB(L) VOV(L)VOV(H) VDISC td(FILT) td(FILT) td(FILT) td(FILT) td(FILT) td(FILT) POK undefined in this region POK undefined in this region POK undefined in this region VOUT UV/ Overload at Output Enable glitch UVLO Stop UVLO Start VOUT OV Figure 1: Timing Diagram (not to scale) Power OK (POK) Output The Power OK (POK) output is an open-drain output, so an external pull-up resistor must be connected. An internal compara- tor monitors the voltage at the VOUT pin and controls the open- drain device at the POK pin. POK is high when the voltage at the VOUT pin is within 10% of the final regulation voltage. The POK output is pulled low if: (1) the ENB pin transitions low, (2) UVLO occurs, (3) TSD occurs, or (4) UV/OVP occurs. The following timing diagram shows the basic operation and fault handling of the A4481:

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A.

APPLICATION INFORMATION

Output Capacitor (COUT): The A4481 is designed to be stable with all types of output capacitors, but it must meet the minimum and maximum capacitance requirement of 3 μF and 10 μF at the intended operating temperature and working voltage. For a ceramic capacitor , X5R or X7R dielectrics with 10 V or higher voltage rating are recommended. However , if the part needs to survive short-to-battery events (e.g. to supply off-board sensors), then 50 to 100 V voltage-rated capacitors are recommended. Input Capacitor (CIN): A 2.2 μF or larger capacitor is recom- mended for an input bypass capacitor. Similarly , choose a capaci- tor that offers plenty of safety margins for known input voltage applications. Thermal Considerations The A4481 remains fully operational to 40 V . However , owing to power dissipation characteristics of the package, full output cur- rent cannot be ensured for all combinations of ambient tempera- ture and input voltage. The maximum allowable power dissipa- tion in the IC is as follows: PMAX = (TJ(MAX ) − TA ) RθJA where TJ(MAX) = maximum junction temperature, TA = ambient air temperature, and RθJA thermal = resistance from junction to ambient. (35°C/W for the 8-pin eSOIC). The power dissipated by the IC can be calculated according to the following equation: PDISS = (VIN – VOUT) × IOUT + VIN × IQ where VIN = input voltage, VOUT = output voltage, IOUT = output current, and IQ = input quiescent current (3.4 mA typical). Figure 2 shows current de-rating plot at selected input voltages based on the above calculations. 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 Output Current – mA Ambient Temperature – °C VIN = 5.35 V VIN = 10 V VIN = 14 V VIN = 20 V VIN = 32 V VIN = 40 V Figure 2: Output Current De-Rating vs. Input Voltage

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Place the input and output capacitors as close as possible and on the same side of the PCB and IC. Place thermal vias directly under the device in a tight pattern, as shown in Figure 4, to improve dissipation. PCB LAYOUT GUIDELINES Figure 3: A4481 Layout Example Figure 4: Suggested PCB layout for thermal optimization (maximum available bottom-layer copper recommended) Ø0.3 mm via Top-layer exposed copper Signal traces LJ package exposed thermal pad LJ package footprint 0.7 mm 0.7 mm VIN VIN NC ENB VOUT GND GND POK PAD GroundInput Capacitor Output Capacitor PowerOK Output µP Enable V IN VOUT Tie directly to VIN to automatically enable the A4481

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. 3.30 Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) PCB Layout Reference View C 1.27 5.60 2.41 1.75 0.65

2.41 NOM

3.30 NOM

C SEATING PLANE

1.27 BSC

A Terminal #1 mark area B C B 2 1 C SEATING PLANE C0.10

0.25 BSC

1.04 REF

1.70 MAX

For Reference Only; not for tooling use (reference MS-012BA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 4.90 ±0.10 0.51 0.31 0.15 0.00 0.25 0.17 1.27 0.40 Exposed thermal pad (bottom surface); dimensions may vary with device A Branded Face Figure 5: Package LJ, 8-Pin eSOIC PACKAGE OUTLINE DRAWING

Load Dump and Short-to-Battery ProtectionA4481 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. For the latest version of this document, visit our website: www.allegromicro.com Copyright ©2016, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

Revision History

– October 9, 2015 Initial Release 1 August 31, 2016 Updated Foldback Current values (page 4) and Power OK (POK) Output section (page 6).