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+42 V 220 μF 25 V ESR VOUT COUT 3.3 V 2 A 2.87 k7 910 7 0.22 μF 0.01 μF CBOOT CIN2 CIN1 0.22 μF CBYP RTSET 54 k7 A4447 Efficiency vs. Output Current 0 500 1000 1500 2000 IOUT (mA) Efficiency % VOUT (V) 3.3 1.8 1.5 Data is for reference only. Efficiency data from circuit shown in left panel. Approximate Scale 1:1 A4447 A4447-DS, Rev. 1 Features and Benefits ▪ Wide input voltage range: 8 to 50 V ▪ Integrated low R DS(on) DMOS switch ▪ 2 A continuous output current ▪ Adjustable fixed off-time ▪ Highly efficient ▪ Adjustable output: 0.8 to 24 V ▪ Small package with exposed thermal pad High Voltage Step Down Regulator Typical Application Package: 8 pin SOIC with exposed thermal pad (suffix LJ)

Description

The A4447 is a 2 A, high efficiency general-purpose buck regulator designed for a wide variety of applications. The output voltage is adjustable from 0.8 to 24 V , based on a resistor divider and the 0.8 V ± 2 % reference. External components include an external clamping diode, inductor, and filter capacitor. The off-time is determined by an external resistor to ground. It operates in both continuous and discontinuous modes to maintain light load regulation. An internal blanking circuit is used to filter out transients due to the reverse recovery of the external clamp diode. Typical blanking time is 200 ns. This new device is ideal for various end products including applications with 8 to 50 V input voltage range and require up to 2 A output current, such as uninterruptible power supplies, point of sale (POS) applications, and industrial applications with 24 or 36 V bus. Applications include: ▪ Printer power supplies ▪ Office automation equipment ▪ POS thermal, laser, photo, and inkjet printers ▪ Tape drives ▪ Industrial applications

High Voltage Step Down RegulatorA4447 2Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. Absolute Maximum Ratings Characteristic Symbol Conditions Min. Typ. Max. Units VIN Supply Voltage V IN – – 50 V VBIAS Input Voltage V BIAS –0.3 – 7 V SW Switching Voltage VS –1 – – V ENB Input Voltage Range V ENB –0.3 – 7 V Operating Ambient Temperature Range T A –20 – 85 °C Junction Temperature T J(max) – – 150 °C Storage Temperature T stg –55 – 150 °C *Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current ratings, or a junction temperature, TJ, of 150°C. Package Thermal Characteristics* Package RθJA (°C/W) PCB LJ 35 4-layer * Additional information is available on the Allegro website.

Ordering Information

Use the following complete part numbers when ordering: Part Number Packing Description A4447SLJTR-T 13-in. reel, 3000 pieces/reel LJ package, SOIC surface mount with exposed thermal pad; leadframe plating 100% matte tin.

High Voltage Step Down RegulatorA4447 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Functional Block Diagram + – Switch PWM Control μC Soft Start Ramp Generation COMP 0.8 V Boot Charge VBIAS is connected to VOUT when V OUT target is between 3.3 and 5 V VIN COUT CBYP VOUT ESR VBB UVLO TSD Switch Disable Bias Supply I_Peak I_Demand Clamp Error BOOT ENB TSET GND VIN LX FB VBIAS

High Voltage Step Down RegulatorA4447 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Characteristics Symbol Test Conditions Min. Typ. Max. Units VIN Quiescent Current3 IVIN(Q) VENB = LOW, IOUT = 0 mA, VIN = 42 V, VBIAS = VOUT – 0.90 1.35 mA VENB = LOW, IOUT = 0 mA, VIN = 42 V, VBIAS < 3 V – 4.4 6.35 mA VENB = HIGH – – 100 μA VBIAS Input Current I BIAS VBIAS = VOUT – 3.5 5 mA Buck Switch On Resistance R DS(on) TA = 25°C, IOUT = 2 A – 450 – m Ω TA = 125°C, IOUT = 2 A – 650 – m Ω Fixed Off-Time Proportion t off Based on calculated value –15 – 15 % Feedback Voltage V FB 0.784 0.8 0.816 V Output Voltage Regulation V OUT IOUT = 0 mA to 2 A –3 – 3 % Feedback Input Bias Current I FB –400 –100 100 nA Soft Start Time t ss 51 0 1 5 m s Buck Switch Current Limit I CL VFB > 0.4 V 2.2 – 3 A VFB < 0.4 V 0.5 – 1.2 A ENB Open Circuit Voltage V OC Output disabled 2.0 – 7 V ENB Input Voltage Threshold V ENB(0) LOW level input (Logic 0), output enabled – – 1.0 V ENB Input Current I ENB(0) VENB = 0 V –10 – –1 μA VIN Undervoltage Threshold V UVLO VIN rising 6.6 6.9 7.2 V VIN Undervoltage Hysteresis V UVLO(hys) VIN falling 0.7 – 1.1 V Thermal Shutdown Temperature T JTSD Temperature increasing – 165 – °C Thermal Shutdown Hysteresis T JTSD(hys) Recovery = TJTSD – TJTSD(hys) –1 5–° C 1Negative current is defined as coming out of (sourcing) the specified device pin. 2Specifications over the junction temperature range of 0ºC to 125ºC are assured by design and characterization. 3VBIAS is connected to VOUT when the VOUT target is between 3.3 and 5 V. ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VIN = 8 to 50 V (unless noted otherwise)

High Voltage Step Down RegulatorA4447 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Functional Description 100 120 140 160 180 200 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 6 Off-Time Setting versus Resistor Value RTSET (kΩ) tOFF (µs) VBIAS = 5 V VBIAS = 3.3 V The A4447 is a fixed off-time, current mode controlled, buck regulator. The regulator requires an external clamping diode, inductor, and filter capacitor. It operates in both continuous and discontinuous modes. An internal blanking circuit is used to filter out transients resulting from the reverse recovery of the external clamp diode. Typical blanking time is 200 ns. The value of a resistor between the TSET and GND determines the fixed off-time (see graph in the t OFF section). VOUT. The output voltage is adjustable from 0.8 to 24 V , set by an external resistor divider. The voltage can be calculated with the following formula: V OUT = VFB × (1 + R1/R2) (1) Light Load Regulation. To maintain voltage regulation during light load conditions, the switching regulator enters a cycle-skip- ping mode. As the output current decreases, there remains some energy that is stored during the power switch minimum on-time. In order to prevent the output voltage from rising, the regulator skips cycles once it reaches the minimum on-time, effectively making the off-time larger. Soft Start. An internal ramp generator and counter allow the out- put to slowly ramp up. This limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any DC load at startup. Internally, the ramp is set to 10 ms nominal rise time. During soft start, current limit is 2.2 A minimum. The following conditions are required to trigger a soft start:

  • V IN > 6 V
  • ENB pin input falling edge
  • Reset of a TSD (thermal shut down) event V BIAS. To improve overall system efficiency, the regulator output, VOUT, is connected to the VBIAS input to supply the operating bias current during normal operating conditions. During startup the circuitry is run off of the VIN supply. VBIAS should be con- nected to VOUT when the V OUT target level is between 3.3 and 5 V . If the output voltage is less than 3.3 V , then the A4447 can operate with an internal supply and pay a penalty in efficiency, as the bias current will come from the high voltage supply, VIN. VBIAS can also be supplied with an external voltage source. No power-up sequencing is required for normal operation. ON/OFF Control. The ENB pin is externally pulled to ground to enable the device and begin the soft start sequence. When the ENB is open circuited, the switcher is disabled and the output decays to 0 V . Protection. The buck switch will be disabled under one or more of the following fault conditions:
  • V IN < 6 V
  • ENB pin = open circuit
  • TSD fault When the device comes out of a TSD fault, it will go into a soft start to limit inrush current. t OFF. The value of a resistor between the TSET pin and ground determines the fixed off-time. The formula to calculate tOFF (μs) is: ,tOFF RTSET= ⎟ 10.2 × 109 1– 0.03 × VBIAS (2) where RTSET (kΩ) is the value of the resistor. Results are shown in the following graph: The RTSET resistor should be not smaller than 7.65 kΩ ±2% to prevent very short off-times from violating the minimum on-time of the switcher. Shorted Load. If the voltage on the FB pin falls below 0.4 V , the regulator will invoke a 0.85 A typical overcurrent limit to handle the shorted load condition at the regulator output. For low output voltages at power up and in the case of a shorted output, the off- time is extended to prevent loss of control of the current limit due to the minimum on-time of the switcher. The extension of the off-time is based on the value of the TSET multiplier and the FB voltage, as shown in the following table: VFB (V) TSET Multiplier < 0.16 8 × t OFF < 0.32 4 × t OFF < 0.5 2 × t OFF > 0.5 t OFF

High Voltage Step Down RegulatorA4447 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Component Selection L1. The inductor must be rated to handle the total load current. The value should be chosen to keep the ripple current to a reason- able value. The ripple current, I RIPPLE, can be calculated by: IRIPPLE = VL(OFF) × tOFF / L (3) V L(OFF) = VOUT + Vf + IL(A V) × RL (4) Example: Given VOUT = 5 V , Vf = 0.55 V , VIN = 42 V , ILOAD = 0.5 A, power inductor with L = 180 μH and RL = 0.5 Ω Rdc at 55°C, tOFF = 7 μs, and RDS(on) = 1 Ω. Substituting into equation 4: VL(OFF) = 5 V + 0.55 V+ 0.5 A × 0.5 Ω = 5.8 V Substituting into equation 3: IRIPPLE = 5.8 V × 7 μs / 180 μH = 225 mA The switching frequency, fSW, can then be estimated by: f SW = 1 / ( tON + tOFF ) (5) t ON = IRIPPLE × L / VL(ON) (6) V L(ON) = VIN – IL(A V) × RDS(on) – IL(A V) × RL– VOUT (7) Substituting into equation 7: VL(ON) = 42 V – 0.5 A × 1 Ω – 0.5 A × 0.5 Ω – 5 V = 36 V Substituting into equation 6: tON = 225 mA × 180 μH / 36 V = 1.12 μs Substituting into equation 7: fSW = 1 / (7 μs +1.12 μs) = 123 kHz Higher inductor values can be chosen to lower the ripple cur- rent. This may be an option if it is required to increase the total maximum current available above that drawn from the switching regulator. The maximum total current available, ILOAD(MAX) , is: ILOAD(MAX) = ICL(min) – IRIPPLE / 2 (8) where ICL(min) is 2.2 A, from the Electrical Characteristics table. D1. The Schottky catch diode should be rated to handle 1.2 times the maximum load current. The voltage rating should be higher than the maximum input voltage expected during all operating conditions. The duty cycle for high input voltages can be very close to 100%. COUT. The main consideration in selecting an output capacitor is voltage ripple on the output. For electrolytic output capacitors, a low-ESR type is recommended. The peak-to-peak output voltage ripple is simply I RIPPLE × ESR. Note that increasing the inductor value can decrease the ripple current. The minimum voltage rating of the capacitor is 10 V . However, because ESR decreases with voltage, the most cost-effective choice may be rated higher in voltage. It is recom- mended that the ESR be less than 100 mΩ.

High Voltage Step Down RegulatorA4447 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. RTSET Selection. Correct selection of RTSET values will ensure that minimum on time of the switcher is not violated and prevent the switcher from cycle skipping. For a given V IN to VOUT ratio, RTSET must be greater than or equal to the value defined by the curve in the RTEST Value Selection graph below. Note. The curve represents the minimum RTSET value. When calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor tolerance should also be considered, so that under all operating conditions the resistance on the TSET pin remains as close to the curve as possible. The RTEST Selection table shows recommended RTSET values based on common operating conditions. For other operating con- ditions, refer to the RTSET Value Selection graph. FB Resistor Selection. The impedance of the FB network should be kept low to improve noise immunity. Large value resis- tors can pick up noise generated by the inductor, which can affect voltage regulation of the switcher. RTSET Value Selection* Selection Graph Recommended Common Values 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 RTSET (kΩ) VIN / VOUT VIN (V) VOUT (V) VIN / VOUT RTSET Value (kΩ) 42 5 8.4 37.4 42 3.3 12.7 54.9 42 1.8 23.3 90.9 42 1.5 28 105 24 5 4.8 20.0 24 3.3 7.3 32.4 24 1.8 13.3 54.9 24 1.5 16 66.5 12 5 2.4 7.68 12 3.3 3.6 13.7 12 1.8 6.6 30.1 12 1.5 8 37.4 *The RTSET resistor should be not smaller than 7.65 kΩ ±2% to prevent very short off-times from violating the minimum on-time of the switcher. Recommended Components Component Description Part Number L1 Sumida 68 μH RCH1216BNP-680K D1 NIEC Schottky Barrier Diode 60 V TO-252AA NSQ03A06 CBYP Ceramic X7A 0.22 μF 100 V Generic CBOOT Ceramic X7A 0.01 μF 100 V Generic CIN Electrolytic 100 μF 50 V; must be able to handle worst case ripple curent Generic Ceramic X7A 0.22 μF 50 V Generic COUT United Chemi-Con PXA 220 μF 16 V Low ESR PXA16VC221MJ12TP Rubycon ZL 220 μF 25 V Low ESR (Option 1) 25ZL220M8x11.5 Panasonic FM 220 μF 25 V Low ESR (Option 2) EEUFM1E221 V OUT 1.5 V 1.8 V 3.3 V 5 V R1 1.30 k Ω 2.55 k Ω 2.87 k Ω 6.34 k Ω R2 1.47 k Ω 2.00 k Ω 0.910 k Ω 1.20 k Ω

High Voltage Step Down RegulatorA4447 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. RTSET COUT CIN1 CIN2 VIN VOUT CBOOT CBYP GND GND GND GND Recommended PCB Layout The large star ground area on the populated side of the PCB, shown in the diagram as the GND nodes, supports high current throughput, and allows the VOUT node to be located as close as practical to the A4447 (U1). Thermal conduction from the A4447 is enhanced by direct contact of its exposed thermal pad to the smaller ground area under the A4447. This area is connected by thermal vias to the large copper ground plane on the unpopulated side of the PCB. Star Ground Exposed copper thermal ground area on the unpopulated side of the PCB In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance ground located very close to the device. This grounding scheme is known as star grounding. It is likely that a ground plane will be necessary to meet thermal requirements. The recommended land pattern illus- trates how to create a low impedance ground that will also assist with removing thermal energy from the device. The input capacitor must be placed as close as possible to the VIN terminal because during the on cycle it is responsible for supplying the current to the switcher. During the off cycle, the current path is from the negative terminal of the COUT cap, through the diode and inductor, and then to the load. As a result, COUT and the rectifier diode must share the connection at the negative terminal of the CIN capacitor in order to reduce ground bounce when the diode is conducting. The inductor should be connected as close as possible to the switching node to minimize noise. Some applications may require a shielded inductor due to EMI restrictions. This will depend on the application and parameters defined by the system that will host the regulator. The high voltage-switching node could affect R TSET. If longer off-times are used, the resistance on the RTSET pin can be quite large. When designing the layout, try to keep RTSET away from the inductor and switching node. It is also beneficial to keep the trace as short as possible to reduce the effect of noise injection. Because of this layout guideline, the TSET pin is located on the other side of the device, away from the switching node. The FB resistor network should have a lower impedance to avoid interference from the switching node. Because the impedance on the FB node can be controlled, it is not as critical to keep the network isolated. It is important to keep the ground trace short so that ground bounce cannot effect the output voltage regulation. VOUT VIN L1 COUT CIN1CIN2 CBYP RTSET CBOOT A4447 ENB LX VBIAS VIN GND FB TSET BOOT PAD

High Voltage Step Down RegulatorA4447 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Package LJ, 8 Pin SOIC Pin Out Diagram BOOT ENB TSET GND VIN LX VBIAS FB Pad Terminal List Table Number Name Description

1 BOOT Gate drive boost node

2 ENB On/off control; logic input

3 TSET Off-time setting

4 GND Ground

5 FB Feedback for adjustable regulator

6 VBIAS Bias supply input

7 LX Buck switching node

8 VIN Supply input

Copyright ©2008-2009, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 3.30 Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) PCB Layout Reference View C 1.27 5.602.41 1.75 0.65

2.41 NOM

3.30 NOM

C SEATING PLANE

1.27 BSC

A Terminal #1 mark area B C B C SEATING PLANEC0.10

0.25 BSC

1.04 REF

1.70 MAX

For Reference Only; not for tooling use (reference MS-012BA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 4.90 ±0.10 0.51 0.31 0.15 0.00 0.25 0.17 1.27 0.40 Exposed thermal pad (bottom surface); dimensions may vary with device A Branded Face