A4402ELPTR-T

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Description

The A4402 is a power management IC that combines a 2% constant on-time buck regulator and a 2% linear regulator. Ideal for applications that require two regulated voltages. The buck regulator output supplies the adjustable linear regulator to reduce power dissipation and increase overall efficiency. The switching regulator is capable of operating above 2 MHz. A greater than 2 MHz switching frequency enables the customer to select low value inductors and capacitors while avoiding EMI. Protection features include undervoltage lockout and thermal shutdown. In case of a shorted load, each regulator features overcurrent protection. The A4402 also features a power-on reset with adjustable delay for the microprocessor output. The A4402 is provided in a 16-pin, ≤1.20 mm nominal overall height TSSOP, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. 4402-DS, Rev. 2 Features and Benefits ▪ 2 MHz switching frequency ▪ Adjustable soft start timer ▪ Watchdog input ▪ Power-on reset output ▪ Adjustable 2% buck regulator ▪ Adjustable 2% linear regulator ▪ Enable input ▪ 6 to 50 V supply voltage range ▪ Overcurrent protection ▪ Undervoltage lockout (UVLO) ▪ Thermal shutdown protection Constant On-Time Buck Converter with Integrated Linear Regulator Package: 16-pin TSSOP with exposed thermal pad (suffix LP) Typical Application Not to scale A4402 ENB VO2 NPOR GND GND GND 1 μF 3.3 V 300 mA VO2 33 μH VIN1 LX FB1 10 μF VBAT FB2 VIN2 POR CPOR TSET CTSET 0.1 μF ISEN VLIN VSW Switching Regulator Output Linear Regulator Output A4402 TON 0.01 μF 4RSENSE .7 μF Rton 750 kΩ kΩ kΩ WDI 0.33 μF 0.15 μF kΩ 31.6 kΩ 9.76 5.62 kΩ 4.7 kΩ BOOT ▪ Photo and inkjet printers ▪ Industrial controls ▪ Distributed power systems ▪ Network applications Applications:

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 2Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. Pin-out Diagram Absolute Maximum Ratings Characteristic Symbol Notes Rating Units VIN1 Pin V IN1 –0.3 to 50 V VIN2 Pin V IN2 –0.3 to 7 V LX Pin V LX –1 to 50 V ISEN Pin V ISEN –0.5 to 1 V ENB Pin V ENB –0.3 to 7 V VO2 Pin V O2 –0.3 to 7 V WDI Pin V WDI –0.3 to 6 V TON Pin V TON –0.3 to 7 V FB1 and FB2 Pins V FBx –0.3 to 7 V NPOR V NPOR –0.3 to 6.5 V Ambient Operating Temperature T A Range E –40 to 85 °C Junction Temperature T j(max) 150 °C Storage Temperature Range T stg –40 to 150 °C Selection Guide Part Number Packing Package A4402ELPTR-T 4000 pieces per 13-in. reel 16-pin TSSOP with exposed thermal pad Thermal Characteristics Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 34 ºC/W *Additional thermal information available on the Allegro website. Terminal List Table Number Name Function

1 TON On time setting terminal

2 GND Ground

3 FB2 Feedback for V

4 VIN2 Input voltage 2

5 VO2 Regulator 2 output

6 WDI Watchdog input

7 TSET Soft start and watchdog timing capacitor terminal

8 NPOR Fault output

9 FB1 Feedback for V

10 POR POR delay

11 ISEN Current sense, limit setting for switching regulator, connect to GND

12 BOOT Boot node for LX

13 LX Switching regulator output

14 GND Ground

15 VIN1 Input voltage 1

16 ENB Enable input

– PAD Exposed thermal pad TON GND FB2 VIN2 VO2 WDI TSET NPOR ENB VIN1 GND LX BOOT ISEN POR FB1 PAD

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Functional Block Diagram ENB VO2 NPOR VFB2 Internal Regulator VIN1 ENB 1 3.3 V 300 mA VO2 FAULT TSD 33 μH LX FB1 BOOT Switch PWM Control Switch Disable Boot Charge VBAT FB2 VIN2 POR CPOR Soft Start Ramp Generator Watchdog Timer TSET CTSET VREF VREF VREF VSW VLIN 0.1 ISEN VSW TON VREG VREG 0.01 4.7 VIN1 Rton 750 k Ω kΩ kΩ kΩ 4.7 k Ω kΩ kΩ WDI WDI 0.15 μF μF0.33 5.62 R RSENSE 31.6 9.76 GND GND μF μF μF μF μF

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Continued on the next page… ELECTRICAL CHARACTERISTICS1,2 valid at TJ = 25°C, VIN = 13.5 V (unless otherwise noted) Characteristics Symbol Test Conditions Min. Typ. Max. Units Input Voltage Supply 1 V IN1 6 13.5 50 V Input Voltage Supply 2 V IN2 VIN2 = V SW 3.3 – 5 V Supply Quiescent Current I IN(Q) ENB = 5 V, IOUT = ISW+ ILIN = 0 mA, VIN = 13.5 V – 10 – mA VIN1 = 13.5 V, ENB = 0 V, IOUT = ISW+ ILIN = 0 mA – – 1 μA ENB Logic Input Voltage V ENB VENB rising 2.0 2.28 2.56 V ENB Hysteresis V ENBHYS – 100 – mV ENB Logic Input Current I ENB High input level, VENB = 3 V – – 100 μA Low input level, VENB < 0.4 V –2 – 2 μA Linear Regulator Output Voltage Range V O2 1.8 – 3.3 V Feedback Voltage V FB2 1 mA < I O2 < 250 mA, 3.3 V < VIN2 < 5 V 1.156 1.180 1.204 V VO2 Undervoltage Lockout Threshold VO2UVLO V O2 rising based on FB voltage 0.896 0.944 0.990 V VO2 Undervoltage Lockout Hysteresis VO2UVHYS 30 50 70 mV Feedback Input Bias Current I FB2 –100 100 400 nA Current Limit I O2 250 – 350 mA Dropout Voltage V DROP I OUT = ISW+ ILIN = 250 mA – – 1.2 V Switching Regulator Output Voltage Range V SW 3.3 – 5 V Feedback Voltage V FB1 I OUT = ISW+ ILIN = 1 mA to 1.0 A, 8 V < VIN < 18 V 1.156 1.180 1.204 V Feedback Input Bias Current I FB1 –400 –100 100 nA Switcher On Time t on VIN = 19.25 V, Rton = 750 kΩ – 670 – ns VIN = 13.5 V, Rton = 750 kΩ 185 235 285 ns VIN = 8 V, Rton = 750 kΩ – 1.4 – μs ton Low Voltage Threshold V PL VIN rising 8.1 9 9.9 V ton High Voltage Threshold V PH VIN rising 15.75 17.5 19.25 V Changeover Hysteresis V HYS – 250 – mV On-time Accuracy err ton –30 – 30 % Minimum On-time t onmin 80 – – ns Minimum Off-time t offmin 130 – – ns Buck Switch On-Resistance R DS(on) TJ = 25°C, ILOAD = 1 A – 400 – m Ω TJ = 125°C, ILOAD = 1 A – 650 – m Ω ISEN Voltage V ISEN – –200 – mV Valley Current Limit Threshold I lim RSENSE = 0.27 Ω – 740 – mA

6 V < VIN < 8 V – – 550 mA

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Protection Circuitry NPOR Output Voltage V NPOR I NPOR = 1 mA – – 400 mV NPOR Leakage Current I NPOR V NPOR = 5 V – – 1 μA NPOR Reset V NPORRESET 20 kΩ pullup connected to VOUT2, VIN < – – 0.7 V Thermal Shutdown Threshold T JTSD T J rising – 170 – ºC Thermal Shutdown Hysteresis T JTSDHYS – 15 – ºC Timing Circuitry TSET Current, Watchdog Mode I TSETWDI NPOR = high 7 10 14 μA TSET Valley Voltage, Watchdog Mode VTRIP – 1.2 – V TSET Reset Voltage, Watchdog Mode VRESET – 0.48 – V WDI Frequency f WDI – – 100 kHz WDI Duty Cycle DC WDI 10 – 90 % WDI Logic Input V WDI(0) VIN2 × 0.55 – – V WDI Logic Input Current I WDI VWDI = 0 to 5 V –20 < 1.0 20 μA WDI Input Hysteresis V WDIHYS – 300 – mV TSET Current, Soft Start Mode I TSETSS NPOR = low 14 20 26 μA POR Current I POR 3.92 5.60 7.28 μA 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin. 2Performance in the range –40°C to 85°C guaranteed by design and characterization. ELECTRICAL CHARACTERISTICS1,2 (continued) valid at TJ = 25°C, VIN = 13.5 V (unless otherwise noted) Characteristics Symbol Test Conditions Min. Typ. Max. Units

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. VIN1 VIN1 ENB VSW VLIN NPOR UVLO Rising UVLO Rising tpor tss UVLO Falling UVLO Falling 6 V 18 V VSW VLIN NPOR tpor tss VPOR VCTSET UVLO Rising tpor UVLO Rising tpor tss Power-Up and Power-Down Timing Diagrams Using ENB Using VIN1

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Watchdog Timing Diagram ENB UVLO Rising Vreset Vtrip VSW NPOR tpor tss WDI VO2 VTSET twait tpor twait

Worcester, Massachusetts 01615-0036 U.S.A. put voltage tends to decrease and the switching period increases. Figure 1. Current limiting during overload

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. TSET The TSET pin serves a dual function by controlling the timing for both the soft start ramp and the WDI input. The current sourced from the TSET pin is dependant on the state of NPOR. There are two formulas for calculating the time constants. C TSET must be selected so that both the WDI frequency and soft start requirements are met. The formulas for calculating WDI and soft start timing are: tWDI 7.2 × 9.6 × 104 × CTSET , and= (2) tSS 6.0 × 6.0 × 104 × CTSET , = (3) where CTSET is the value of the capacitor and the results, tx, are in s. Watchdog The WDI input is used to monitor the state of a DSP or microcontroller. A constant current is driven into the capacitor on TSET, causing the voltage on the TSET pin to ramp upward until, at each rising edge on the WDI input, the ramp is pulled down to V RESET. If no edge is seen on the WDI pin before the ramp reaches VTRIP , the NPOR pin is pulled low. The watchdog timer is not activated until the WDI input sees one rising edge. The WDI pin should be pulled to ground with a 4.7 kΩ resistor. Soft Start During soft start, an internal ramp generator and the external capacitor on TSET are used to ramp the output voltage in a controlled fashion. This reduces the demand on the exter- nal power supply by limiting the current that charges the output capacitor and any DC load at startup. Either of the following conditions are required to trigger a soft start:

• ENB pin input rising edge
• Reset of a TSD event When a soft start event occurs, VO2 is held in the off state until the soft start ramp timer expires. Then the regulator will power up normally. Refer to timing diagrams for details. BOOT A bootstrap capacitor is used to provide adequate charge to the NMOS switch. The boot capacitor is referenced to LX and supplies the gate drive with a voltage larger than the supply voltage. The size of the capacitor must be 0.01 μF, X7R type, and rated for at least 25 V . TON A resistor from the TON input to VIN1 sets the on-time of the converter for a given input voltage. The formula to calculate the on-time is: ton 3.12–12 + 30 × 10–9 =. VIN1 Rton (4) When the supply voltage is between 9 and 17.5 V , the switcher period remains constant, at a level based on the selected value of R ton . At voltages lower than 9 V and higher than 17.5 V , the period is reduced by a factor of 3.5. If a constant period is desired over varying input voltages, it is important to select an on-time that under worst case conditions will not exceed the minimum off-time or minimum on-time of the converter. For reasonable input voltage ranges, the period of the converter can be held constant, resulting in a constant operating frequency over the input supply range. More information on how to choose R ton can be found in the Application Information section. ISEN The sense input is used to sense the current in the diode during the off-time cycle. The value for RSENSE is obtained by the formula: RSENSE = 0.2 / IV ALLEY , (5) where IV ALLEY is the lowest current measured through the induc- tor during the off-time cycle. It is recommended that the current sense resistor be sized so that, at peak output current, the voltage on ISEN does not exceed –0.5 V . Because the diode current is measured when the inductor current is at the valley, the average output current is greater than the I V ALLEY value. The value for IV ALLEY should be: IV ALLEY = IOUT(av) – 0.5 IRIPPLE + K , (6) where: IOUT(av) is the average of both output currents, IRIPPLE is the inductor ripple current, and K is a guardband margin. The peak current in the switch is then: IPEAK = IV ALLEY + IRIPPLE . (7)

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. The valley current must be calculated so that, at the worst-case ripple, the converter can still supply the required current to the load. Further information on how to calculate the ripple current is included in the Application Information section. ENB An active high input enables the device. When set low, the device enters sleep mode; all internal circuitry is disabled, and the part draws a maximum of 1 μA. Thermal Shutdown When the device junction temperature, T J , is sensed to be at TJTSD, a thermal shutdown circuit disables the regulator output, protecting the A4402 from damage. Power-on Reset Delay The POR function monitors the VFB2 voltage and provides a signal that can be used to reset a DSP or microcontroller. A POR event is triggered by either of the follow- ing conditions:

• VFB2 falls below its UVLO threshold. This occurs if the current limit on either regulator is exceeded, or if the switcher voltage falls due to TSD.
• After a rising edge on the WDI input, the voltage on TSET reaches V TRIP. An open drain output, through the NPOR pin, is provided to signal a POR event to the DSP or microcontroller. The reset occurs after an adjustable delay, t POR, set by an external capacitor connected to the POR pin. The value of tPOR is calculated using the following formula: tPOR = 2.4 × 102 × CPOR , (8) where CPOR is the value of the capacitor and tPOR is in s. Shutdown The buck regulator will shutdown if one of the fol- lowing conditions is present:
• TSD
• ENB falling edge

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Switcher On-Time and Switching Frequency In order for the switcher to maintain regulation, the energy that is transferred to the inductor during the on-time must be transferred to the capacitor during the off-time. Because of this relationship, the load current, IR drops, as well as input and output voltages, affect the on-time of the converter. The equation that governs switcher on-time is: ton = . VIN1+ RDS(on)× IPEAK + Vf TSW × (VSW+ RLOAD× IPEAK + Vf + RSENSE× IPEAK ) (9) The effects of the voltage drop on the inductor and trace resis- tance affect the switching frequency. However, the frequency variation due to these factors is small and is covered in the varia- tion of the switcher period, TSW , which is ±25% of the target. Removing these current dependant terms simplifies the equation: ton =× . VIN1+ Vf + (VSENSE× IPEAK ) VSW+ Vf + (VSENSE× IPEAK ) fSW (10) Be sure to use worst-case sense voltage and forward voltage of the diode, including any effects due to temperature. For example, given a 1 A converter with a supply voltage of 13.5 V , output voltage is 5 V , V f is 0.5 V , VSENSE is 0.15 V and the desired fre- quency is 2.0 MHz. We can solve for ton as follows: ton 199 ns== × . 13.5 + 0.5 + 0.15 5 + 0.5 + 0.15 2×106 The formulas above describe how ton changes based on input and load conditions. Because load changes are minimal, and the out- put voltage is fixed, the dominant factor that affects the on-time is the input voltage. The converter is able to maintain a constant period over a varying supply voltage because the on-time change is based on the input voltage. The current into the TON terminal is derived from a resistor tied to VIN1, which sets the on-time proportional to the supply voltage. Selecting the resistor value, based on the t on calculated above, is done using the following formula: RTON = . 3.12 × 10–12 VIN1× (ton+ 10 ns) (11) After the resistor is selected and a suitable ton is found, it must be demonstrated that ton does not, under worst-case conditions, exceed the minimum on-time or minimum off-time of the con- verter. The minimum on-time occurs at maximum input voltage and minimum load. The maximum off time is occurs at minimum supply voltage and maximum load. For supply voltages below 9.5 V and above 7 V , refer to the Low V oltage Operation section. Low Voltage Operation The converter can run at very low input voltages. With a 5 V output, the minimum input supply can be as low as 6 V . When operating at high frequencies, the on-time of the converter must be very short because the available period is short. At high input voltages the converter must maintain very short on-times, while at low input voltages the converter must maintain long off-times. Rather than limit the supply voltage range, the converter solves this problem by automatically increas- ing the period by a factor of 3.5. With the period extended, the converter will not violate the minimum on-time or off-time. If the input voltage is between 9.5 V and 17 V , the converter will main- tain a constant period. When calculating worst-case on-times and off-times, make sure to use the multiplier if the supply voltage is between those values. When operating at voltages below 8 V , additional care must be taken when selecting the inductor and diode. At low voltages the maximum current may be limited due to the IR drops in the current path. When selecting external components for low voltage operation, the IR drops must be considered when determining on-time, so the complete formula should be used to make sure the converter does not violate the timing specification. Inductor Selection Choosing the right inductor is critical to the correct operation of the switcher. The converter is capable of running at frequencies above 2 MHz. This makes it possible to use small inductor values, which reduces cost and board area. The inductor value is what determines the ripple current. It is important to size the inductor so that under worst-case conditions I V ALLEY equals IAV minus half the ripple current plus reasonable margin. If the ripple current is too large, the converter will be current limited. Typically peak-to-peak ripple current should be limited to 20% to 25% of the maximum average load current.

Application Information

12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Worst-case ripple current occurs at maximum supply voltage. capacitors be used in parallel to further reduce emissions. forward voltage of the diode. ered using I2R and the minimum duty cycle. ance paths to each other. Figure 2 illustrates the technique. Figure 2. Star Ground Connection

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. The ground from each of the components should be very close to each other and be connected on the same surface as the com- ponents. Internal ground planes should not be used for the star ground connection, as vias add impedance to the current path. In order to further reduce noise effects on the PCB, noise sensi- tive traces should not be connected to internal ground planes. The feedback network from the switcher output should have an independent ground trace that goes directly to the exposed pad underneath the device. The exposed pad should be connected to internal ground planes and to any exposed copper used for heat dissipation. If the grounds from the device are also connected directly to the exposed pad the ground reference from the feed- back network will be less susceptible to noise injection or ground bounce. To reduce radiated emissions from the high frequency switching nodes it is important to have an internal ground plane directly under the LX node. The plane should not be broken directly under the node as the lowest impedance path back to the star ground would be directly under the signal trace. If another trace does break the return path, the energy will have to find another path, which is through radiated emissions. PAD A4402 C1 C8 TON GND FB2 VIN2 VO2 WDI TSET NPOR ENB VIN1 GND LX BOOT ISEN POR FB1 VIN1 VSW VLIN R6R7 R1 PCB Layout Diagram GND VIN2 C1 C8 VSW VLIN VIN1 GND GND GND GND GND PCB Thermal Vias Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.) A4402 Solder Star Ground

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 14Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Pin Circuit Diagrams Power Terminals LX GND GND 54 V GND GND 7 V VIN1 GND 54 V VIN1 TON GND VIN2 FB1 FB2 WDI TSET NPOR POR ISEN ENB Logic Terminals VIN1 BOOT GND 10 V 10 V VIN2 VO2 GND

Constant On-Time Buck Converter with Integrated Linear RegulatorA4402 15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. CSEATING PLANEC0.10 16X 6.10 0.65 0.45 1.70 3.00 5.00 ±0.10 3.00 3.00 3.00

1.20 MAX

0.15 MAX

0.65 0.25 (1.00) 4° ±4 0.25 +0.05 –0.06 0.15 +0.05 –0.06 GAUGE PLANE SEATING PLANE B A A Terminal #1 mark area B All dimensions nominal, not for tooling use (reference JEDEC MO-153 ABT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) PCB Layout Reference View Exposed thermal pad (bottom surface) C C Package LP, 16-Pin TSSOP Copyright ©2008-2009, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com