A40MX04-1PL100ES

A42MX16-1PQ100ES ACTEL

Document overview

• Manufacturer or author: Provided By digicamel.com
• PDF pages: 123

Technical content

Features

• Single-Chip ASIC Alternative  3,000 to 54,000 System Gates  Up to 2.5 kbits Configurable Dual-Port SRAM  Fast Wide-Decode Circuitry  Up to 202 User-Programmable I/O Pins High Performance  5.6 ns Clock-to-Out  250 MHz Performance  5 ns Dual-Port SRAM Access  100 MHz FIFOs  7.5 ns 35-Bit Address Decode HiRel Features  Commercial, Industrial, Automotive, and Military Temperature Plastic Packages  Commercial, Military Temp erature, and MIL-STD-883 Ceramic Packages  QML Certification  Ceramic Devices Available to DSCC SMD Ease of Integration  Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os), with PCI-Compliant I/Os  Up to 100% Resource Utilization and 100% Pin Locking  Deterministic, User -Controllable Timing  Unique In-System Diagnostic and Verification Capability with Silicon Explorer II  Low Power Consumption  IEEE Standard 1149.1 (JTAG) Boundary Scan Testing Product Profile Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 Capacity System Gates SRAM Bits 3,000 6,000 14,000 24,000 36,000 54,000 2,560 Logic Modules Sequential Combinatorial Decode 295 547 348 336 624 608 954 912 1,230 1,184 SRAM Modules Dedicated Flip-Flops – – 348 624 954 1,230 Maximum Flip-Flops 147 273 516 928 1,410 1,822 Clocks 112 2 2 6 User I/O (maximum) 57 69 104 140 176 202 PCI ––– – Y e s Y e s Boundary Scan Test (BST) ––– – Y e s Y e s Packages (by pin count) PLCC PQFP VQFP TQFP CQFP PBGA 44, 68 100 44, 68, 84 100 100, 160 100 176 100, 160, 208 100 176 160, 208 176 208, 240 208, 256 272 v6.0

40MX and 42MX FPGA Families ii v6.0

Ordering Information

Blank = Commercial (0 to +70˚C) I = Industrial (–40 to +85˚C) M = Military (–55 to +125˚C) B = MIL-STD-883 A = Automotive (–40 to +125˚C) Application (Temperature Range) PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack BG = Plastic Ball Grid Array CQ = Ceramic Quad Flat Pack Blank = Standard Speed –1 = Approximately 15% Faster than Standard –2 = Approximately 25% Faster than Standard –3 = Approximately 35% Faster than Standard –F = Approximately 40% Slower than Standard A40MX02 = 3,000 System Gates A40MX04 = 6,000 System Gates A42MX09 = 14,000 System Gates A42MX16 = 24,000 System Gates A42MX24 = 36,000 System Gates A42MX36 = 54,000 S ystem Gates A42MX16 1 PQ 100 ES User I/Os Device PLCC 44-Pin PLCC 68-Pin PLCC 84-Pin PQFP 100-Pin PQFP 160-Pin PQFP 208-Pin PQFP 240-Pin VQFP 80-Pin VQFP 100-Pin TQFP 176-Pin PBGA 272-Pin A40MX04 34 57 69 69 – – – 69 – – – A42MX09 – – 72 83 101 – – – 83 104 – A42MX16 – – 72 83 125 140 – – 83 140 – A42MX24 – – 72 – 125 176 – – – 150 – A 4 2 M X 3 6 ––––– 1 7 6 2 0 2 ––– 2 0 2 Note: Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array

40MX and 42MX FPGA Families v6.0 iii Ceramic Device Resources Temperature Grade Offerings Speed Grade Offerings Contact your local Actel representative for device availability. User I/Os Device CQFP 208-Pin CQFP 256-Pin A42MX36 176 202 Note: Package Definitions CQFP = Ceramic Quad Flat Pack Package A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 44 C, I, M C, I, M PLCC 68 C, I, A, M C, I, M PLCC 84 C, I, A, M C, I, A, M C, I, M C, I, M PQFP 100 C, I, A, M C, I, A, M C, I, A, M C, I, M PQFP 160 C, I, A, M C, I, M C, I, A, M PQFP 208 C, I, A, M C, I, A, M C, I, A, M PQFP 240 C, I, A, M VQFP 80 C, I, A, M C, I, A, M VQFP 100 C, I, A, M C, I, A, M TQFP 176 C, I, A, M C, I, A, M C, I, A, M PBGA 272 C, I, M CQFP 208 C, M, B CQFP 256 C, M, B Note: C = Commercial I = Industrial A = Automotive M = Military B = MIL-STD-883 Class B – F S t d – 1– 2– 3 I ✓✓✓✓ A ✓ M ✓✓ B ✓✓ Note: Refer to the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX offerings.

v6.0 v Table of Contents 40MX and 42MX FPGA Families 40MX and 42MX FPGA Families Junction Temperature (T Package Pin Assignments

vi v6.0 Table of Contents 40MX and 42MX FPGA Families Datasheet Information

40MX and 42MX FPGA Families v6.0 1-1 40MX and 42MX FPGA Families General Description Actel's 40MX and 42MX familie s offer a cost-effective design solution at 5V. The MX devices are single-chip solutions and provide high performance while shortening the system design and development cycle. MX devices can integrate and consolidate logic implemented in multiple PALs, CPLDs, and FPGAs. Example applications includ e high-speed controllers and address decoding, peripheral bus interfaces, DSP, and co- processor functions. The MX device architecture is based on Actel’s patented antifuse technology implem ented in a 0.45µm triple- metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby power consumption of comparable FPGAs. Actel’s MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades. Actel’s A42MX24 and A42MX 36 devices also feature MultiPlex I/Os, which suppor t mixed-voltage systems, enable programmable PCI, deliver high-performance operation at both 5.0V an d 3.3V, and provide a low- power mode. The devices are fully compliant with the PCI Local Bus Specification (version 2.1). They deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance. The 42MX24 and 42MX36 devices include system-level features such as IEEE Stan dard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can efficiently address applications requiring wide datapath manipulation and can perform transformation functions such as those required for telecommunications, networking, and DSP. All MX devices are fully te sted over automotive and military temperature ranges. In addition, the largest member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened to MIL- STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and PQ208 devices are pin- compatible. MX Architectural Overview The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All devices within these families are composed of logic modules, I/O modules, routing resources and clock networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contai ns embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain wide- decode modules. Logic Modules The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources (Figure 1-1). The logic module can implem ent the four basic logic functions (NAND, AND, OR and NOR) in gates of two, three, or four inputs. The logic module can also implement a variety of D-latc hes, exclusivity functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the array; latches and flip- flops can be constructed from logic modules whenever required in the application. Figure 1-1 • 40MX Logic Module

40MX and 42MX FPGA Families v6.0 1-3 A42MX24 and A42MX36 devi ces contain D-modules, which are arranged around th e periphery of the device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that found in CPLD architectures ( Figure 1-4). The D-module allows A42MX24 and A42MX36 devices to perform wide- decode functions at speeds comparable to CPLDs and PALs. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic. Dual-Port SRAM Modules The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user -definable width and depth. A block diagram of the A42M X36 dual-port SRAM block is shown in Figure 1-5. The A42MX36 SRAM module s are true dual-port structures containing independent read and write ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WR AD[5:0], respectively) for 64x4-bit blocks. When config ured in byte mode, the highest order address bits (RDAD5 and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]), which are connected to segmented vertical routing tracks. The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring FIFO and LIFO queues. The ACTgen Macro Builder within Actel's Designer software provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can be used to implement registers for other user logic within the design. Figure 1-4  A42MX24 and A42MX36 D-Module Implementation

7 Inputs

Figure 1-5  A42MX36 Dual-Port SRAM Block SRAM Module 32 x 8 or 64 x 4 (256 Bits) Read Port Logic Write Port Logic RD[7:0] Routing Tracks Latches ReadLogic [5:0] RDAD[5:0] REN RCLK LatchesWD[7:0] Latches WRAD[5:0] Write Logic MODE BLKEN WEN WCLK [5:0] [7:0]

40MX and 42MX FPGA Families v6.0 1-7 Programming Device programming is supp orted through the Silicon Sculptor series of programmer s. Silicon Sculptor II is a compact, robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor II is desi gned to allow concurrent programming of multiple units from the same PC. Silicon Sculptor II programs devices independently to achieve the fastest program ming times possible. After being programmed, each fuse is verified to insure that it has been programmed correctly. Furthermore, at the end of programming, there are integrity tests that are run to ensure no extra fuses have been programmed. Not only does it test fuses (both programmed and nonprogrammed), Silicon Sculpt or II also allows self-test to verify its own hardware extensively. The procedure for programm ing an MX device using Silicon Sculptor II is as follows: 1. Load the .AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via In-House Programming from the factory. For more details on programming MX devices, please refer to the Programming Antifuse Devices and the Silicon Sculptor II user's guides. Power Supply MX devices are designed to operate in both 5.0V and 3.3V environments. In particular, 42MX devices can operate in mixed 5.0V/3.3V systems. Table 1 describes the voltage support of MX devices. Power-Up/Down in Mixed-Voltage Mode When powering up 42MX in mixed voltage mode (VCCA =5 . 0 V a n d VCCI = 3.3V), VCCA must be greater than or equal to V CCI throughout the power-up sequence. If VCCI exceeds VCCA during power up, either the I/Os' input protection junction on the I/Os will be forward-biased or the I/Os will be at logical HIGH, and I CC rises to high levels. For power-down, any sequence with V CCA and VCCI can be implemented. Low Power Mode 42MX devices have been designed with a Low Power Mode. This feature, activate d with setting the special LP pin to HIGH for a period longer than 800 ns, is particularly useful for batt ery-operated systems where battery life is a primary concern. In this mode, the core of the device is turned off and the device consumes minimal power with low standby curr ent. In addition, all input buffers are turned off, and all outputs and bidirectional buffers are tristated. Since the core of the device is turned off, the states of the registers are lost. The device must be re-initialized when exiting Low Power Mode. I/ Os can be driven during LP mode, and clock pins should be driven HIGH or LOW and should not float to avoid drawing current. To exit LP mode, the LP pin must be pulled LOW for over 200 µs to allow for charge pumps to power up, and device initialization will begin. Figure 1-11  Fuselock eu Table 1  Voltage Support of MX Devices Device V CC VCCA VCCI Maximum Input Tolerance Nominal Output Voltage 40MX 5.0V – – 5.5V 5.0V 3.3V – – 3.6V 3.3V 42MX – 5.0V 5.0V 5.5V 5.0V – 3.3V 3.3V 3.6V 3.3V – 5.0V 3.3V 5.5V 3.3V

40MX and 42MX FPGA Families 1-8 v6.0 Power Dissipation The general power consumption of MX devices is made up of static and dynamic power and can be expressed with the following equation: General Power Equation P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N + IOH * (VCCI – VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, on design details, and on the system I/O. The power can be divided into two components: static and active. Static Power Component The static power due to stan dby current is typically a small component of the overall power consumption. Standby power is calculated for commercial, worst-case conditions. The static powe r dissipation by TTL loads depends on the number of outputs driving, and on the DC load current. For instance, a 32-bit bus sinking 4mA at 0.33V will generate 42mW with all outputs driving LOW, and 140mW with all outputs driving HIGH. The actual dissipation will average so mewhere in between, as I/Os switch states with time. Active Power Component Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. Dynamic power consumption is frequency-dependent and is a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitances due to PC board traces and load de vice inputs. An additional component of the active power dissipation is the totem pole current in the CMOS tran sistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. The power dissipated by a CMOS circuit can be expressed by the equation: Power (µW) = CEQ * VCCA 2 * F(1) where: CEQ =Equivalent capacitance expressed in picofarads (pF) VCCA =Power supply in volts (V) F =Switching frequency in megahertz (MHz) Equivalent Capacitance Equivalent capacitance is calculated by measuring ICCactive at a specified freq uency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below. CEQ Values for Actel MX FPGAs Modules (C EQM)3.5 Input Buffers (C EQI)6.9 Output Buffers (C EQO)18.2 Routed Array Clock Buffer Loads (C EQCR)1.4 To calculate the active pow er dissipated from the complete design, the switching frequency of each part of the logic must be known. The equation below shows a piece-wise linear summation over all components. Power = VCCA 2 * [(m x CEQM * fm)Modules + (n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2) where: m = Number of logic modules switching at frequency fm n = Number of input buffers switching at frequency fn p = Number of output buffers switching at frequency fp q1 = Number of clock loads on the first routed array clock q2 = Number of clock loads on the second routed array clock r1 = Fixed capacitance due to first routed array clock r2 = Fixed capacitance due to second routed array clock

40MX and 42MX FPGA Families v6.0 1-9 Fixed Capacitance Values for MX FPGAs (pF) Test Circuitry and Silicon Explorer II Probe MX devices contain probing circuitry that provides built- in access to every node in a design, via the use of Silicon Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer software, allow users to examine any of the internal nets of the device while it is operating in a prototyping or a production system. The user can probe into an MX device without changing the placement and routing of the design and without using any additional resources. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle and providing a true representation of the device under actual functional situations. Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standa rd COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the PRA/PRB output pins for observation. Probing functionality is activated when the MODE pin is held HIGH. Figure 1-12 illustrates the interconnection between Silicon Explorer II and 40MX devices, while Figure 1-13 on page 1-10 illustrates the interconnection between Silicon Explorer II and 42MX devices To allow for probing capabilities, the security fuses must not be programmed. (Refer to <zBlue>“User Security” section on page 6 for the security fuses of 40MX and 42MX devices). Table 2 on page 1-10 summarizes the possible device configurations for probing. PRA and PRB pins are dual -purpose pins. When the "Reserve Probe Pin" is checked in the Designer software, PRA and PRB pins are reserved as dedicated outputs for probing. If PRA and PRB pins are required as user I/Os to ac hieve successful layout and "Reserve Probe Pin" is ch ecked, the layout tool will override the option and pl ace user I/Os on PRA and PRB pins. C EQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CL = Output load capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz fq2 = Average second routed array clock rate in MHz Device Type routed_Clk1 routed_Clk2 A40MX02 41.4 N/A A40MX04 68.6 N/A A42MX09 118 118 A42MX16 165 165 A42MX24 185 185 A42MX36 220 220 Figure 1-12  Silicon Explorer II Setup with 40MX 40MX Silicon Explorer II PRAPRB SDO DCLK SDI MODE Serial Connection to Windows PC

16 Logic Analyzer Channels

40MX and 42MX FPGA Families 1-10 v6.0 Design Consideration It is recommended to use a series 70 Ω termination resistor on every probe connector (SDI, SDO, MODE, DCLK, PRA and PRB). The 70 Ω series termination is used to prevent data transmission corruption during probing and reading back the checksum. IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry 42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers and instruction register (Figure 1-14 on page 1-11 ). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/ PRELOAD and BYPASS) and some optional instructions. Table 3 on page 1-11 describes the ports that control JTAG testing, while Table 4 on page 1-11 describes the test instructions supported by these MX devices. Each test section is accessed through the TAP, which has four associated pins: TCK (t est clock input), TDI and TDO (test data input and out put), and TMS (test mode selector). The TAP controller is a four -bit state machine. The '1's and '0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architec ture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. 42MX24 and 42MX36 devices s upport three types of test data registers: bypass, device identification, and boundary scan. The bypass regi ster is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Figure 1-13  Silicon Explorer II Setup with 42MX Table 2  Device Configuration Options for Probe Capability Security Fuse(s) Programmed MODE PRA, PRB 1 SDI, SDO, DCLK1 No LOW User I/Os 2 User I/Os2 No HIGH Probe Circuit Outputs Probe Circuit Inputs Yes – Probe Circuit Secured Probe Circuit Secured Notes: 1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidi rectional ports. Since these pins are active during probing, inp ut signals will not pass through these pins and may cause contention. 2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the <zBlue>“Pin Descriptions” section on page 77 for information on unused I/O pins. 42MX Silicon Explorer II PRAPRB SDO DCLK SDI MODE Serial Connection to Windows PC

40MX and 42MX FPGA Families v6.0 1-11 Each I/O cell has three boundary -scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary- scan register chain, which st arts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O buffer to capt ure and load data into the register to control or observe the logic state of each I/O. Figure 1-14  42MX IEEE 1149.1 Boundary Scan Circuitry Table 3  Test Access Port Descriptions Port Description TMS (Test Mode Select) Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK). TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency for TCK is 20 MHz. TDI (Test Data Input) Serial input for instruction and test data. Da ta is captured on the rising edge of the test logic clock. TDO (Test Data Output) Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high impedance) when data scanning is not in progress. Table 4  Supported BST Public Instructions Instruction IR Code (IR2.IR0) Instruction Type Description EXTEST 000 Mandatory Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. SAMPLE/PRELOAD 001 Mandatory Allows a snapshot of the signals at the device pins to be captured and examined during operation HIGH Z 101 Optional Tristates all I/Os to allow external signals to drive pins. Please refer to the IEEE Standard 1149.1 specification. CLAMP 110 Optional Allows state of signals driven from component pins to be determined from the Boundary-Scan Register. Please refer to the IEEE Standard 1149.1 specification for details. BYPASS 111 Mandatory Enables the bypass regi ster between the TDI and TDO pins. The test data passes through the selected device to adjacent devices in the test chain. Boundary Scan Register Instruction Decode Control Logic TAP Controller Instruction Register Bypass Register TMS TCK TDI Output MUX TDO JTAG JTAG

40MX and 42MX FPGA Families v6.0 1-13 Development Tool Support The MX family of FPGAs is fully supported by both Actel's Libero™ Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is a design management environment th at streamlines the design flow. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify® for Acte l from Synplicity®, ViewDraw for Actel from Mentor Graphics, ModelSim™ HDL Simulator from Mentor Graphics®, WaveFormer Lite™ from SynaptiCAD™, and Designer software from Actel. Refer to the Libero IDE flow (located on Actel’s website) diagram for more information. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-r oute, and a world-class integrated static timing an alyzer and constraints editor. With the Designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. Additionally, the back- annotation flow is compat ible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel’s integrated verification and logic analysis tool. Anot her tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Me ntor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Related Documents Application Notes Actel BSDL Files Format Description www.actel.com/documents/BSDLformat_AN.pdf Programming Antifuse Devices http://www.actel.com/documents/ AntifuseProgram_AN.pdf Actel's Implementation of Security in Actel Antifuse FPGAs www.actel.com/documents/Antifuse_Security_AN.pdf User’s Guides and Manuals Antifuse Macro Library Guide www.actel.com/documents/libguide_UG.pdf Silicon Sculptor II www.actel.com/techdocs/manuals/default.asp#programmers Miscellaneous Libero IDE Flow Diagram www.actel.com/products/tools/libero/flow.html

40MX and 42MX FPGA Families 1-14 v6.0 5.0V Operating Conditions Table 6  Absolute Maximum Ratings for 40MX Devices* Symbol Parameter Limits Units VCC DC Supply Voltage –0.5 to +7.0 V VI Input Voltage –0.5 to V CC+0.5 V VO Output Voltage –0.5 to V CC+0.5 V tSTG Storage Temperature –65 to +150 °C Note: *Stresses beyond those listed u nder "Absolute Maximum Ratings" may cause pe rmanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 7  Absolute Maximum Ratings for 42MX Devices* Symbol Parameter Limits Units VCCI DC Supply Voltage for I/Os –0.5 to +7.0 V VCCA DC Supply Voltage for Array –0.5 to +7.0 V VI Input Voltage –0.5 to V CCI+0.5 V VO Output Voltage –0.5 to V CCI+0.5 V tSTG Storage Temperature –65 to +150 °C Note: *Stresses beyond those listed u nder "Absolute Maximum Ratings" may cause pe rmanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 8  Recommended Operating Conditions Parameter Commercial I ndustrial Military Units Temperature Range* 0 to +70 -40 to +85 –55 to +125 °C Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.

40MX and 42MX FPGA Families v6.0 1-15 Table 9  5V TTL Electrical Specifications Symbol Parameter Commercial Commercial -F Industrial Military VOH 1 IOH = -10mA 2.4 2.4 V IOH = -4mA 3.7 3.7 V VOL 1 IOL = 10mA 0.5 0.5 V IOL = 6mA 0.4 0.4 V IIL VIN = 0.5V -10 -10 -10 -10 µA IIH VIN = 2.7V -10 -10 -10 -10 µA Input Transition Time, TR and TF 500 500 500 500 ns CIO I / O C a p a c i t a n c e 1 01 01 01 0 p F Standby Current, ICC A40MX02, A40MX04 3 2 51 02 5 m A A42MX09 5 25 25 25 mA A42MX16 6 25 25 25 mA A42MX24, A42MX36 20 25 25 25 mA Low-Power Mode Standby Current 42MX devices only 0.5 I CC - 5.0 I CC - 5.0 I CC - 5.0 mA IIO, I/O source sink current Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html) Notes: 1. Only one output tested at a time. V CC/VCCI = min. 2. All outputs unloaded. All inputs = V CC/VCCI or GND.

40MX and 42MX FPGA Families 1-16 v6.0 3.3V Operating Conditions Table 10  Absolute Maximum Ratings for 40MX Devices* Symbol Parameter Limits Units VCC DC Supply Voltage –0.5 to +7.0 V VI Input Voltage –0.5 to V CC+0.5 V VO Output Voltage –0.5 to V CC+0.5 V tSTG Storage Temperature –65 to +150 °C Note: *Stresses beyond those listed u nder "Absolute Maximum Ratings" may cause pe rmanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 11  Absolute Maximum Ratings for 42MX Devices* Symbol Parameter Limits Units VCCI DC Supply Voltage for I/Os –0.5 to +7.0 V VCCA DC Supply Voltage for Array –0.5 to +7.0 V VI Input Voltage –0.5 to V CCI+0.5 V VO Output Voltage –0.5 to V CCI+0.5 V tSTG Storage Temperature –65 to +150 °C Note: *Stresses beyond those listed u nder "Absolute Maximum Ratings" may cause pe rmanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 12  Recommended Operating Conditions Parameter Commercial I ndustrial Military Units Temperature Range* 0 to +70 –40 to +85 –55 to +125 °C Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades.

40MX and 42MX FPGA Families v6.0 1-17 3.3V LVTTL Electrical Specifications Table 13  3.3V LVTTL Electrical Specifications Symbol Parameter Commercial Commercial -F Industrial Military VOH 1 IOH = –4mA 2.15 2.15 2.4 2.4 V VOL 1 IOL = 6mA 0.4 0.4 0.48 0.48 V IIL –10 –10 –10 –10 µA IIH –10 –10 –10 –10 µA Input Transition Time, TR and TF 500 500 500 500 ns CIO I/O Capacitance 10 10 10 10 pF Standby Current, ICC

2 A40MX02,

A42MX24, A42MX36 15 25 25 25 mA Low-Power Mode Standby Current 42MX devices only 0.5 I CC - 5.0 I CC - 5.0 I CC - 5.0 mA IIO, I/O source sink current Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html) Notes: 1. Only one output tested at a time. V CC/VCCI = min. 2. All outputs unloaded. All inputs = V CC/VCCI or GND.

40MX and 42MX FPGA Families 1-18 v6.0 Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) Mixed 5.0V/3.3V Electrical Specifications Table 14  Absolute Maximum Ratings* Symbol Parameter Limits Units V CCI DC Supply Voltage for I/Os –0.5 to +7.0 V VCCA DC Supply Voltage for Array –0.5 to +7.0 V VI Input Voltage –0.5 to V CCI+0.5 V VO Output Voltage –0.5 to V CCI+0.5 V tSTG Storage Temperature –65 to +150 °C Note: *Stresses beyond those listed u nder "Absolute Maximum Ratings" may cause pe rmanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 15  Recommended Operating Conditions Parameter Commercial I ndustrial Military Units Temperature Range* 0 to +70 -40 to +85 –55 to +125 °C Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. Table 16  Mixed 5.0V/3.3V Electrical Specifications Symbol Parameter Commercial Commercial '-F 'Industrial Military VOH 1 IOH = –10mA 2.4 2.4 V IOH = –4mA 3.7 3.7 V VOL 1 IOL = 10mA 0.5 0.5 V IOL = 6mA 0.4 0.4 V IL VIN = 0.5V –10 –10 –10 –10 µA IH VIN = 2.7V –10 –10 –10 –10 µA Input Transition Time, TR and TF 500 500 500 500 ns CIO I/O Capacitance 10 10 10 10 pF Standby Current, ICC

2 A42MX09 5 25 25 25 mA

A42MX24, A42MX36 20 25 25 25 mA Low-Power Mode Standby Current 0.5 I CC - 5.0 I CC - 5.0 I CC - 5.0 mA IIO I/O source sink current Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html) Notes: 1. Only one output tested at a time. V CCI = min. 2. All outputs unloaded. All inputs = V CCI or GND.

40MX and 42MX FPGA Families v6.0 1-19 Output Drive Characteristics for 5.0V PCI Signaling MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 1-16 on page 1-21 shows the typical output drive characteristics of the MX device s. MX output drivers are co mpliant with the PCI Local Bus Specification. Table 17  DC Specification (5.0V PCI Signaling)1 PCI MX Symbol Parameter Condition Min. Max. Min. Max. Units VCCI Supply Voltage for I/Os 4.75 5.25 4.75 5.25 2 V VIH Input High Voltage 2.0 V CC + 0.5 2.0 V CCI + 0.3 V VIL Input Low Voltage –0.5 0.8 –0.3 0.8 V IIH Input High Leakage Current V IN = 2.7V 70 — 10 µA IIL Input Low Leakage Current V IN=0.5V –70 — –10 µA VOH Output High Voltage I OUT = –2 mA IOUT = –6 mA 2.4 3.84 V VOL Output Low Voltage I OUT = 3 mA, 6 mA 0.55 — 0.33 V CIN Input Pin Capacitance 10 — 10 pF CCLK CLK Pin Capacitance 5 12 — 10 pF LPIN Pin Inductance 20 — < 8 nH 3 nH Notes: 2. Maximum rating for V CCI –0.5V to 7.0V. 3. Dependent upon the chosen package. PCI recommends QFP a nd BGA packaging to reduce pin inductance and capacitance. Table 18  AC Specifications (5.0V PCI Signaling)* PCI MX Symbol Parameter Condition Min. Max. Min. Max. Units ICL Low Clamp Current –5 < V IN ≤ –1 –25 + (V IN +1) /0.015 –60 –10 mA Slew (r) Output Rise Slew Rate 0.4V to 2.4V load 1 5 1.8 2.8 V/ns Slew (f) Output Fall Slew Rate 2.4V to 0.4V load 1 5 2.8 4.3 V/ns

40MX and 42MX FPGA Families 1-20 v6.0 Output Drive Characteristics for 3.3V PCI Signaling Table 19  DC Specification (3.3V PCI Signaling)1 PCI MX Symbol Parameter Condition Min. Max. Min. Max. Units VCCI Supply Voltage for I/Os 3.0 3.6 3.0 3.6 V VIH Input High Voltage 0.5 V CC + 0.5 0.5 V CCI + 0.3 V VIL Input Low Voltage –0.5 0.8 –0.3 0.8 V IIH Input High Leakage Current V IN = 2.7V 70 10 µA IIL Input Leakage Current –70 –10 µA VOH Output High Voltage I OUT = –2 mA 0.9 3.3 V VOL Output Low Voltage I OUT = 3 mA, 6 mA 0.1 0.1 V CCI V CIN Input Pin Capacitance 10 10 pF CCLK CLK Pin Capacitance 5 12 10 pF LPIN Pin Inductance 20 < 8 nH 3 nH Notes: 2. Maximum rating for V CCI –0.5V to 7.0V. 3. Dependent upon the chosen package. PCI recommends QFP a nd BGA packaging to reduce pin inductance and capacitance. Table 20  AC Specifications for (3.3V PCI Signaling)* PCI MX Symbol Parameter Condition Min. Max. Min. Max. Units ICL Low Clamp Current –5 < V IN ≤ –1 –25 + (V IN +1) /0.015 –60 –10 mA Slew (r) Output Rise Slew Rate 0.2V to 0.6V load 1 4 1.8 2.8 V/ns Slew (f) Output Fall Slew Rate 0.6V to 0.2V load 1 4 2.8 4.0 V/ns

40MX and 42MX FPGA Families v6.0 1-21 Figure 1-16  Typical Output Drive Characteristics (Based Upon Measured Data) 01 2 3 4 5 6 MX PCI IOL MX PCI IOH PCI I OL Maximum PCI I OL Minimum PCI I OH Minimum PCI I OH Maximum Voltage Out (V) –0.20 –0.15 –0.10 –0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Current (A)

40MX and 42MX FPGA Families 1-22 v6.0 Junction Temperature (TJ) The temperature variable in the Designer software refers to the junction temper ature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than th e ambient temperature. EQ 1-1, shown below, can be used to calculate junction temperature. EQ 1-1 Junction Temperature = ∆T + Ta(1) Where: Ta = Ambient Temperature ∆T = Temperature gradient between junction (silicon) and ambient ∆T = θja * P(2) P = Power θja = Junction to ambient of package. θja numbers are located in the Package Ther mal Characteristics table below. Package Thermal Characteristics The device junction-to-case thermal characteristic is θjc, and the junction-to-ambien t air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. The maximum junction temperature is 150°C. Maximum power dissipation for commercial- and industrial-grade devices is a function of θja. A sample calculation of the absolute maximum power dissipation allowed for a TQFP 176-pin package at commercial temperature and still air is as follow: The maximum power dissipat ion for military-grade devi ces is a function of θjc. A sample calculation of the absolute maximum power dissipation allowed for CQFP 208-pin package at military temperature and still air is as follows: Table 21  Package Thermal Characteristics Plastic Packages Pin Count θjc θja UnitsStill Air 1.0 m/s 200 ft/min. 2.5 m/s 500 ft/min. Plastic Quad Flat Pack 100 12.0 27.8 23.4 21.2 °C/W Plastic Quad Flat Pack 160 10.0 26.2 22.8 21.1 °C/W Plastic Quad Flat Pack 208 8.0 26.1 22.5 20.8 °C/W Plastic Quad Flat Pack 240 8.5 25.6 22.3 20.8 °C/W Plastic Leaded Chip Carrier 44 16.0 20.0 24.5 22.0 °C/W Plastic Leaded Chip Carrier 68 13.0 25.0 21.0 19.4 °C/W Plastic Leaded Chip Carrier 84 12.0 22.5 18.9 17.6 °C/W Thin Plastic Quad Flat Pack 176 11.0 24.7 19.9 18.0 °C/W Very Thin Plastic Quad Flat Pack 80 12.0 38.2 31.9 29.4 °C/W Very Thin Plastic Quad Flat Pack 100 10.0 35.3 29.4 27.1 °C/W Plastic Ball Grid Array 272 3.0 18.3 14.9 13.9 °C/W Ceramic Packages Ceramic Quad Flat Pack 208 2.0 22.0 19.8 18.0 °C/W Ceramic Quad Flat Pack 256 2.0 20.0 16.5 15.0 °C/W Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. ( °C)– Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. ( °C)–

40MX and 42MX FPGA Families 1-26 v6.0 Sequential Module Timing Characteristics Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops. Figure 1-25  Flip-Flops and Latches tWCLKA tWA SYN tHD tSU EN A tSUD tRS tA tWCLKI tCO tHENA G, CLK E Q PRE, CLR (Positive Edge-Triggered) D E CLK CLR PRE Y

40MX and 42MX FPGA Families 1-30 v6.0 Predictable Performance: Tight Delay Distributions Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay in creases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks. The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel’s patented antifuse offers a very low resistive/ capacitive interconnect. The antifuses, fabricated in 0.45 µm lithography, offer nominal levels of 100 Ω resistance and 7.0fF capacitance per antifuse. MX fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The proprietary architectu re limits the number of antifuses per path to a maximum of four, with 90 percent of interconnects using only two antifuses. Timing Characteristics Device timing characteristics fall into three categories: family-dependent, device-dependent, and design- dependent. The input and output buffer characteristics are common to all MX device s. Internal routing delays are device-dependent; actual delays are not determined until after place-and-route of the user's design is complete. Delay values may then be determined by using the Designer software utility or by performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment in Actel's Designer software prior to placement and routing. Up to 6% of the nets in a design may be designated as critical. Long Tracks Some nets in the design use long tracks, which are special routing resources th at span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections, which increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks add appr oximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (FO=8) routing delays in th e data sheet specifications section, shown in Table 28 on page 1-36. Timing Derating MX devices are manufactured with a CMOS process. Therefore, device perfor mance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temp erature and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature and worst-case processing.

40MX and 42MX FPGA Families v6.0 1-31 Temperature and Voltage Derating Factors Table 22  42MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCCA = 5.0V) 42MX Voltage Temperature –55°C –40°C 0°C 25°C 70°C 85°C 125°C Note: This derating factor applies to all routing and propagation delays. Figure 1-34  42MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25°C, VCCA = 5.0V) 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 Voltage (V) Derating Factor –55˚C –40˚C 0˚C 25˚C 70˚C 85˚C 125˚C

40MX and 42MX FPGA Families 1-32 v6.0 Table 23  40MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCC = 5.0V) 40MX Voltage Temperature –55°C –40°C 0°C 25°C 70°C 85°C 125°C Note: This derating factor applies to all routing and propagation delays. Figure 1-35  40MX Junction Temperature and Voltage Derating Curves (Normalized to T J = 25°C, VCC = 5.0V) Factor 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 Voltage (V) Derating –55˚C –40˚C 0˚C 25˚C 70˚C 85˚C 125˚C

40MX and 42MX FPGA Families v6.0 1-33 Table 24  42MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCCA = 3.3V) 42MX Voltage Temperature –55°C –40°C 0°C 25°C 70°C 85°C 125°C Note: This derating factor applies to all routing and propagation delays. Figure 1-36  42MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25°C, VCCA = 3.3V) (V) 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 Voltage (V) Derating Factor 3.00 3.30 3.60 55˚C 40˚C 0˚C 25˚C 70˚C 85˚C 125˚C

40MX and 42MX FPGA Families 1-34 v6.0 Table 25  40MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCC = 3.3V) 40MX Voltage Temperature –55°C –40°C 0°C 25°C 70°C 85°C 125°C Note: This derating factor applies to all routing and propagation delays. Figure 1-37  40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25°C, VCC = 3.3V) 3.00 3.30 3.60 Voltage (V) Derating Factor 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 55˚C 40˚C 0˚C 25˚C 70˚C 85˚C 125˚C

40MX and 42MX FPGA Families v6.0 1-35 PCI System Timing Specification Table 26 and Table 27 list the critical PCI timing parameters and the corresponding timing parameters for the MX PCI-compliant devices. PCI Models Actel provides synthesizable VHDL and Verilog-HDL models for a PCI Target in terface, a PCI Target and Target+DMA Master interface. Contact your Actel sales representative for more details. Table 26  Clock Specification for 33 MHz PCI Symbol Parameter PCI A42MX24 A42MX36 tCYC CLK Cycle Time 30 – 4.0 – 4.0 – ns tHIGH CLK High Time 11 – 1.9 – 1.9 – ns tLOW C L K L o w T i m e 1 1 –1 . 9–1 . 9– n s Table 27  Timing Parameters for 33 MHz PCI PCI A42MX24 A42MX36 t VAL CLK to Signal Valid—Bused Signals 2 11 2.0 9.0 2.0 9.0 ns tVAL(PTP) CLK to Signal Valid—Point-to-Point 2 2 12 2.0 9.0 2.0 9.0 ns tON Float to Active 2 – 2.0 4.0 2.0 4.0 ns tOFF Active to Float – 28 – 8.3 1 –8 . 3 1 ns tSU Input Set-Up Time to CLK—Bused Signals 7 – 1.5 – 1.5 – ns tSU(PTP) Input Set-Up Time to CLK—Point-to-Point 10, 12 2 –1 . 5–1 . 5– n s tH Input Hold to CLK 0 – 0 – 0 – ns Notes: 1. T OFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns. 2. REQ# and GNT# are point-to-poi nt signals and have different output valid dela y and input setup times than do bussed signals. GNT# has a setup of 10; REW# has a setup of 12.

40MX and 42MX FPGA Families 1-36 v6.0 Timing Characteristics Table 28  A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCC = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Propagation Delays Logic Module Predicted Routing Delays1 Logic Module Sequential Timing2 tHD tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width fMAX Flip-Flop (Latch) Clock Frequency (FO = 128) 181 168 154 134 80 MHz Input Module Propagation Delays Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35pF loading.

40MX and 42MX FPGA Families v6.0 1-37 Input Module Predicted Routing Delays1 Global Clock Network t CKH Input Low to HIGH FO = 16 FO = 128 4.6 4.6 5.3 5.3 6.0 6.0 7.0 7.0 9.8 9.8 ns tCKL Input High to LOW FO = 16 FO = 128 4.8 4.8 5.6 5.6 6.3 6.3 7.4 7.4 10.4 10.4 ns tPWH Minimum Pulse Width HIGH FO = 16 FO = 128 2.2 2.4 2.6 2.7 2.9 3.1 3.4 3.6 4.8 5.1 ns tPWL Minimum Pulse Width LOW FO = 16 FO = 128 2.2 2.4 2.6 2.7 2.9 3.01 3.4 3.6 4.8 5.1 ns tCKSW Maximum Skew FO = 16 FO = 128 0.4 0.5 0.5 0.6 0.5 0.7 0.6 0.8 0.8 1.2 ns tP Minimum Period FO = 16 FO = 128 4.7 4.8 5.4 5.6 6.1 6.3 7.2 7.5 10.0 10.4 ns fMAX Maximum Frequency FO = 16 FO = 128 188 181 175 168 160 154 139 134 MHz Table 28  A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35pF loading.

40MX and 42MX FPGA Families 1-38 v6.0 TTL Output Module Timing4 tENZH Enable Pad Z to HIGH tENZL Enable Pad Z to LOW tENHZ Enable Pad HIGH to Z tENLZ Enable Pad LOW to Z CMOS Output Module Timing4 tENZH Enable Pad Z to HIGH tENZL Enable Pad Z to LOW tENHZ Enable Pad HIGH to Z tENLZ Enable Pad LOW to Z Table 28  A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35pF loading.

40MX and 42MX FPGA Families v6.0 1-39 Table 29  A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCC = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Propagation Delays Logic Module Predicted Routing Delays1 Logic Module Sequential Timing2 tHD tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width fMAX Flip-Flop (Latch) Clock Frequency (FO = 128) 109 101 92 80 48 MHz Input Module Propagation Delays Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-40 v6.0 Input Module Predicted Routing Delays1 Global Clock Network t CKH Input LOW to HIGH FO = 16 FO = 128 6.4 6.4 7.4 7.4 8.3 8.3 9.8 9.8 13.7 13.7 ns tCKL Input HIGH to LOW FO = 16 FO = 128 6.7 6.7 7.8 7.8 8.8 8.8 10.4 10.4 14.5 14.5 ns tPWH Minimum Pulse Width HIGH FO = 16 FO = 128 3.1 3.3 3.6 3.8 4.1 4.3 4.8 5.1 6.7 7.1 ns tPWL Minimum Pulse Width LOW FO = 16 FO = 128 3.1 3.3 3.6 3.8 4.1 4.3 4.8 5.1 6.7 7.1 ns tCKSW Maximum Skew FO = 16 FO = 128 0.6 0.8 0.6 0.9 0.7 1.0 0.8 1.2 1.2 1.6 ns tP Minimum Period FO = 16 FO = 128 6.5 6.8 7.5 7.8 8.5 8.9 10.1 10.4 14.1 14.6 ns fMAX Maximum Frequency FO = 16 FO = 128 113 109 105 101 MHz TTL Output Module Timing4 Table 29  A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-41 CMOS Output Module Timing4 Table 29  A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-42 v6.0 Table 30  A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCC = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Propagation Delays Logic Module Predicted Routing Delays1 Logic Module Sequential Timing2 tHD tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width fMAX Flip-Flop (Latch) Clock Frequency (FO = 128) 181 167 154 134 80 MHz Input Module Propagation Delays Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns . Use the Timer utility from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-43 Input Module Predicted Routing Delays1 Global Clock Network t CKH Input Low to HIGH FO = 16 FO = 128 4.6 4.6 5.3 5.3 6.0 6.0 7.0 7.0 9.8 9.8 ns tCKL Input High to LOW FO = 16 FO = 128 4.8 4.8 5.6 5.6 6.3 6.3 7.4 7.4 10.4 10.4 ns tPWH Minimum Pulse Width HIGH FO = 16 FO = 128 2.2 2.4 2.6 2.7 2.9 3.1 3.4 3.6 4.8 5.1 ns tPWL Minimum Pulse Width LOW FO = 16 FO = 128 2.2 2.4 2.6 2.7 2.9 3.01 3.4 3.6 4.8 5.1 ns tCKSW Maximum Skew FO = 16 FO = 128 0.4 0.5 0.5 0.6 0.5 0.7 0.6 0.8 0.8 1.2 ns tP Minimum Period FO = 16 FO = 128 4.7 4.8 5.4 5.6 6.1 6.3 7.2 7.5 10.0 10.4 ns fMAX Maximum Frequency FO = 16 FO = 128 188 181 175 168 160 154 139 134 MHz TTL Output Module Timing4 Table 30  A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns . Use the Timer utility from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-44 v6.0 CMOS Output Module Timing1 Table 30  A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns . Use the Timer utility from the Designer software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-45 Table 31  A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCC = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Propagation Delays Logic Module Predicted Routing Delays1 Logic Module Sequential Timing2 tHD tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width fMAX Flip-Flop (Latch) Clock Frequency (FO = 128) 109 101 92 80 48 MHz Input Module Propagation Delays Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-46 v6.0 Input Module Predicted Routing Delays1 Global Clock Network t CKH Input LOW to HIGH FO = 16 FO = 128 6.4 6.4 7.4 7.4 8.4 8.4 9.9 9.9 13.8 13.8 ns tCKL Input HIGH to LOW FO = 16 FO = 128 6.8 6.8 7.8 7.8 8.9 8.9 10.4 10.4 14.6 14.6 ns tPWH Minimum Pulse Width HIGH FO = 16 FO = 128 3.1 3.3 3.6 3.8 4.1 4.3 4.8 5.1 6.7 7.1 ns tPWL Minimum Pulse Width LOW FO = 16 FO = 128 3.1 3.3 3.6 3.8 4.1 4.3 4.8 5.1 6.7 7.1 ns tCKSW Maximum Skew FO = 16 FO = 128 0.6 0.8 0.6 0.9 0.7 1.0 0.8 1.2 1.2 1.6 ns tP Minimum Period FO = 16 FO = 128 6.5 6.8 7.5 7.8 8.5 8.9 10.1 10.4 14.1 14.6 ns fMAX Maximum Frequency FO = 16 FO = 128 113 109 105 101 MHz TTL Output Module Timing4 Table 31  A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-47 CMOS Output Module Timing4 Table 31  A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCC = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Desi gner software to check the hold time for this macro. 4. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-48 v6.0 Table 32  A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Propagation Delays1 Logic Module Predicted Routing Delays2 Logic Module Sequential Timing3, 4 tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width fMAX Flip-Flop (Latch) Clock Frequency 268 244 224 195 117 MHz Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-49 Input Module Propagation Delays Input Module Predicted Routing Delays2 Global Clock Network tCKH Input LOW to HIGH FO = 32 FO = 256 2.4 2.7 2.7 3.0 3.0 3.4 3.6 4.0 5.0 5.5 ns ns tCKL Input HIGH to LOW FO = 32 FO = 256 3.5 3.9 3.9 4.3 4.4 4.9 5.2 5.7 7.3 8.0 ns ns tPWH Minimum Pulse Width HIGH FO = 32 FO = 256 1.2 1.3 1.4 1.5 1.5 1.7 1.8 2.0 2.5 2.7 ns ns tPWL Minimum Pulse Width LOW FO = 32 FO = 256 1.2 1.3 1.4 1.5 1.5 1.7 1.8 2.0 2.5 2.7 ns ns tCKSW Maximum Skew FO = 32 FO = 256 0.3 0.3 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 ns ns tSUEXT Input Latch External Set-Up FO = 32 FO = 256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO = 32 FO = 256 2.3 2.2 2.6 2.4 3.0 3.3 3.5 3.9 4.9 5.5 ns ns tP Minimum Period FO = 32 FO = 256 3.4 3.7 3.7 4.1 4.0 4.5 4.7 5.2 7.8 8.6 ns ns fMAX Maximum Frequency FO = 32 FO = 256 296 268 269 244 247 224 215 195 129 117 MHz MHz Table 32  A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-50 v6.0 TTL Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad), 64 Clock Loading tACO Array Clock-to-Out (Pad-to-Pad),

64 Clock Loading

Table 32  A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-51 CMOS Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad), 64 Clock Loading tACO Array Clock-to-Out (Pad-to-Pad), Table 32  A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-52 v6.0 Table 33  A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Propagation Delays1 Logic Module Predicted Routing Delays2 Logic Module Sequential Timing 3, 4 tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width fMAX Flip-Flop (Latch) Clock Frequency 161 146 135 117 70 MHz Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-53 Input Module Propagation Delays Input Module Predicted Routing Delays2 Global Clock Network tCKH Input LOW to HIGH FO = 32 FO = 256 4.1 4.5 4.5 5.0 5.1 5.6 6.0 6.7 8.4 9.3 ns ns tCKL Input HIGH to LOW FO = 32 FO = 256 5.0 5.4 5.5 6.0 6.2 6.8 7.3 8.0 10.2 11.2 ns ns tPWH Minimum Pulse Width HIGH FO = 32 FO = 256 1.7 1.9 1.9 2.1 2.1 2.3 2.5 2.7 3.5 3.8 ns ns tPWL Minimum Pulse Width LOW FO = 32 FO = 256 1.7 1.9 1.9 2.1 2.1 2.3 2.5 2.7 3.5 3.8 ns ns tCKSW Maximum Skew FO = 32 FO = 256 0.4 0.4 0.5 0.5 0.5 0.5 0.6 0.6 0.9 0.9 ns ns tSUEXT Input Latch External Set-Up FO = 32 FO = 256 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO = 32 FO = 256 3.3 3.7 3.7 4.1 4.2 4.6 4.9 5.5 6.9 7.6 ns ns tP Minimum Period FO = 32 FO = 256 5.6 6.1 6.2 6.8 6.7 7.4 7.8 8.5 12.9 14.2 ns ns fMAX Maximum Frequency FO = 32 FO = 256 177 161 161 146 148 135 129 117 MHz MHz Table 33  A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-54 v6.0 TTL Output Module Timing5 tENZH Enable Pad Z to HIGH tENZL Enable Pad Z to LOW tENHZ Enable Pad HIGH to Z tENLZ Enable Pad LOW to Z tLCO I/O Latch Clock-to- Out (Pad-to-Pad), (Pad-to-Pad), dTLH Capacity Loading, LOW to HIGH dTHL Capacity Loading, HIGH to LOW Table 33  A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-55 CMOS Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad), 64 Clock Loading tACO Array Clock-to-Out (Pad-to-Pad), Table 33  A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-56 v6.0 Table 34  A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75V , TJ = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Propagation Delays1 Logic Module Predicted Routing Delays2 Logic Module Sequential Timing3,4 tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width fMAX Flip-Flop (Latch) Clock Frequency 215 195 179 156 94 MHz Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-57 Input Module Propagation Delays Input Module Predicted Routing Delays2 Global Clock Network t CKH Input LOW to HIGH FO = 32 FO = 384 2.6 2.9 2.9 3.2 3.3 3.6 3.9 4.3 5.4 6.0 ns ns tCKL Input HIGH to LOW FO = 32 FO = 384 3.8 4.5 4.2 5.0 4.8 5.6 5.6 6.6 7.8 9.2 ns ns tPWH Minimum Pulse Width HIGH FO = 32 FO = 384 3.2 3.7 3.5 4.1 4.0 4.6 4.7 5.4 6.6 7.6 ns ns tPWL Minimum Pulse Width LOW FO = 32 FO = 384 3.2 3.7 3.5 4.1 4.0 4.6 4.7 5.4 6.6 7.6 ns ns tCKSW Maximum Skew FO = 32 FO = 384 0.3 0.3 0.4 0.4 0.4 0.4 0.5 0.5 0.7 0.7 ns ns tSUEXT Input Latch External Set-Up FO = 32 FO = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO = 32 FO = 384 2.8 3.2 3.1 3.5 5.5 4.0 4.1 4.7 5.7 6.6 ns ns tP Minimum Period FO = 32 FO = 384 4.2 4.6 4.67 5.1 5.1 5.6 5.8 6.4 9.7 10.7 ns ns fMAX Maximum Frequency FO = 32 FO = 384 237 215 215 195 198 179 172 156 103 MHz MHz Table 34  A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V , TJ = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-58 v6.0 TTL Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad), 64 Clock Loading tACO Array Clock-to-Out (Pad-to-Pad), CMOS Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad), 64 Clock Loading tACO Array Clock-to-Out (Pad-to-Pad), Table 34  A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V , TJ = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-59 Table 35  A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Propagation Delays1 Logic Module Predicted Routing Delays2 Logic Module Sequential Timing3, 4 tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width fMAX Flip-Flop (Latch) Clock Frequency 129 117 108 94 56 MHz Notes: 1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-60 v6.0 Input Module Propagation Delays Input Module Predicted Routing Delays2 Global Clock Network t CKH Input LOW to HIGH FO = 32 FO = 384 4.4 4.8 4.8 5.3 5.5 6.0 6.5 7.1 9.0 9.9 ns ns tCKL Input HIGH to LOW FO = 32 FO = 384 5.3 6.2 5.9 6.9 6.7 7.9 7.8 9.2 11.0 12.9 ns ns tPWH Minimum Pulse Width HIGH FO = 32 FO = 384 5.7 6.6 6.3 7.4 7.1 8.3 8.4 9.8 11.8 13.7 ns ns tPWL Minimum Pulse Width LOW FO = 32 FO = 384 5.3 6.2 5.9 6.9 6.7 7.9 7.8 9.2 11.0 12.9 ns ns tCKSW Maximum Skew FO = 32 FO = 384 0.5 2.2 0.5 2.4 0.6 2.7 0.7 3.2 1.0 4.5 ns ns tSUEXT Input Latch External Set-Up FO = 32 FO = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO = 32 FO = 384 3.9 4.5 4.3 4.9 4.9 5.6 5.7 6.6 8.0 9.2 ns ns tP Minimum Period FO = 32 FO = 384 7.0 7.7 7.8 8.6 8.4 9.3 9.7 10.7 16.2 17.8 ns ns fMAX Maximum Frequency FO = 32 FO = 384 142 129 129 117 119 108 103 MHz MHz Table 35  A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-61 TTL Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad), 64 Clock Loading tACO Array Clock-to-Out (Pad-to-Pad), CMOS Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad), 64 Clock Loading tACO Array Clock-to-Out (Pad-to-Pad), Table 35  A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-62 v6.0 Table 36  A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Combinatorial Functions1 Logic Module Predicted Routing Delays2 Logic Module Sequential Timing3, 4 tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width ns Input Module Propagation Delays t Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-63 Input Module Predicted Routing Delays2 Global Clock Network t CKH Input LOW to HIGH FO=32 FO=486 2.6 2.9 2.9 3.2 3.3 3.6 3.9 4.3 5.4 5.9 ns ns tCKL Input HIGH to LOW FO=32 FO=486 3.7 4.3 4.1 4.7 4.6 5.4 5.4 6.3 7.6 8.8 ns ns tPWH Minimum Pulse Width HIGH FO=32 FO=486 2.2 2.4 2.4 2.6 2.7 3.0 3.2 3.5 4.5 4.9 ns ns tPWL Minimum Pulse Width LOW FO=32 FO=486 2.2 2.4 2.4 2.6 2.7 3.0 3.2 3.5 4.5 4.9 ns ns tCKSW Maximum Skew FO=32 FO=486 0.5 0.5 0.6 0.6 0.7 0.7 0.8 0.8 1.1 1.1 ns ns tSUEXT Input Latch External Set-Up FO=32 FO=486 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO=32 FO=486 2.8 3.3 3.1 3.7 3.5 4.2 4.1 4.9 5.7 6.9 ns ns tP Minimum Period (1/fMAX) FO=32 FO=486 4.7 5.1 5.2 5.7 5.7 6.2 6.5 7.1 10.9 11.9 ns ns Table 36  A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-64 v6.0 TTL Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O tACO Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Table 36  A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-65 CMOS Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad) 32 I/O tACO Array Latch Clock-to-Out (Pad- to-Pad) 32 I/O Table 36  A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 4.75V, T J = 70°C) ‘–3’ Speed ‘–2’Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-66 v6.0 Table 37  A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Combinatorial Functions1 Logic Module Predicted Routing Delays2 Logic Module Sequential Timing3, 4 tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width ns Input Module Propagation Delays t tINGO Input Latch Gate-to- Output Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-67 Input Module Predicted Routing Delays2 Global Clock Network t CKH Input LOW to HIGH FO=32 FO=486 4.4 4.8 4.8 5.3 5.5 6.0 6.5 7.1 9.1 10.0 ns ns tCKL Input HIGH to LOW FO=32 FO=486 5.1 6.0 5.7 6.6 6.4 7.5 7.6 8.8 10.6 12.4 ns ns tPWH Minimum Pulse Width HIGH FO=32 FO=486 3.0 3.3 3.3 3.7 3.8 4.2 4.5 4.9 6.3 6.9 ns ns tPWL Minimum Pulse Width LOW FO=32 FO=486 3.0 3.3 3.4 3.7 3.8 4.2 4.5 4.9 6.3 6.9 ns ns tCKSW Maximum Skew FO=32 FO=486 0.8 0.8 0.8 0.8 1.0 1.0 1.1 1.1 1.6 1.6 ns ns tSUEXT Input Latch External Set-Up FO=32 FO=486 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns TTL Output Module Timing5 Table 37  A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-68 v6.0 TTL Output Module Timing5 (Continued) tLCO I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O tACO Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O CMOS Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O tACO Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O tHEXT Input Latch External Hold FO=32 FO=486 3.9 4.6 4.3 5.2 4.9 5.8 5.7 6.9 8.1 9.6 ns ns tP Minimum Period (1/fMAX) FO=32 FO=486 7.8 8.6 8.7 9.5 9.5 10.4 10.8 11.9 18.2 19.9 ns ns Table 37  A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-69 Table 38  A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75V , TJ = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Combinatorial Functions1 Logic Module Predicted Routing Delays2 Logic Module Sequential Timing3, 4 tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width ns Synchronous SRAM Operations t Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-70 v6.0 Synchronous SRAM Operations (Continued) Asynchronous SRAM Operations t tRENSUA Read Enable Set-Up to Address Valid Input Module Propagation Delays t Table 38  A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75V , TJ = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-71 Input Module Predicted Routing Delays2 Global Clock Network tCKH Input LOW to HIGH FO=32 FO=635 2.7 3.0 3.0 3.3 3.4 3.8 4.0 4.4 5.6 6.2 ns ns tCKL Input HIGH to LOW FO=32 FO=635 3.8 4.9 4.2 5.4 4.8 6.1 5.6 7.2 7.8 10.1 ns ns tPWH Minimum Pulse Width HIGH FO=32 FO=635 1.8 2.0 2.0 2.2 2.2 2.5 2.6 2.9 3.6 4.1 ns ns tPWL Minimum Pulse Width LOW FO=32 FO=635 1.8 2.0 2.0 2.2 2.2 2.5 2.6 2.9 3.6 4.1 ns ns tCKSW Maximum Skew FO=32 FO=635 0.8 0.8 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 ns ns tSUEXT Input Latch External Set-Up FO=32 FO=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO=32 FO=635 2.8 3.3 3.2 3.7 3.6 4.2 4.2 4.9 5.9 6.9 ns ns tP Minimum Period (1/fMAX) FO=32 FO=635 5.5 6.0 6.1 6.6 6.6 7.2 7.6 8.3 12.7 13.8 ns ns fMAX Maximum Datapath Frequency FO=32 FO=635 180 166 164 151 151 139 131 121 MHz MHz TTL Output Module Timing5 Table 38  A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75V , TJ = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-72 v6.0 TTL Output Module Timing5 (Continued) tLCO I/O Latch Clock-to-Out (Pad-to- Pad) 32 I/O tACO Array Latch Clock-to-Out (Pad- to-Pad) 32 I/O CMOS Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad) 32 I/O tACO Array Latch Clock-to-Out (Pad- to-Pad) 32 I/O Table 38  A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75V , TJ = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-73 Table 39  A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Logic Module Combinatorial Functions1 Logic Module Predicted Routing Delays2 Logic Module Sequential Timing3, 4 tWCLKA Flip-Flop (Latch) Clock Active Pulse Width tWASYN Flip-Flop (Latch) Asynchronous Pulse Width Synchronous SRAM Operations Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-74 v6.0 Synchronous SRAM Operations (Continued) Asynchronous SRAM Operations t tRENSUA Read Enable Set-Up to Address Valid Input Module Propagation Delays t tINGO Input Latch Gate-to- Output Table 39  A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-75 Input Module Predicted Routing Delays2 Global Clock Network tCKH Input LOW to HIGH FO=32 FO=635 4.6 5.0 5.1 5.6 5.7 6.3 6.7 7.4 9.3 10.3 ns ns tCKL Input HIGH to LOW FO=32 FO=635 5.3 6.8 5.9 7.6 6.7 8.6 7.8 10.1 11.0 14.1 ns ns tPWH Minimum Pulse Width HIGH FO=32 FO=635 2.5 2.8 2.7 3.1 3.1 3.5 3.6 4.1 5.1 5.7 ns ns tPWL Minimum Pulse Width LOW FO=32 FO=635 2.5 2.8 2.7 3.1 3.1 3.5 3.6 4.1 5.1 5.7 ns ns tCKSW Maximum Skew FO=32 FO=635 1.0 1.0 1.2 1.2 1.3 1.3 1.5 1.5 2.2 2.2 ns ns tSUEXT Input Latch External Set-Up FO=32 FO=635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO=32 FO=635 4.0 4.6 4.4 5.2 5.0 5.9 5.9 6.9 8.2 9.6 ns ns tP Minimum Period (1/fMAX) FO=32 FO=635 9.2 9.9 10.2 11.0 11.1 12.0 12.7 13.8 21.2 23.0 ns ns fMAX Maximum Datapath Frequency FO=32 FO=635 108 100 MHz MHz TTL Output Module Timing5 Table 39  A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families 1-76 v6.0 TTL Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad) 32 I/O tACO Array Latch Clock-to-Out (Pad- to-Pad) 32 I/O CMOS Output Module Timing5 tLCO I/O Latch Clock-to-Out (Pad-to- Pad) 32 I/O Table 39  A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued) (Worst-Case Commercial Conditions, VCCA = 3.0V, T J = 70°C) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed ‘–F’ Speed Notes: 1. For dual-module macros, use t PD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for th e Input Buffer Latch are defined with respect to the PAD and the D input. External se tup/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading.

40MX and 42MX FPGA Families v6.0 1-77 Pin Descriptions CLK/A/B, I/O Global Clock Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK, I/O Diagnostic Clock Clock input for diagnostic probe and device programming. DCLK is acti ve when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground Input LOW supply voltage. I/O Input/Output Input, output, tristate or bi-d irectional buffer. Input and output levels are compatib le with standard TTL and CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 40. In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all dual- purpose pins when configured as I/Os as well. LP Low Power Mode Controls the low power mode of all 42MX devices. The device is placed in the low power mode by connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW. The device enters the low power mode 800ns after the LP pin is driven to a logic HIGH. It will resume normal operation in 200µs after the LP pin is driven to a logic LOW. MODE Mode Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to provide verification capability. The MODE pin should be terminated to GND through a 10k Ω resistor so that the MODE pin can be pulled HIGH when required. NC No Connection This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. PRA, I/O PRB, I/O Probe A/B The Probe pin is used to ou tput data from any user- defined design node within the device. Each diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a user- defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. The Probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. QCLKA/B/C/D, I/O Quadrant Clock Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can function as user I/Os. SDI, I/O Serial Data Input Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO, I/O Serial Data Output Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO is available for 42MX devices only. When Silicon Explorer II is be ing used, SDO will act as an output while the "checksum" command is run. It will return to user I/O when "checksum" is complete. TCK, I/O Test Clock Clock signal to shift the Boundary Scan Test (BST) data into the device. This pi n functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices. TDI, I/O Test Data In Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin functions as an I/O when "Reserve JTAG " is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices. TDO, I/O Test Data Out Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36 devices. Table 40  Configuration of Unused I/Os Device Configuration A40MX02, A40MX04 Pulled LOW A42MX09, A42MX16 Pulled LOW A42MX24, A42MX36 Tristated

40MX and 42MX FPGA Families 1-78 v6.0 TMS, I/O Test Mode Select The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode when the TMS pin is set LOW, the TCK, TDI and TDO pins are boundary scan pins. Once the boundary scan pins are in test mode, they will rema in in that mode until the internal boundary scan stat e machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG specification recommends a 10k Ω pull-up resistor on the pin. BST pins are only available in A42MX24 and A42MX36 devices. VCC Supply Voltage Input supply voltage for 40MX devices VCCA Supply Voltage Supply voltage for array in 42MX devices VCCI Supply Voltage Supply voltage for I/Os in 42MX devices WD, I/O Wide Decode Output When a wide decode module is used in a 42MX device this pin can be used as a dedicated output from the wide decode module. This direct connection eliminates additional interconnect dela ys associated with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type to the output of the wide decode macro and place this output on one of the reserved WD pins.

40MX and 42MX FPGA Families v6.0 2-1 Package Pin Assignments 44-Pin PLCC Figure 2-1  44-Pin PLCC 441 44-Pin PLCC 44-pin PLCC Pin Number A40MX02 Function A40MX04 Function 1I / O I / O 2I / O I / O CC VCC 4I / O I / O 5I / O I / O 6I / O I / O 7I / O I / O 8I / O I / O 9I / O I / O

10 GND GND

11 I/O I/O

12 I/O I/O

13 I/O I/O

15 I/O I/O

16 V CC VCC

17 I/O I/O

18 I/O I/O

19 I/O I/O

20 I/O I/O

21 GND GND

22 I/O I/O

23 I/O I/O

24 I/O I/O

26 I/O I/O

27 I/O I/O

28 I/O I/O

29 I/O I/O

30 I/O I/O

31 I/O I/O

32 GND GND

33 CLK, I/O CLK, I/O

34 MODE MODE

36 SDI, I/O SDI, I/O

37 DCLK, I/O DCLK, I/O

38 PRA, I/O PRA, I/O

39 PRB, I/O PRB, I/O

40 I/O I/O

41 I/O I/O

42 I/O I/O

43 GND GND

44 I/O I/O

Pin Number A40MX02 Function A40MX04 Function

40MX and 42MX FPGA Families 2-2 v6.0 68-Pin PLCC Figure 2-2  68-Pin PLCC 1 68 68-Pin PLCC 44-pin PLCC Pin Number A40MX02 Function A40MX04 Function 1I / O I / O 2I / O I / O 3I / O I / O 4V CC VCC 5I / O I / O 6I / O I / O 7I / O I / O 8I / O I / O 9I / O I / O

10 I/O I/O

14 GND GND

15 GND GND

16 I/O I/O

25 V CC VCC

33 I/O I/O

34 I/O I/O

35 I/O I/O

36 I/O I/O

37 I/O I/O

39 I/O I/O

43 I/O I/O

45 I/O I/O

46 I/O I/O

47 I/O I/O

48 I/O I/O

49 GND GND

50 I/O I/O

51 I/O I/O

52 CLK, I/O CLK, I/O

53 I/O I/O

54 MODE MODE

56 SDI, I/O SDI, I/O

57 DCLK, I/O DCLK, I/O

58 PRA, I/O PRA, I/O

59 PRB, I/O PRB, I/O

60 I/O I/O

61 I/O I/O

62 I/O I/O

63 I/O I/O

64 I/O I/O

65 I/O I/O

66 GND GND

67 I/O I/O

68 I/O I/O

40MX and 42MX FPGA Families v6.0 2-3 84-Pin PLCC Figure 2-3  84-Pin PLCC 18 4 84-Pin PLCC

40MX and 42MX FPGA Families 2-4 v6.0 84-Pin PLCC Pin Number A40MX04 Function A42MX09 Function A42MX16 Function A42MX24 Function 1I / O I / O I / O I / O

2 I/O CLKB, I/O CLKB, I/O CLKB, I/O

4V CC PRB, I/O PRB, I/O PRB, I/O

5 I/O I/O I/O WD, I/O

6 I/O GND GND GND

8 I/O I/O I/O WD, I/O

9 I/O I/O I/O WD, I/O

10 I/O DCLK, I/O DCLK, I/O DCLK, I/O

11 I/O I/O I/O I/O

12 NC MODE MODE MODE

13 I/O I/O I/O I/O

14 I/O I/O I/O I/O

15 I/O I/O I/O I/O

16 I/O I/O I/O I/O

17 I/O I/O I/O I/O

18 GND I/O I/O I/O

19 GND I/O I/O I/O

20 I/O I/O I/O I/O

21 I/O I/O I/O I/O

22 I/O V

23 I/O V CCI VCCA VCCA

24 I/O I/O I/O I/O

26 V CC I/O I/O I/O

27 I/O I/O I/O I/O

28 I/O GND GND GND

29 I/O I/O I/O I/O

30 I/O I/O I/O I/O

31 I/O I/O I/O I/O

32 I/O I/O I/O I/O

34 I/O I/O I/O TMS, I/O

35 I/O I/O I/O TDI, I/O

36 I/O I/O I/O WD, I/O

37 I/O I/O I/O I/O

38 I/O I/O I/O WD, I/O

39 I/O I/O I/O WD, I/O

40 GND I/O I/O I/O

41 I/O I/O I/O I/O

42 I/O I/O I/O I/O

43 I/O V

44 I/O I/O I/O WD, I/O

45 I/O I/O I/O WD, I/O

CC I/O I/O WD, I/O

47 I/O I/O I/O WD, I/O

48 I/O I/O I/O I/O

49 I/O GND GND GND

50 I/O I/O I/O WD, I/O

51 I/O I/O I/O WD, I/O

52 I/O SDO, I/O SDO, I/O SDO, TDO, I/O

53 I/O I/O I/O I/O

54 I/O I/O I/O I/O

55 I/O I/O I/O I/O

56 I/O I/O I/O I/O

57 I/O I/O I/O I/O

58 I/O I/O I/O I/O

59 I/O I/O I/O I/O

60 GND I/O I/O I/O

61 GND I/O I/O I/O

62 I/O I/O I/O TCK, I/O

63 I/O LP LP LP

64 CLK, I/O V

65 I/O V CCI VCCI VCCI

66 MODE I/O I/O I/O

67 V CC I/O I/O I/O

68 V CC I/O I/O I/O

69 I/O I/O I/O I/O

70 I/O GND GND GND

40MX and 42MX FPGA Families v6.0 2-5

71 I/O I/O I/O I/O

72 SDI, I/O I/O I/O I/O

73 DCLK, I/O I/O I/O I/O

74 PRA, I/O I/O I/O I/O

75 PRB, I/O I/O I/O I/O

76 I/O SDI, I/O SDI, I/O SDI, I/O

77 I/O I/O I/O I/O

78 I/O I/O I/O WD, I/O

79 I/O I/O I/O WD, I/O

80 I/O I/O I/O WD, I/O

81 I/O PRA, I/O PRA, I/O PRA, I/O

82 GND I/O I/O I/O

83 I/O CLKA, I/O CLKA, I/O CLKA, I/O

84 I/O V

40MX and 42MX FPGA Families 2-6 v6.0 100-Pin PQFP Package Figure 2-4  100-Pin PQFP Package (Top View) 1100 100-Pin PQFP

40MX and 42MX FPGA Families v6.0 2-7 100-Pin PQFP Pin Number A40MX02 Function A40MX04 Function A42MX09 Function A42MX16 Function 1N C N C I / O I / O

2 NC NC DCLK, I/O DCLK, I/O

4 NC NC MODE MODE

6 PRB, I/O PRB, I/O I/O I/O

7 I/O I/O I/O I/O

8 I/O I/O I/O I/O

10 I/O I/O I/O I/O

12 I/O I/O I/O I/O

13 GND GND I/O I/O

16 I/O I/O V

17 I/O I/O V CCI VCCA

18 I/O I/O I/O I/O

22 I/O I/O GND GND

23 I/O I/O I/O I/O

25 I/O I/O I/O I/O

26 I/O I/O I/O I/O

27 NC NC I/O I/O

28 NC NC I/O I/O

29 NC NC I/O I/O

30 NC NC I/O I/O

31 NC I/O I/O I/O

32 NC I/O I/O I/O

33 NC I/O I/O I/O

34 I/O I/O GND GND

35 I/O I/O I/O I/O

36 GND GND I/O I/O

37 GND GND I/O I/O

38 I/O I/O I/O I/O

39 I/O I/O I/O I/O

40 I/O I/O V

44 V CC VCC I/O I/O

45 I/O I/O I/O I/O

46 I/O I/O GND GND

47 I/O I/O I/O I/O

48 NC I/O I/O I/O

49 NC I/O I/O I/O

50 NC I/O I/O I/O

51 NC NC I/O I/O

52 NC NC SDO, I/O SDO, I/O

53 NC NC I/O I/O

54 NC NC I/O I/O

55 NC NC I/O I/O

57 I/O I/O GND GND

60 I/O I/O I/O I/O

61 I/O I/O I/O I/O

62 I/O I/O I/O I/O

63 GND GND I/O I/O

64 I/O I/O LP LP

65 I/O I/O V

66 I/O I/O V CCI VCCI

67 I/O I/O V CCA VCCA

68 I/O I/O I/O I/O

69 V CC VCC I/O I/O

70 I/O I/O I/O I/O

40MX and 42MX FPGA Families 2-8 v6.0

72 I/O I/O GND GND

73 I/O I/O I/O I/O

74 I/O I/O I/O I/O

75 I/O I/O I/O I/O

76 I/O I/O I/O I/O

77 NC NC I/O I/O

78 NC NC I/O I/O

79 NC NC SDI, I/O SDI, I/O

80 NC I/O I/O I/O

81 NC I/O I/O I/O

82 NC I/O I/O I/O

83 I/O I/O I/O I/O

84 I/O I/O GND GND

85 I/O I/O I/O I/O

86 GND GND I/O I/O

87 GND GND PRA, I/O PRA, I/O

88 I/O I/O I/O I/O

89 I/O I/O CLKA, I/O CLKA, I/O

90 CLK, I/O CLK, I/O V

91 I/O I/O I/O I/O

92 MODE MODE CLKB, I/O CLKB, I/O

94 V CC VCC PRB, I/O PRB, I/O

95 NC I/O I/O I/O

96 NC I/O GND GND

97 NC I/O I/O I/O

98 SDI, I/O SDI, I/O I/O I/O

99 DCLK, I/O DCLK, I/O I/O I/O

100 PRA, I/O PRA, I/O I/O I/O

40MX and 42MX FPGA Families v6.0 2-9 160-Pin PQFP Package Figure 2-5  160-Pin PQFP Package (Top View) 160 160-Pin PQFP

40MX and 42MX FPGA Families 2-10 v6.0 160-Pin PQFP Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

1 I/O I/O I/O

2 DCLK, I/O DCLK, I/O DCLK, I/O

4I / O I / O W D , I / O 5I / O I / O W D , I / O 6N C V CCI VCCI

7 I/O I/O I/O

8 I/O I/O I/O

9 I/O I/O I/O

10 NC I/O I/O

11 GND GND GND

12 NC I/O I/O

13 I/O I/O WD, I/O

14 I/O I/O WD, I/O

15 I/O I/O I/O

16 PRB, I/O PRB, I/O PRB, I/O

17 I/O I/O I/O

18 CLKB, I/O CLKB, I/O CLKB, I/O

19 I/O I/O I/O

21 CLKA, I/O CLKA, I/O CLKA, I/O

22 I/O I/O I/O

23 PRA, I/O PRA, I/O PRA, I/O

24 NC I/O WD, I/O

25 I/O I/O WD, I/O

26 I/O I/O I/O

27 I/O I/O I/O

28 NC I/O I/O

29 I/O I/O WD, I/O

30 GND GND GND

31 NC I/O WD, I/O

32 I/O I/O I/O

33 I/O I/O I/O

34 I/O I/O I/O

35 NC V

36 I/O I/O WD, I/O

37 I/O I/O WD, I/O

38 SDI, I/O SDI, I/O SDI, I/O

39 I/O I/O I/O

40 GND GND GND

41 I/O I/O I/O

42 I/O I/O I/O

43 I/O I/O I/O

44 GND GND GND

45 I/O I/O I/O

46 I/O I/O I/O

47 I/O I/O I/O

48 I/O I/O I/O

49 GND GND GND

50 I/O I/O I/O

51 I/O I/O I/O

52 NC I/O I/O

53 I/O I/O I/O

54 NC V

55 I/O I/O I/O

56 I/O I/O I/O

57 V CCA VCCA VCCA

58 V CCI VCCI VCCI

59 GND GND GND

61 LP LP LP

62 I/O I/O TCK, I/O

63 I/O I/O I/O

64 GND GND GND

65 I/O I/O I/O

66 I/O I/O I/O

67 I/O I/O I/O

68 I/O I/O I/O

69 GND GND GND

70 NC I/O I/O

40MX and 42MX FPGA Families v6.0 2-11

71 I/O I/O I/O

72 I/O I/O I/O

73 I/O I/O I/O

74 I/O I/O I/O

75 NC I/O I/O

76 I/O I/O I/O

77 NC I/O I/O

78 I/O I/O I/O

79 NC I/O I/O

80 GND GND GND

81 I/O I/O I/O

82 SDO, I/O SDO, I/O SDO, TDO, I/O

83 I/O I/O WD, I/O

84 I/O I/O WD, I/O

85 I/O I/O I/O

86 NC V

87 I/O I/O I/O

88 I/O I/O WD, I/O

89 GND GND GND

90 NC I/O I/O

91 I/O I/O I/O

92 I/O I/O I/O

93 I/O I/O I/O

94 I/O I/O I/O

95 I/O I/O I/O

96 I/O I/O WD, I/O

97 I/O I/O I/O

99 GND GND GND

100 NC I/O I/O

101 I/O I/O I/O

102 I/O I/O I/O

103 NC I/O I/O

104 I/O I/O I/O

105 I/O I/O I/O

106 I/O I/O WD, I/O

107 I/O I/O WD, I/O

108 I/O I/O I/O

109 GND GND GND

110 NC I/O I/O

111 I/O I/O WD, I/O

112 I/O I/O WD, I/O

113 I/O I/O I/O

114 NC V

115 I/O I/O WD, I/O

116 NC I/O WD, I/O

117 I/O I/O I/O

118 I/O I/O TDI, I/O

119 I/O I/O TMS, I/O

120 GND GND GND

121 I/O I/O I/O

122 I/O I/O I/O

123 I/O I/O I/O

124 NC I/O I/O

125 GND GND GND

126 I/O I/O I/O

127 I/O I/O I/O

128 I/O I/O I/O

129 NC I/O I/O

130 GND GND GND

131 I/O I/O I/O

132 I/O I/O I/O

133 I/O I/O I/O

134 I/O I/O I/O

135 NC V

136 I/O I/O I/O

137 I/O I/O I/O

138 NC V

139 V CCI VCCI VCCI

140 GND GND GND

40MX and 42MX FPGA Families 2-12 v6.0

141 NC I/O I/O

142 I/O I/O I/O

143 I/O I/O I/O

144 I/O I/O I/O

145 GND GND GND

146 NC I/O I/O

147 I/O I/O I/O

148 I/O I/O I/O

149 I/O I/O I/O

150 NC V

151 NC I/O I/O

152 NC I/O I/O

153 NC I/O I/O

154 NC I/O I/O

155 GND GND GND

156 I/O I/O I/O

157 I/O I/O I/O

158 I/O I/O I/O

159 MODE MODE MODE

160 GND GND GND

40MX and 42MX FPGA Families v6.0 2-13 208-Pin PQFP Package Figure 2-6  208-Pin PQFP Package (Top View) 208-Pin PQFP 208

40MX and 42MX FPGA Families 2-14 v6.0 208-Pin PQFP Pin Number A42MX16 Function A42MX24 Function A42MX36 Function

1 GND GND GND

3 MODE MODE MODE

4 I/O I/O I/O

5 I/O I/O I/O

6 I/O I/O I/O

11 NC I/O I/O

12 I/O I/O I/O

13 I/O I/O I/O

14 I/O I/O I/O

16 NC I/O I/O

18 I/O I/O I/O

20 I/O I/O I/O

21 I/O I/O I/O

22 GND GND GND

23 I/O I/O I/O

24 I/O I/O I/O

25 I/O I/O I/O

27 GND GND GND

29 V CCA VCCA VCCA

30 I/O I/O I/O

31 I/O I/O I/O

35 I/O I/O I/O

36 I/O I/O I/O

37 I/O I/O I/O

38 I/O I/O I/O

40 I/O I/O I/O

41 NC I/O I/O

42 NC I/O I/O

43 NC I/O I/O

44 I/O I/O I/O

49 I/O I/O I/O

50 NC I/O I/O

51 NC I/O I/O

52 GND GND GND

53 GND GND GND

54 I/O TMS, I/O TMS, I/O

55 I/O TDI, I/O TDI, I/O

57 I/O WD, I/O WD, I/O

58 I/O WD, I/O WD, I/O

59 I/O I/O I/O

61 NC I/O I/O

62 NC I/O I/O

64 I/O I/O I/O

65 I/O I/O QCLKA, I/O

66 I/O WD, I/O WD, I/O

67 NC WD, I/O WD, I/O

68 NC I/O I/O

69 I/O I/O I/O

70 I/O WD, I/O WD, I/O

40MX and 42MX FPGA Families v6.0 2-15

71 I/O WD, I/O WD, I/O

75 I/O I/O I/O

77 I/O I/O I/O

78 GND GND GND

80 NC V CCI VCCI

82 I/O I/O I/O

83 I/O I/O I/O

84 I/O I/O I/O

85 I/O WD, I/O WD, I/O

86 I/O WD, I/O WD, I/O

88 I/O I/O I/O

89 NC I/O I/O

91 I/O I/O QCLKB, I/O

93 I/O WD, I/O WD, I/O

94 I/O WD, I/O WD, I/O

95 NC I/O I/O

96 NC I/O I/O

97 NC I/O I/O

99 I/O I/O I/O

100 I/O WD, I/O WD, I/O

101 I/O WD, I/O WD, I/O

103 SDO, I/O SDO, TDO, I/O SDO, TDO, I/O

105 GND GND GND

106 NC V CCA VCCA

107 I/O I/O I/O

109 I/O I/O I/O

110 I/O I/O I/O

111 I/O I/O I/O

112 NC I/O I/O

113 NC I/O I/O

114 NC I/O I/O

115 NC I/O I/O

116 I/O I/O I/O

118 I/O I/O I/O

119 I/O I/O I/O

120 I/O I/O I/O

124 I/O I/O I/O

125 I/O I/O I/O

126 GND GND GND

128 I/O TCK, I/O TCK, I/O

131 GND GND GND

132 V CCI VCCI VCCI

133 V CCA VCCA VCCA

135 I/O I/O I/O

138 I/O I/O I/O

139 I/O I/O I/O

140 I/O I/O I/O

40MX and 42MX FPGA Families 2-16 v6.0

145 I/O I/O I/O

147 NC I/O I/O

148 NC I/O I/O

149 NC I/O I/O

150 GND GND GND

151 I/O I/O I/O

152 I/O I/O I/O

153 I/O I/O I/O

154 I/O I/O I/O

155 I/O I/O I/O

157 GND GND GND

159 SDI, I/O SDI, I/O SDI, I/O

160 I/O I/O I/O

161 I/O WD, I/O WD, I/O

162 I/O WD, I/O WD, I/O

163 I/O I/O I/O

165 NC I/O I/O

166 NC I/O I/O

167 I/O I/O I/O

168 I/O WD, I/O WD, I/O

169 I/O WD, I/O WD, I/O

170 I/O I/O I/O

171 NC I/O QCLKD, I/O

172 I/O I/O I/O

173 I/O I/O I/O

174 I/O I/O I/O

175 I/O I/O I/O

176 I/O WD, I/O WD, I/O

177 I/O WD, I/O WD, I/O

178 PRA, I/O PRA, I/O PRA, I/O

179 I/O I/O I/O

180 CLKA, I/O CLKA, I/O CLKA, I/O

181 NC I/O I/O

182 NC V

183 V CCA VCCA VCCA

184 GND GND GND

185 I/O I/O I/O

186 CLKB, I/O CLKB, I/O CLKB, I/O

187 I/O I/O I/O

188 PRB, I/O PRB, I/O PRB, I/O

189 I/O I/O I/O

190 I/O WD, I/O WD, I/O

191 I/O WD, I/O WD, I/O

192 I/O I/O I/O

193 NC I/O I/O

194 NC WD, I/O WD, I/O

195 NC WD, I/O WD, I/O

196 I/O I/O QCLKC, I/O

197 NC I/O I/O

198 I/O I/O I/O

199 I/O I/O I/O

200 I/O I/O I/O

201 NC I/O I/O

203 I/O WD, I/O WD, I/O

204 I/O WD, I/O WD, I/O

205 I/O I/O I/O

206 I/O I/O I/O

207 DCLK, I/O DCLK, I/O DCLK, I/O

208 I/O I/O I/O

40MX and 42MX FPGA Families v6.0 2-17 240-Pin PQFP Package Figure 2-7  240-Pin PQFP Package (Top View) 240-Pin PQFP 240

40MX and 42MX FPGA Families 2-18 v6.0 240-Pin PQFP Pin Number A42MX36 Function 1I / O

2 DCLK, I/O

6W D , I / O 7W D , I / O CCI 9I / O

10 I/O

11 I/O

12 I/O

13 I/O

14 I/O

15 QCLKC, I/O

16 I/O

17 WD, I/O

18 WD, I/O

19 I/O

20 I/O

21 WD, I/O

22 WD, I/O

23 I/O

24 PRB, I/O

25 I/O

26 CLKB, I/O

27 I/O

28 GND

30 V CCI

31 I/O

32 CLKA, I/O

33 I/O

34 PRA, I/O

35 I/O

36 I/O

37 WD, I/O

38 WD, I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

44 I/O

45 QCLKD, I/O

46 I/O

47 WD, I/O

48 WD, I/O

49 I/O

50 I/O

51 I/O

53 I/O

54 WD, I/O

55 WD, I/O

56 I/O

57 SDI, I/O

58 I/O

60 GND

61 GND

62 I/O

63 I/O

64 I/O

65 I/O

66 I/O

67 I/O

68 I/O

69 I/O

70 I/O

71 V CCI

72 I/O

73 I/O

74 I/O

75 I/O

76 I/O

77 I/O

78 I/O

79 I/O

80 I/O

81 I/O

82 I/O

83 I/O

84 I/O

86 I/O

87 I/O

88 V CCA

89 V CCI

90 V CCA

92 TCK, I/O

93 I/O

94 GND

95 I/O

96 I/O

97 I/O

98 I/O

99 I/O

100 I/O

101 I/O

102 I/O

103 I/O

104 I/O

105 I/O

106 I/O

107 I/O

108 V CCI

109 I/O

110 I/O

111 I/O

112 I/O

113 I/O

114 I/O

115 I/O

116 I/O

117 I/O

119 GND

120 GND

121 GND

122 I/O

123 SDO, TDO, I/O

124 I/O

125 WD, I/O

126 WD, I/O

127 I/O

129 I/O

130 I/O

131 I/O

132 WD, I/O

133 WD, I/O

134 I/O

135 QCLKB, I/O

136 I/O

137 I/O

138 I/O

139 I/O

140 I/O

40MX and 42MX FPGA Families v6.0 2-19

141 I/O

142 WD, I/O

143 WD, I/O

144 I/O

145 I/O

146 I/O

147 I/O

148 I/O

149 I/O

151 V CCA

152 GND

153 I/O

154 I/O

155 I/O

156 I/O

157 I/O

158 I/O

159 WD, I/O

160 WD, I/O

161 I/O

162 I/O

163 WD, I/O

164 WD, I/O

165 I/O

166 QCLKA, I/O

167 I/O

168 I/O

169 I/O

170 I/O

171 I/O

173 I/O

174 WD, I/O

175 WD, I/O

176 I/O

177 I/O

178 TDI, I/O

179 TMS, I/O

180 GND

182 GND

183 I/O

184 I/O

185 I/O

186 I/O

187 I/O

188 I/O

189 I/O

190 I/O

191 I/O

193 I/O

194 I/O

195 I/O

196 I/O

197 I/O

198 I/O

199 I/O

200 I/O

201 I/O

202 I/O

203 I/O

204 I/O

205 I/O

207 I/O

208 I/O

210 V CCI

211 I/O

212 I/O

213 I/O

214 I/O

215 I/O

216 I/O

217 I/O

218 I/O

220 I/O

221 I/O

222 I/O

223 I/O

224 I/O

225 I/O

226 I/O

228 I/O

229 I/O

230 I/O

231 I/O

232 I/O

233 I/O

234 I/O

235 I/O

236 I/O

237 GND

238 MODE

240 GND

40MX and 42MX FPGA Families 2-20 v6.0 80-Pin VQFP Figure 2-8  80-Pin VQFP 801 80-Pin VQFP

40MX and 42MX FPGA Families v6.0 2-21 80-Pin VQFP Pin Number A40MX02 Function A40MX04 Function 1I / O I / O 2N C I / O 3N C I / O 4N C I / O 5I / O I / O 6I / O I / O 7G N D G N D 8I / O I / O 9I / O I / O

14 I/O I/O

17 NC I/O

18 NC I/O

19 NC I/O

21 I/O I/O

25 I/O I/O

27 GND GND

32 I/O I/O

38 I/O I/O

41 NC I/O

42 NC I/O

43 NC I/O

47 GND GND

49 I/O I/O

50 CLK, I/O CLK, I/O

52 MODE MODE

54 NC I/O

55 NC I/O

56 NC I/O

57 SDI, I/O SDI, I/O

58 DCLK, I/O DCLK, I/O

59 PRA, I/O PRA, I/O

60 NC NC

61 PRB, I/O PRB, I/O

66 I/O I/O

68 GND GND

69 I/O I/O

70 I/O I/O

71 I/O I/O

72 I/O I/O

73 I/O I/O

75 I/O I/O

76 I/O I/O

77 I/O I/O

78 I/O I/O

79 I/O I/O

80 I/O I/O

40MX and 42MX FPGA Families 2-22 v6.0 100-Pin VQFP Package Figure 2-9  100-Pin VQFP Package (Top View) 100-Pin VQFP 100

40MX and 42MX FPGA Families v6.0 2-23 100-Pin VQFP Package Pin Number A42MX09 Function A42MX16 Function 1I / O I / O

2 MODE MODE

15 V CCI VCCI

20 GND GND

38 V CCA VCCA

44 GND GND

50 SDO, I/O SDO, I/O

52 I/O I/O

54 I/O I/O

55 GND GND

56 I/O I/O

57 I/O I/O

58 I/O I/O

59 I/O I/O

62 LP LP

64 V CCI VCCI

65 V CCA VCCA

70 GND GND

74 I/O I/O

77 SDI, I/O SDI, I/O

81 I/O I/O

82 GND GND

83 I/O I/O

84 I/O I/O

85 PRA, I/O PRA, I/O

86 I/O I/O

87 CLKA, I/O CLKA, I/O

89 I/O I/O

90 CLKB, I/O CLKB, I/O

91 I/O I/O

92 PRB, I/O PRB, I/O

93 I/O I/O

94 GND GND

95 I/O I/O

96 I/O I/O

97 I/O I/O

98 I/O I/O

99 I/O I/O

100 DCLK, I/O DCLK, I/O

40MX and 42MX FPGA Families 2-24 v6.0 176-Pin TQFP Package Figure 2-10  176-Pin TQFP Package (Top View) 176-Pin TQFP 176

40MX and 42MX FPGA Families v6.0 2-25 176-Pin TQFP Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

2 MODE MODE MODE

3 I/O I/O I/O

13 NC V

16 I/O I/O I/O

18 GND GND GND

19 NC I/O I/O

20 NC I/O I/O

22 NC I/O I/O

23 GND GND GND

24 NC V

25 V CCA VCCA VCCA

26 NC I/O I/O

27 NC I/O I/O

29 NC I/O I/O

33 NC NC I/O

37 NC I/O I/O

38 NC NC I/O

45 GND GND GND

46 I/O I/O TMS, I/O

47 I/O I/O TDI, I/O

49 I/O I/O WD, I/O

50 I/O I/O WD, I/O

52 NC V

54 NC I/O I/O

55 NC I/O WD, I/O

56 I/O I/O WD, I/O

57 NC NC I/O

58 I/O I/O I/O

59 I/O I/O WD, I/O

60 I/O I/O WD, I/O

62 I/O I/O I/O

64 NC I/O I/O

66 NC I/O I/O

67 GND GND GND

69 I/O I/O WD, I/O

70 I/O I/O WD, I/O

40MX and 42MX FPGA Families 2-26 v6.0

74 NC I/O I/O

77 NC NC WD, I/O

78 NC I/O WD, I/O

79 I/O I/O I/O

80 NC I/O I/O

82 NC V

85 I/O I/O WD, I/O

86 NC I/O I/O

87 SDO, I/O SDO, I/O SDO, TDO, I/O

90 I/O I/O I/O

98 I/O I/O I/O

100 I/O I/O I/O

101 NC NC I/O

106 GND GND GND

107 NC I/O I/O

108 NC I/O TCK, I/O

111 GND GND GND

113 V CCA VCCA VCCA

116 NC V

121 NC NC I/O

125 NC I/O I/O

126 NC NC I/O

129 I/O I/O I/O

130 I/O I/O I/O

133 GND GND GND

135 SDI, I/O SDI, I/O SDI, I/O

136 NC I/O I/O

137 I/O I/O WD, I/O

138 I/O I/O WD, I/O

140 NC V

40MX and 42MX FPGA Families v6.0 2-27

141 I/O I/O I/O

143 NC I/O I/O

144 NC I/O WD, I/O

145 NC NC WD, I/O

146 I/O I/O I/O

150 I/O I/O WD, I/O

151 NC I/O WD, I/O

152 PRA, I/O PRA, I/O PRA, I/O

154 CLKA, I/O CLKA, I/O CLKA, I/O

156 GND GND GND

158 CLKB, I/O CLKB, I/O CLKB, I/O

159 I/O I/O I/O

160 PRB, I/O PRB, I/O PRB, I/O

161 NC I/O WD, I/O

162 I/O I/O WD, I/O

164 I/O I/O I/O

165 NC NC WD, I/O

166 NC I/O WD, I/O

168 NC I/O I/O

169 I/O I/O I/O

170 NC V

171 I/O I/O WD, I/O

172 I/O I/O WD, I/O

173 NC I/O I/O

175 DCLK, I/O DCLK, I/O DCLK, I/O

176 I/O I/O I/O

40MX and 42MX FPGA Families 2-28 v6.0 208-Pin CQFP Figure 2-11  208-Pin CQFP (Top View) A42MX36 208-Pin CQFP Pin #1 Index 208207206205204203202201200 164163162161160159158157 53 54 55 56 57 58 59 60 61 97 98 99 100101102103104 105 106 107 108 109 110 111 112 113 149 150 151 153 154 155 156

40MX and 42MX FPGA Families v6.0 2-29 208-Pin CQFP Pin Number A42MX36 Function 1G N D 2V CCA 3M O D E 4I / O 5I / O 6I / O 7I / O 8I / O 9I / O

15 I/O

18 I/O

21 I/O

22 GND

24 I/O

26 I/O

27 GND

29 V CCA

30 I/O

34 I/O

37 I/O

38 I/O

45 I/O

47 I/O

48 I/O

52 GND

53 GND

54 TMS, I/O

55 TDI, I/O

57 WD, I/O

58 WD, I/O

59 I/O

61 I/O

65 QCLKA, I/O

66 WD, I/O

67 WD, I/O

70 WD, I/O

71 WD, I/O

78 GND

80 V CCI

85 WD, I/O

86 WD, I/O

88 I/O

89 I/O

90 I/O

91 QCLKB, I/O

92 I/O

93 WD, I/O

94 WD, I/O

100 WD, I/O

101 WD, I/O

103 TDO, I/O

105 GND

106 V CCA

108 I/O

118 I/O

119 I/O

120 I/O

121 I/O

123 I/O

125 I/O

126 GND

128 TCK, I/O

131 GND

132 V CCI

133 V CCA

135 I/O

40MX and 42MX FPGA Families 2-30 v6.0

142 I/O

143 I/O

150 GND

151 I/O

152 I/O

157 GND

159 SDI, I/O

160 I/O

161 WD, I/O

162 WD, I/O

163 I/O

166 I/O

168 WD, I/O

169 WD, I/O

171 QCLKD, I/O

172 I/O

174 I/O

175 I/O

176 WD, I/O

177 WD, I/O

178 PRA, I/O

179 I/O

180 CLKA, I/O

181 I/O

183 V CCA

184 GND

186 CLKB, I/O

188 PRB, I/O

190 WD, I/O

191 WD, I/O

192 I/O

194 WD, I/O

195 WD, I/O

196 QCLKC, I/O

203 WD, I/O

204 WD, I/O

206 I/O

207 DCLK, I/O

40MX and 42MX FPGA Families v6.0 2-31 256-Pin CQFP Figure 2-12  256-Pin CQFP (Top View) A42MX36 256-Pin CQFP Pin #1 Index 256255254 253252251250249248 200199198197196195194193 65 66 67 68 69 70 71 72 73 121122123124125126127128 129 130 131 132 133 135 136 137 185 186 187 188 189 190 191 192

40MX and 42MX FPGA Families 2-32 v6.0 256-Pin CQFP Pin Number A42MX36 Function 1N C 2G N D 3I / O 4I / O 5I / O 6I / O 7I / O 8I / O 9I / O

10 GND

17 I/O

22 I/O

28 I/O

31 GND

32 V CCA

34 TCK, I/O

36 GND

48 GND

52 I/O

54 I/O

55 I/O

57 I/O

62 GND

67 SDO, TDO, I/O

69 WD, I/O

71 I/O

72 V CCI

76 WD, I/O

77 GND

78 WD, I/O

80 QCLKB, I/O

85 I/O

87 WD, I/O

88 WD, I/O

91 I/O

94 I/O

96 V CCA

97 GND

98 GND

105 WD, I/O

106 WD, I/O

109 WD, I/O

110 WD, I/O

112 QCLKA, I/O

114 GND

121 WD, I/O

122 WD, I/O

126 I/O

127 GND

132 I/O

133 I/O

139 GND

40MX and 42MX FPGA Families v6.0 2-33

150 I/O

158 V CCA

159 V CCI

160 GND

164 I/O

165 GND

178 I/O

182 I/O

188 MODE

190 GND

195 DCLK, I/O

199 WD, I/O

200 WD, I/O

206 GND

209 QCLKC, I/O

210 I/O

211 WD, I/O

212 WD, I/O

215 WD, I/O

216 WD, I/O

218 PRB, I/O

219 I/O

220 CLKB, I/O

222 GND

223 GND

225 V CCI

227 CLKA, I/O

229 PRA, I/O

232 WD, I/O

233 WD, I/O

237 I/O

238 I/O

239 I/O

240 QCLKD, I/O

241 I/O

242 WD, I/O

243 GND

244 WD, I/O

245 I/O

246 I/O

247 I/O

248 V CCI

249 I/O

250 WD, I/O

251 WD, I/O

252 I/O

253 SDI, I/O

254 I/O

255 GND

40MX and 42MX FPGA Families 2-34 v6.0 272-Pin BGA Package Figure 2-13  272-Pin BGA Package (Top View) 272-Pin PBGA 2019181716151413121110987654321 A B C D E F G H J K L M N P R T U V W Y

40MX and 42MX FPGA Families v6.0 2-35 272-Pin PBGA Pin Number A42MX36 Function A1 GND A2 GND A3 I/O A4 WD, I/O A5 I/O A6 I/O A7 WD, I/O A8 WD, I/O A9 I/O A10 I/O A11 CLKA A12 I/O A13 I/O A14 I/O A15 I/O A16 WD, I/O A17 I/O A18 I/O A19 GND A20 GND B1 GND B2 GND B3 DCLK, I/O B4 I/O B5 I/O B6 I/O B7 WD, I/O B8 I/O B9 PRB, I/O B10 I/O B11 I/O B12 WD, I/O B13 I/O B14 I/O B15 WD, I/O B16 I/O B17 WD, I/O B18 I/O B19 GND B20 GND C1 I/O C2 MODE C3 GND C4 I/O C5 WD, I/O C6 I/O C7 QCLKC, I/O C8 I/O C9 I/O C10 CLKB C11 PRA, I/O C12 WD, I/O C13 I/O C14 QCLKD, I/O C15 I/O C16 WD, I/O C17 SDI, I/O C18 I/O C19 I/O C20 I/O D1 I/O D2 I/O D3 I/O D4 I/O D5 V CCI D6 I/O D7 I/O D8 V CCA D9 WD, I/O D10 V CCI 272-Pin PBGA Pin Number A42MX36 Function D11 I/O D12 V CCI D13 I/O D14 V CCI D15 I/O D16 V CCA D17 GND D18 I/O D19 I/O D20 I/O E1 I/O E2 I/O E3 I/O E4 V CCA E17 V CCI E18 I/O E19 I/O E20 I/O F1 I/O F2 I/O F3 I/O F4 V CCI F17 I/O F18 I/O F19 I/O F20 I/O G1 I/O G2 I/O G3 I/O G4 V CCI G17 V CCI G18 I/O G19 I/O G20 I/O H1 I/O 272-Pin PBGA Pin Number A42MX36 Function H2 I/O H3 I/O H4 V CCA H17 I/O H18 I/O H19 I/O H20 I/O J1 I/O J2 I/O J3 I/O J4 V CCI J9 GND J10 GND J11 GND J12 GND J17 V CCA J18 I/O J19 I/O J20 I/O K1 I/O K2 I/O K3 I/O K4 V CCI K9 GND K10 GND K11 GND K12 GND K17 I/O K18 V CCA K19 V CCA K20 LP L1 I/O L2 I/O L3 V CCA L4 V CCA 272-Pin PBGA Pin Number A42MX36 Function

40MX and 42MX FPGA Families 2-36 v6.0 L9 GND L10 GND L11 GND L12 GND L17 V CCI L18 I/O L19 I/O L20 TCK, I/O M1 I/O M2 I/O M3 I/O M4 V CCI M9 GND M10 GND M11 GND M12 GND M17 I/O M18 I/O M19 I/O M20 I/O N1 I/O N2 I/O N3 I/O N4 V CCI N17 V CCI N18 I/O N19 I/O N20 I/O P1 I/O P2 I/O P3 I/O P4 V CCA P17 I/O P18 I/O P19 I/O 272-Pin PBGA Pin Number A42MX36 Function P20 I/O R1 I/O R2 I/O R3 I/O R4 V CCI R17 V CCI R18 I/O R19 I/O R20 I/O T1 I/O T2 I/O T3 I/O T4 I/O T17 V CCA T18 I/O T19 I/O T20 I/O U1 I/O U2 I/O U3 I/O U4 I/O U5 V CCI U6 WD, I/O U7 I/O U8 I/O U9 WD, I/O U10 V CCA U11 V CCI U12 I/O U13 I/O U14 QCLKB, I/O U15 I/O U16 V CCI U17 I/O U18 GND 272-Pin PBGA Pin Number A42MX36 Function U19 I/O U20 I/O V1 I/O V2 I/O V3 GND V4 GND V5 I/O V6 I/O V7 I/O V8 WD, I/O V9 I/O V10 I/O V11 I/O V12 I/O V13 WD, I/O V14 I/O V15 WD, I/O V16 I/O V17 I/O V18 SDO, TDO, I/O V19 I/O V20 I/O W1 GND W2 GND W3 I/O W4 TMS, I/O W5 I/O W6 I/O W7 I/O W8 WD, I/O W9 WD, I/O W10 I/O W11 I/O W12 I/O 272-Pin PBGA Pin Number A42MX36 Function W13 WD, I/O W14 I/O W15 I/O W16 WD, I/O W17 I/O W18 WD, I/O W19 GND W20 GND Y1 GND Y2 GND Y3 I/O Y4 TDI, I/O Y5 WD, I/O Y6 I/O Y7 QCLKA, I/O Y8 I/O Y9 I/O Y10 I/O Y11 I/O Y12 I/O Y13 I/O Y14 I/O Y15 I/O Y16 I/O Y17 I/O Y18 WD, I/O Y19 GND Y20 GND 272-Pin PBGA Pin Number A42MX36 Function

FPGA Families 40MX and 42MX 3-2 v6.0 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are desi gnated as "Product Brief," "Advance d," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.

5.1 In the 160-Pin PQFP table, the following pins changed:

Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP 2-10 In the 208-Pin PQFP table, the following pins changed: Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP Pin 198 (42MX09) has changed to I/O 2-14 The n the 240-Pin PQFP table, the following pins changed: Pin 91 (42MX36) has changed to LP 2-18 In the 100-Pin VQFP Package table, the following pins changed: Pin 62 (42MX09 and 42MX16) has changed to LP 2-23 In the 176-Pin TQFP table, the following pins changed: Pin 109 (42MX09 and 42MX16) has changed to LP 2-25 In the 272-Pin PBGA table, the following pins changed: Pin K20 (42MX36) has changed to LP 2-35 v5.0 The "Low Power Mode" section was updated. 1-7 Footnote 8 in the Table 9  5V TTL Elec trical Specifications was updated. 1-15 Footnote 8 in the Table 13  3.3V LVTTL Electrical Specifications was updated. 1-17 v4.0.1 Because the changes in this data sheet are exte nsive and technical in nature, this should be viewed as a new document. Please read it as you would a data sheet that is published for the first time. ALL Note that the “Package Characteristics and Mech anical Drawings” section has been eliminated from the data sheet. The mechanical drawings are now contained in a separate document, “Package Characteristics and Mechanical Drawings,” available on the Actel web site. Previous version Changes in current version (v6.0) Page

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