A3983 ALLEGRO
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26184.29A A3983 DMOS Microstepping Driver with Translator The A3983 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A3983 includes a fixed off- time current regulator which has the ability to operate in Slow or Mixed decay modes. The translator is the key to the easy implementation of the A3983. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A3983 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. The chopping control in the A3983 automatically selects the current decay mode (Slow or Mixed). When a signal occurs at the STEP input pin, the A3983 determines if that step results in a higher or lower current in each of the motor phases. If the change is to a higher current, then the decay mode is set to Slow decay. If the change is to a lower current, then the current decay is set to Mixed (set initially to a fast decay for a period amounting to 31.25% of the fixed off-time, then to a slow decay for the remainder of the off-time). This current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A3983 is supplied in a low-profile (1.2 mm maximum), 24-pin TSSOP with exposed thermal pad (package LP). It is also available in a lead (Pb) free version (suffix –T), with 100% matte tin plated leadframes. Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO and thermal shutdown circuitry Crossover-current protection Use the following complete part number when ordering: AB SO LUTE MAX I MUM RAT INGS Part Number Pb-free Package Description A3983SLP – 24-pin, TSSOP Exposed thermal pad A3983SLP-T Yes Operating Temperature Range Ambient, T *Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Package LP
FEATURES
& Control Logic Approximate Scale 1:1
26184.29A Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com Allegro MicroSystems, Inc. A3983 DMOS Microstepping Driver with Translator Functional Block Diagram SENSE1 SENSE2 VREG VCP CP2 Control Logic DAC VDD PWM Latch Blanking Mixed Decay DAC STEP DIR RESET MS1 PWM Latch Blanking Mixed Decay Current Regulator CP1 Charge Pump RS2 RS1 VBB1 OUT1A OUT1B VBB2 OUT2A OUT2B 0.1 μF VREF Translator Gate Drive DMOS Full Bridge DMOS Full Bridge 0.1 μF 0.22 μF OSC ROSC MS2 REF ENABLE SLEEP
26184.29A Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. A3983 DMOS Microstepping Driver with Translator ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) 1Negative current is defined as coming out of (sourcing from) the specified device pin. 2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3errI = (ITrip – IProg ) ⁄ IProg , where IProg = %ITripMAX× ITripMAX. Characteristics Symbol Test Conditions Min. Typ.2 Max. Units Output Drivers Load Supply Voltage Range V BB Operating 8 – 35 V During Sleep Mode 0 – 35 V Logic Supply Voltage Range V DD Operating 3.0 – 5.5 V Output On Resistance R DSON Source Driver, IOUT = –1.5 A – 0.350 0.450 Ω Sink Driver, IOUT = 1.5 A – 0.300 0.370 Ω Body Diode Forward Voltage V F Source Diode, IF = –1.5 A – – 1.2 V Sink Diode, IF = 1.5 A – – 1.2 V Motor Supply Current I BB fPWM < 50 kHz – – 4 mA Operating, outputs disabled – – 2 mA Sleep Mode – – 10 μA Logic Supply Current I DD fPWM < 50 kHz – – 8 mA Outputs off – – 5 mA Sleep Mode – – 10 μA Control Logic Logic Input Voltage VIN(1) VDD×0.7 ––V VIN(0) –– VDD×0.3 V Logic Input Current IIN(1) VIN = VDD×0.7 –20 <1.0 20 μA IIN(0) VIN = VDD×0.3 –20 <1.0 20 μA Microstep Select 2 MS2 – 100 – k Ω Input Hysteresis V HYS(IN) 150 300 500 mV Blank Time tBLANK 0.7 1 1.3 μs Fixed Off-Time tOFF OSC > 3 V 20 30 40 μs ROSC = 25 kΩ 23 30 37 μs Reference Input Voltage Range V REF 0–4V Reference Input Current I REF –3 0 3 μA Current Trip-Level Error3 errI VREF = 2 V, %ITripMAX = 38.27% – – ±15 % VREF = 2 V, %ITripMAX = 70.71% – – ±5 % VREF = 2 V, %ITripMAX = 100.00% – – ±5 % Crossover Dead Time t DT 100 475 800 ns Protection Thermal Shutdown Temperature T J – 165 – °C Thermal Shutdown Hysteresis T JHYS –1 5–° C UVLO Enable Threshold UV LO VDD rising 2.35 2.7 3 V UVLO Hysteresis UV HYS 0.05 0.10 – V
26184.29A Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. A3983 DMOS Microstepping Driver with Translator THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA One-layer PCB, one-sided with copper limited to solder pads 100 ºC/W One layer PCB, two-sided with copper limited to solder pads and 3.8 in.2 of copper area on each side, connected to GND pins 32 ºC/W High-K PCB (multilayer with significant copper areas, based on JEDEC standard) 28 ºC/W *In still air. Additional thermal information available on Allegro Web site. 20 40 60 80 100 120 140 160 180 Temperature (°C) Power Dissipation, PD (W) 0.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 Maximum Power Dissipation, PD(max) θJA = 32 ºC/W) Low-K PCB θJA = 100 ºC/W) Minimum-K PCB θJA = 28 ºC/W) High-K PCB
Figure 1. Logic Interface Timing Diagram Table 1. Microstep Resolution Truth Table
26184.29A Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. A3983 DMOS Microstepping Driver with Translator Functional Description Device Operation. The A3983 is a complete microstep- ping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PMW (pulse width modulated) control cir- cuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (R S1 or RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in fig- ures 2 through 5), and the current regulator to Mixed Decay Mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of inputs MS1 and MS2, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode for the active full-bridge is set to Mixed. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back EMF of the motor. RESET Input (RESET). The RESET input sets the translator to a predefined Home state (shown in figures 2 through 5), and turns off all of the DMOS outputs. All STEP inputs are ignored until the RESET input is set to high. Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the combined state of inputs MS1 and MS2. Microstep Select (MS1 and MS2). Selects the micro- stepping format, as shown in table 1. MS2 has a 100 kΩ pull- down resistance. Any changes made to these inputs do not take effect until the next STEP rising edge. Direction Input (DIR). This determines the direction of rotation of the motor. When low, the direction will be clock- wise and when high, counterclockwise. Changes to this input do not take effect until the next STEP rising edge. Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, I TRIP . Ini- tially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and the current sense resistor, R Sx. When the voltage across RSx equals the DAC output voltage, the current sense compara- tor resets the PWM latch. The latch then turns off either the source DMOS FETs (when in Slow Decay Mode) or the sink and source DMOS FETs (when in Mixed Decay Mode). The maximum value of current limiting is set by the selec- tion of R Sx and the voltage at the VREF pin. The transcon- ductance function is approximated by the maximum value of current limiting, I TripMAX (A), which is set by ITripMAX = VREF / ( 8 × RS) where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V). The DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX / 100) × ITripMAX (See table 2 for %ITripMAX at each step.) It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded. Fixed Off-Time. The internal PWM current control cir- cuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The one shot off-time, t OFF, is determined by the selection of an external resistor con- nected from the ROSC timing pin to ground. If the ROSC Functional Description
26184.29A Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. A3983 DMOS Microstepping Driver with Translator pin is tied to an external voltage > 3 V , then tOFF defaults to 30 μs. The ROSC pin can be safely connected to the VDD pin for this purpose. The value of tOFF (μs) is approximately tOFF ≈ ROSC ⁄ 825 Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching tran- sients related to the capacitance of the load. The blank time, t BLANK (μs), is approximately tBLANK ≈ 1 μs Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side DMOS gates. A 0.1 μF ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 μF ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side DMOS gates. VREG (VREG). This internally-generated voltage is used to operate the sink-side DMOS outputs. The VREG pin must be decoupled with a 0.22 μF ceramic capacitor to ground. VREG is internally monitored. In the case of a fault condi- tion, the DMOS outputs of the A3983 are disabled. Enable Input (ENABLE). This input turns on or off all of the DMOS outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, MS1, and MS2, as well as the internal sequencing logic, all remain active, independent of the ENABLE input state. Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the DMOS out- puts of the A3983 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the DMOS outputs and resets the translator to the Home state. Sleep Mode (SLEEP). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output DMOS FETs, current regulator, and charge pump. A logic low on the SLEEP pin puts the A3983 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A3983 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabi- lize, provide a delay of 1 ms before issuing a Step command. Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 3 thru 5. As the trip point is reached, the A3983 initially goes into a fast decay mode for 31.25% of the off-time. t OFF. After that, it switches to Slow Decay mode for the remainder of tOFF. Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed–off-time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low DMOS R DSON. This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Turning off synchronous rectification prevents the reversal of the load current when a zero-current level is detected.
Figure 4. Decay Modes for Quarter-Step Increments Figure 3. Decay Modes for Half-Step IncrementsFigure 2. Decay Mode for Full-Step Increments
Figure 5. Decay Modes for Eighth-Step Increments
Table 2. Step Sequencing Settings
26184.29A Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. A3983 DMOS Microstepping Driver with Translator Pin List Table Name Description Number CP1 Charge pump capacitor 1 1 CP2 Charge pump capacitor 2 2 VCP Reservoir capacitor 3 VREG Regulator decoupling 4 MS1 Logic input 5 MS2 Logic input 6 RESET Logic input 7 ROSC Timing set 8 SLEEP Logic input 9 VDD Logic supply 10 STEP Logic input 11 REF Current trip reference voltage input 12 GND Ground* 13 DIR Logic input 14 OUT1B DMOS Full Bridge 1 Output B 15 VBB1 Load supply 16 SENSE1 Sense resistor for Bridge 1 17 OUT1A DMOS Full Bridge 1 Output A 18 OUT2A DMOS Full Bridge 2 Output A 19 SENSE2 Sense resistor for Bridge 2 20 VBB2 Load supply 21 OUT2B DMOS Full Bridge 2 Output B 22 ENABLE Logic input 23 GND Ground* 24 *The two GND pins must be tied together externally by connecting to the exposed pad ground plane under the device.
26184.29A Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. A3983 DMOS Microstepping Driver with Translator
26184.29A Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. A3983 DMOS Microstepping Driver with Translator The products described here are manufactured under one or Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2005 AllegroMicrosystems, Inc.