A3950SEU-T

A3950_06 ALLEGRO

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Technical content

Approximate Scale 1:1 Package LP, 16 pin TSSOP with Exposed Thermal Pad

Description

Designed for PWM (pulse width modulated) control of dc motors, the A3950 is capable of peak output currents to ±2.8 A and operating voltages to 36 V . PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to lower power dissipation during PWM operation. Internal circuit protection includes motor lead short-to- supply / short-to-ground, thermal shutdown with hysteresis, undervoltage monitoring of V BB and VCP, and crossover-current protection. The A3950 is supplied in a thin profile (<1.2 mm overall height) 16 pin TSSOP package (LP), and a very thin (0.75 mm nominal height) QFN package. Both packages provide an exposed pad for enhanced thermal dissipation, and are lead (Pb) free with 100% matte tin leadframe plating. A3950DS, Rev. 4 Features and Benefits ▪ Low R DS(on) outputs ▪ Overcurrent protection ▪ Motor lead short-to-supply protection ▪ Short-to-ground protection ▪ Sleep function ▪ Synchronous rectification ▪ Diagnostic output ▪ Internal undervoltage lockout (UVLO) ▪ Crossover-current protection DMOS Full-Bridge Motor Driver Packages: Typical Application Diagrams A3950 Package EU, 16 pin QFN with Exposed Thermal Pad Package LPPackage EU VBB 0.1 μF 50 V 0.22 μF 25 V 100 μF 50 V 0.1 μF 50 V 0.1 μF 50 V A3950 VDD 5 kΩ NC OUTA SENSE VBB MODE NFAULT VREG VCPPHASE GND SLEEP ENABLE GND CP2 CP1 OUTB VBB 0.1 μF 50 V 0.22 μF 25 V 0.1 μF 50 V 0.1 μF 50 V 100 μF 50 V A3950 VDD 5 kΩ SLEEP ENABLE OUTA SENSE NFAULT MODE PHASE GND OUTB VBB VCP GND CP2 CP1 VREG NC

DMOS Full-Bridge Motor DriverA3950 2Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Selection Guide Part Number Packing Package A3950SLP-T 96 pieces / tube 16 pin TSSOP with exposed thermal pad A3950SLPTR-T 13 in. reel, 4000 pieces / reel A3950SEU-T 92 pieces / tube 16 pin QFN with exposed thermal pad A3950SEUTR-T 7 in. reel, 1500 pieces / reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage V BB 36 V Output Current I OUT 2.8 A Sense Voltage V SENSE ±500 mV VBB to OUTx 36 V OUTx to SENSE 36 V Logic Input Voltage V IN –0.3 to 7 V Operating Ambient Temperature T A Range S –20 to 85 ºC Maximum Junction Temperature T J(max) 150 ºC Storage Temperature T stg –40 to 125 ºC

DMOS Full-Bridge Motor DriverA3950 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com UVLO STB STG TSD Warning VBB OUTA OUTB SENSE Low-Side Gate Supply Charge Pump Motor Lead Protection Pad Control Logic Bias Supply GND GND SLEEP NFAULT PHASE ENABLEVDD 5 kΩ 5 kΩ MODE VREG 0.22 μF 25 V 0.1 μF 0.1 μF 0.1 μF 100 μF OUTA VBB VCP Load Supply CP2CP1 OUTB SENSE Functional Block Diagram Terminal List Table Name Number NFAULT 15 1 Fault output, open drain MODE 16 2 Logic input PHASE 1 3 Logic input for direction control GND 2, 12 4,13 Ground SLEEP 3 5 Logic input ENABLE 4 6 Logic input OUTA 6 7 DMOS full-bridge output A SENSE 7 8 Power return VBB 8 9 Load supply voltage OUTB 9 10 DMOS full-bridge output B CP1 10 11 Charge pump capacitor terminal CP2 11 12 Charge pump capacitor terminal VCP 13 14 Reservoir capacitor terminal VREG 14 15 Regulator decoupling terminal NC 5 16 No connection Pad – – Exposed pad for thermal dissipation connect to GND pins

DMOS Full-Bridge Motor DriverA3950 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com ELECTRICAL CHARACTERISTICS at TJ = 25°C, VBB = 8 to 36 V, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Units Motor Supply Current I BB fPWM < 50 kHz – 6 8.5 mA Charge pump on, outputs disabled – 3 4.5 mA Sleep mode – – 10 μA PHASE, ENABLE, MODE Input Voltage V IH 2.0 – – V VIL – – 0.8 V SLEEP Input Voltage VIH 2.7 – – V VIL – – 0.8 V PHASE, MODE Input Current1 IIH VIN = 2.0 V – <1.0 20 μA IIL VIN = 0.8 V –20 <–2.0 20 μA ENABLE Input Current IIH VIN = 2.0 V – 40 100 μA IIL VIN = 0.8 V – 16 40 μA SLEEP Input Current IIH VIN = 2.7 V – 27 50 μA IIL VIN = 0.8 V – <1 10 μA NFAULT Output Voltage V OL Isink = 1.0 mA – – 0.4 V Input Hysteresis, except SLEEP V IHys 100 150 250 mV Output On Resistance R DS(on) Source driver, IOUT = -2.8 A, TJ=25°C – 0.35 0.48 Ω Source driver, IOUT = -2.8 A, TJ=125°C – 0.55 0.8 Ω Sink driver, IOUT = 2.8 A, TJ=25°C – 0.3 0.43 Ω Sink driver, IOUT = 2.8 A, TJ=125°C – 0.45 0.7 Ω Body Diode Forward Voltage1 Vf Source diode, If = –2.8 A – – 1.4 V Sink diode, If = 2.8 A – – 1.4 V Propagation Delay Time t pd PWM, change to source or sink ON – 600 – ns PWM, change to source or sink OFF – 100 – ns Crossover Delay t COD – 500 – ns Protection Circuitry UVLO Threshold V UV VBB increasing – 6.5 – V UVLO Hysteresis V UVHys – 250 – mV Overcurrent Threshold2 IOCP 3––A Overcurrent Protection Period t OCP – 1.2 – ms Thermal Warning Temperature T JW Temperature increasing – 160 – °C Thermal Warning Hysteresis T JWHys Recovery = TJW – TJWHys –1 5–° C Thermal Shutdown Temperature T JTSD Temperature increasing – 175 – °C Thermal Shutdown Hysteresis T JTSDHys Recovery = TJTSD – TJTSDHys –1 5–° C 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2Overcurrent protection is tested at 25°C in a restricted range and guaranteed by characterization. THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance R θJA Preliminary: EU package, 4-layer PCB based on JEDEC standard 30 ºC/W LP package, 4-layer PCB based on JEDEC standard 34 ºC/W LP package, 2-layer PCB with 3.8 in.2 copper both sides, connected by thermal vias 43 ºC/W *Additional thermal data available on the Allegro Web site.

DMOS Full-Bridge Motor DriverA3950 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Timing Diagram: PWM Control VBB VBB 23 4 6 7 A Charge pump and VREG power-on delay (≈200 μs) OutBOutAOutA OutB A1 2 3 4 5 6 7 9 8 SLEEP ENABLE PHASE MODE VOUTA VBB VBB VOUTB IOUTX

DMOS Full-Bridge Motor DriverA3950 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com BLANK NFAULT Motor lead short condition Normal dc motor capacitance Charge Pump Counter ENABLE, Source or Sink High-Z IOUTx IPEAK IOCP VOUTA VOUTB tBLANK tOCP Timing Diagram: Overcurrent Control

DMOS Full-Bridge Motor DriverA3950 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Device Operation. The 3950 is designed to operate one dc motor. The currents in the output full-bridges, all N-channel DMOS, are regulated with fixed off-time pulse width modulated (PWM) control circuitry. Logic Inputs. If logic inputs are pulled up to VDD , it is good practice to use a high value pull-up resistor in order to limit cur- rent to the logic inputs should an overvoltage event occur. Logic inputs include: SLEEP, MODE, PHASE, and ENABLE. The voltage on any logic input cannot exceed the specified maximum of 7 V . VREG. This supply voltage is used to run the sink-side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The VREG pin should be decoupled with a 0.22 μF capacitor to ground. Charge Pump. The charge pump is used to generate a sup- ply above V BB to drive the source-side DMOS gates. A 0.1 μF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 μF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power-on the UVLO circuit disables the drivers. Sleep Mode. Control input SLEEP is used to minimize power consumption when the A3950 is not in use. This disables much of the internal circuitry, including the regulator and charge pump. A logic low setting puts the device into Sleep mode, and a logic high setting allows normal operation. After coming out of Sleep mode, provide a 1 ms interval before applying PWM signals, to allow the charge pump to stabilize. MODE. Control input MODE is used to toggle between fast decay mode and slow decay mode. A logic high puts the device in slow decay mode. Synchronous rectification is always enabled. Braking. The braking function is implemented by driving the device in slow decay mode via the MODE setting and applying an enable chop command. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts out the motor generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by V BEMF/RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations: high speed and high-inertia loads. Diagnostic Output. The NFAULT pin signals a problem with the chip via an open drain output. A motor fault, undervoltage condition, or T J > 160°C will drive the pin active low. This output is not valid when SLEEP puts the device into minimum power dissipation mode. TSD. Two die temperature monitors are integrated on the chip. As die temperature increases towards the maximum, a thermal warning signal will be triggered at 160°C. This fault drives the NFAULT low, but does not disable the operation of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs will be disabled until the internal temperature falls below a hysteresis of 15°C. Functional Description Control Logic Table1 Pin Function PHASE ENABLE MODE SLEEP OUTA OUTB 1 1 X 1 H L Forward 0 1 X 1 L H Reverse X 0 1 1 L L Brake (slow decay)

1001 L H Fast Decay Synchronous Rectification

0001 H L Fast Decay Synchronous Rectification2

1X indicates “don’t care,” Z indicates high impedance. 2To prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A.

DMOS Full-Bridge Motor DriverA3950 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Overcurrent Protection. Referring to the figures below, the voltage on the output pins relative to supply are monitored to ensure that the motor lead is not shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag NFAULT is driven low, and a 1.2 ms fault timer is started. After this 1.2 ms period, t OCP , the device will then be allowed to follow the input commands and another turn-on is attempted. If there is still a fault condition, the cycle repeats. If, after t OCP expires, it is determined that the short condition is not present, the NFAULT pin is released and normal operation resumes. Shorted load condition, output current waveform is shown along with the NFAULT output. Shorted load condition illustrating repetitive cycles with a 1.2 ms delay. ISHORT NFAULT 2 μs / div. 2 A / div. Fault asserted ISHORT NFAULT 200 μs / div. 2 A / div.TOCP = 1.2 ms Fault asserted

that could affect critical applications. current is not allowed to go negative (direction change). Instead, as the current approaches zero, the drivers turn off. Figure 1. Current Decay Patterns

DMOS Full-Bridge Motor DriverA3950 10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com SENSE Pin. A low value resistor can be placed between the SENSE pin and ground for current sensing purposes. To mini- mize ground-trace IR drops in sensing the output current level, the current sensing resistor should have an independent ground return to the star ground point. This trace should be as short as possible. For low value sense resistors, the IR drops in the PCB can be significant, and should be taken into account. When selecting a value for the sense resistor be sure not to exceed the maximum voltage on the SENSE pin of ±500 mV . Ground. A star ground should be located as close to the A3950 as possible. The copper ground plane directly under the exposed thermal pad makes a good location for the star ground point. The exposed pad can be connected to ground for this purpose. Layout. The printed circuit board should use a heavy ground- plane. For optimum electrical and thermal performance, the A3950 must be soldered directly onto the board. On the under- side of the A3950 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. The load supply pin, VBB, should be decoupled with an elec- trolytic capacitor (typically 100 μF) in parallel with a ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB, connected to VREG, and between CP1 and CP2, should be as close to the pins of the device as possible, in order to minimize lead inductance. VBB OUTB GND GND CVBB1 CVBB2 OUTA EU package shown VBB C1 C2 CVBB2 PAD CVBB1 A3950 EU PackageNC OUTA SENSE VBB MODE NFAULT VREG VCPPHASE GND SLEEP ENABLE GND CP2 CP1 OUTB

DMOS Full-Bridge Motor DriverA3950 11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3.8 NOM .150 0.15R REF .006 3.8 NOM .150 0.35 NOM .014 0.65 NOM .026 1.15 NOM .045 4X0.20 MIN .008 12X0.20 MIN .008 A B 0.80 0.70 .031 .028 0.05 0.00 .002 .000 0.20 REF .008 CSEATING PLANEC0.08 [.003] 16X 16X 0.10 [.004] M C A B 0.05 [.002] M C 0.35 0.25 .014 .010 0.65 0.45 .026 .018 4.15 3.85 .163 .152 4.15 3.85 .163 .152 0.65 .026 A A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) All dimensions reference only, not for tooling use. (reference JEDEC MO-220WGGC-4) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown C C Reference land pattern layout (reference IPC7351 QFN65P400X400X80-17BM); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 2.15 NOM .085 2.15 NOM .085 2.15 NOM .085 2.15 NOM .085 B 4X 0.20 MIN .008

DMOS Full-Bridge Motor DriverA3950 12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2005, 2006 Allegro MicroSystems, Inc. 2X0.20 MIN .008 1.20 MAX .047 0.15 0.00 .006 .000 0.30 0.19 .012 .007 4.5 4.3 .177 .169 6.6 6.2 .260 .244 0.20 0.09 .008 .004 0.75 0.45 .030 .018 REF .039 5.10 4.90 .201 .193 CSEATING PLANE A B 16X 0.10 [.004] M C A B C0.10 [.004] 16X 0.65 .026 0.25 .010 6.1 NOM .240 0.45 NOM .018 0.65 NOM .026 1.65 NOM .065 NOM .118 NOM .118 NOM .118 NOM .118 14X0.20 MIN .008 GAUGE PLANE SEATING PLANE B A A Terminal #1 mark area B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling All dimensions reference only, not for tooling use. (reference JEDEC MO-153 ABT) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown C Reference land pattern layout (reference IPC7351 TSOP65P640X120-17M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C