A3949_04 ALLEGRO
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29319.47E A3949 DMOS Full-Bridge Motor Driver Designed for PWM (pulse width modulated) control of dc motors, the A3949 is capable of peak output currents to ±2.8 A and operating volt- ages to 36 V . PHASE and ENABLE input terminals are provided for use in control- ling the speed and direction of a dc motor with externally applied PWM control signals. Internal synchronous rectifi cation control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of V BB and VCP , and crossover current protec- tion. The A3949 is supplied in a choice of two power packages, a 16-pin plastic SOIC with a copper batwing tab (part number suffi x LB), and a low profi le (1.1mm) 16-pin TSSOP (suffi x LP) with exposed power tab. Both packages are available in a lead-free version (100% matte tin leadframe). Single supply operation Very small outline package Low RDS(ON) outputs Sleep function Internal UVLO Crossover current protection Thermal shutdown protection Use the following complete part numbers when ordering: AB SO LUTE MAX I MUM RAT INGS Part Number Pb-free * Package Packing A3949SLB-T Yes 16-pin, SOIC 47 per tube A3949SLBTR-T Yes 16-pin, SOIC 1000 per reel A3949SLP-T Yes 16-pin, TSSOP 96 per tube A3949SLPTR-T Yes 16-pin, TSSOP 4000 per reel *Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classifi cation indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadline for receipt of LAST TIME BUY orders: April 27, 2007. These variants include: A3949SLB, A3949SLBTR, A3949SLP, and A3949SLPTR. Load Supply V oltage Package Power Dissipation, PD Operating Temperature Range Ambient Temperature, T 1Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, DO NOT exceed the specifi ed IOUT or TJ. 2Measured on a typical two-sided PCB with 2 in.2 copper ground plane. 3Measured on a JEDEC-standard "High-K" 4-layer PCB.
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Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com Data Sheet 29319.47D A3949 DMOS Full-Bridge Motor Driver Functional Block Diagram VREG CP2 Load Supply Low Side Gate Supply CP1 Charge Pump 0.1 μF 0.1 μF DMOS Full Bridge OSC .22 μF 25 V 0.1 μF 100 μF Control Logic MODE PHASE ENABLE SLEEP VCP VBB OUTA OUTB SENSE GND GND PHASE ENABLE MODE SLEEP OUTA OUTB Function 1 1 X 1 H L Forward 0 1 X 1 L H Reverse X 0 1 1 L L Brake (slow decay) 1001LH Fast decay SR* 0001HL Fast decay SR* X X X 0 Hi-Z Hi-Z Sleep mode Control Logic Table * To prevent reversal of current during fast decay SR (synchronous rectifi cation), the outputs go to the high impedance state as the current approaches zero.
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Data Sheet 29319.47D A3949 DMOS Full-Bridge Motor Driver ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 8 V to 36 V (unless otherwise noted) Characteristics Symbol Test Conditions Min. Typ. Max. Units Output-On Resistance R DSON Source driver, IOUT = –2.8 A, TJ= 25°C – .4 .48 Ω Source driver, IOUT = –2.8 A, TJ= 125°C – .68 – Ω Sink driver, IOUT = 2.8 A, TJ= 25°C – .3 .43 Ω Sink driver, IOUT = –2.8 A, TJ= 125°C – .576 – Ω Body Diode Forward Voltage V F Source diode, IF = –2.8 A – 1.1 1.3 V Sink diode, IF = 2.8 A – 1 1.3 V Motor Supply Current I BB fPWM < 50 kHz – 6 8.5 mA Charge pump turned on; outputs disabled – 3 4.5 mA Sleep mode – – 10 μA Logic Input Voltage PHASE, ENABLE, MODE V IN(1) 2.0 – – V VIN(0) – – 0.8 V Logic Input Voltage SLEEP VIN(1) 2.7 – – V VIN(0) – – 0.8 V Logic Input Current PHASE, MODE pins IIN(1) VIN = 2.0 V – < 1.0 20 μA IIN(0) VIN = 0.8 V – < –2.0 –20 μA Logic Input Current ENABLE pin IIN(1) VIN = 2.0 V – 40 100 μA IIN(0) VIN = 0.8 V – 16 40 μA Logic Input Current SLEEP pin IIN(1) VIN = 2.7 V – 27 50 μA IIN(0) VIN = 0.8 V – < 1 10 μA Propagation Delay Times t pd From PWM change to source or sink turn on – 600 – ns From PWM change to source or sink turn off – 100 – ns Crossover Delay t COD – 500 – ns Protection Circuitry UVLO Enable Threshold VBB rising – 6 – V UVLO Hysteresis – 250 – mV Thermal Shutdown Temp. T J – 170 – °C Thermal Shutdown Hysteresis ΔTJ –1 5 – ° C
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Data Sheet 29319.47D A3949 DMOS Full-Bridge Motor Driver PWM Control Timing Diagram ENABLE PHASE MODE OUTA OUTB IOUT 0 V 0 V SLEEP A Charge pump and VREG power-up delay (approximately 200 us) 0 A 2 3 4 5 6 7 98 VBB VBB A 1 VBB VBB OUTBOUTAOUTA OUTB
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Data Sheet 29319.47D A3949 DMOS Full-Bridge Motor Driver VREG. This supply voltage is used to operate the sink- side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The VREG pin should be decoupled with a 0.22 μF capacitor to ground. Charge Pump. The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1 uF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 uF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high side DMOS devices. The VCP voltage is internally monitored, and in the case of a fault condition, the outputs of the device are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power-up, the UVLO circuit disables the drivers. Sleep Mode. Control input SLEEP is used to minimize power consumption when the A3949 is not in use. This disables much of the internal circuitry, including the low-side gate supply and the charge pump. A logic low on this pin puts the device into Sleep mode. A logic high allows normal operation. After coming out of Sleep mode, the user should wait 1 ms before applying PWM signals, to allow the charge pump to stabilize. Braking. The braking function is implemented by driv- ing the device in slow decay mode via the MODE pin, and applying an enable chop command. Because it is possible to drive current in both directions through the DMOS switches, this confi guration effectively shorts out the motor-generated BEMF, as long as the enable chop mode is asserted on the ENABLE pin. The maximum current can be approximated by V BEMF / RL. Care should be taken to insure that the maxi- mum ratings of the device are not exceeded in worse case braking situations of high speed and high inertial loads. Functional Description
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Data Sheet 29319.47D A3949 DMOS Full-Bridge Motor Driver Terminal List Table Name Description Number TSSOP-16 SOIC-16 N/C Not used 1 1 MODE Logic input 2 2 PHASE Logic input for direction control 3 3 GND Ground 4* 4* SLEEP Logic input 5 5 ENABLE Logic input 6 6 OUTA Output A for full bridge 7 7 SENSE Power return 8 8 VBB Load supply voltage 9 9 OUTB Output B for full bridge 10 10 CP1 Charge pump capacitor 11 11 CP2 Charge pump capacitor 12 12 GND Ground 13* 13* VCP Reservoir capacitor 14 14 VREG Low side gate supply decoupler 15 15 N/C Not used 16 16 *For the TSSOP package, connect pins 4 and 13 to the exposed thermal pad via the PCB layout. In the SOIC package, the pins are internally connected.
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Data Sheet 29319.47D A3949 DMOS Full-Bridge Motor Driver A3949SLB 16-Pin Batwing SOIC NOTES: 1. Exact body and lead confi guration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 0.20 0.09 0.008 0.004 .75 .45 0.030 0.018 1.20 MAX 0.047 .15 .00 0.006 0.000 .30 .19 0.012 0.007 4.5 4.3 0.177 0.169 6.6 6.2 0.260 0.244 REF 0.039 5.1 4.9 0.201 0.193 .65 BSC .026 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface) Gauge Plane Seating Plane BSC 0.118 BSC 0.118 .25 BSC 0.010 A .65 BSC .026 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface) Gauge Plane Seating Plane BSC 0.118 BSC 0.118 .25 BSC 0.010 A A3949SLP 16-Pin TSSOP .406 .398 10.31 10.11 .299 .291 7.59 7.39 .414 .398 10.52 10.11 .020 .014 0.51 0.36 .026 REF 0.66 .050 BSC 1.27 .012 .004 0.30 0.10 .104 .096 2.64 2.44 .040 .020 1.02 0.51 .011 .009 0.28 0.23 Dimensions in inches Metric dimensions (mm) in brackets, for reference only Leads 4 and 13 are connected inside the device package. No internal connection of leads for thermal dissipation.
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Data Sheet 29319.47D A3949 DMOS Full-Bridge Motor Driver The products described here are manufactured under one or Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon - si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2003, 2004 AllegroMicrosystems, Inc.