A3946KLP

3946_04 ALLEGRO

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29319.150b 3946 Half-Bridge Power MOSFET Controller The A3946 is designed specifi cally for ap pli ca tions that require high power unidirectional dc motors, three-phase brushless dc motors, or other inductive loads. The A3946 provides two high-current gate drive outputs that are capable of driving a wide range of power N-channel MOSFETs. The high-side gate driver switches an N-channel MOSFET that controls current to the load, while the low-side gate driver switches an N-channel MOSFET as a synchronous rectifi er. A bootstrap capacitor provides the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high side allows for dc (100% duty cycle) operation of the half-bridge. The A3946 is available in a choice of two power pack ag es: a 16-lead SOIC with internally fused leads (part number suffi x LB), and a 16-lead TSSOP with ex posed thermal pad (suffi x LP). Both packages have a lead (Pb) free version, with 100% matte tin plated leadframes (suffi x -T). „ On-chip charge pump for 7 V minimum input supply voltage „ High-current gate drive for driving a wide range of N-channel MOSFETs „ Bootstrapped gate drive with charge pump for 100% duty cycle „ Overtemperature protection „ Undervoltage protection „ –40ºC to 135ºC ambient operation Package Thermal Resistance, RJA Operating Temperature Range, TA ..–40°C to +135°C Storage Temperature Range, TS ....-55°C to +150°C Notes: 1. Measured on a two-sided PCB with 3 in.2 of 2 oz. copper. 2. Measured on JEDEC standard High-K board. AB SO LUTE MAX I MUM RAT INGS A3946KLB SOIC A3946KLP TSSOP with Exposed Thermal Pad 16VREG CP2 CP1 PGND GL S GH BOOT VBB VREF DT LGND RESET IN2 IN1 ~FAULT

FEATURES

Scale 1:1 Scale 1:1 16VREG CP2 CP1 PGND GL S GH BOOT VBB VREF DT LGND RESET IN2 IN1 ~FAULT Selection Guide Part Number Pb-free Packing Package A3946KLB – 47 pieces/tube 16-pin SOIC with internally fused leads A3946KLB-T Yes A3946KLBTR – 1000 pieces/reel A3946KLBTR-T Yes A3946KLP – 96 pieces/tube 16-pin TSSOP with exposed thermal pad A3946KLP-T Yes A3946KLPTR – 4000 pieces/reel A3946KLPTR-T Yes

Worcester, Massachusetts 01615-0036 (508) 853-5000

115 Northeast Cutoff, Box 15036

www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller Functional Block Diagram Control Logic Table IN1 IN2 DT Pin RESET GH GL Function X X X 0 Z Z Sleep mode

00 R DEAD - LGND 1 L H Low-side FET ON following dead time

01 R DEAD - LGND 1 L L All OFF

10 R DEAD - LGND 1 L L All OFF

11 R DEAD - LGND 1 H L High-side FET ON following dead time

0 1 VREF 1 L H Low-side FET ON 1 0 VREF 1 H L High-side FET ON 1 1 VREF 1 H H CAUTION: High-side and low-side FETs ON VBB VREG CBOOT +VBAT +5 Vref Charge Pump BOOT GH S GL LGND VREG CP1CP2 Charge Pump RESET Protection VREG Undervoltage Overtemperature UVLOBOOT IN2 ~FAULT DT Control Logic Turn-On Delay IN1 RDEAD VREF VREF Bootstrap UVLO kΩ CREG 0.47 uF, X7R V rated to VBAT R GATE RGATE ILIM PGND High Side Driver Low Side Driver 0.47 uF, X7R V rated to VBAT 0.1 uF X7R 10 V P L PL L L L L L P PL P P

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted) Characteristics Symbol Test Conditions Limits Min. Typ. Max. Units VBB Quiescent Current I VBB RESET = High, Outputs Low – 36 m A RESET = Low –– 10 μA VREG Output Voltage V REG VBB > 7.75 V, Ireg = 0 mA to 15 mA 12.0 13 13.5 V VBB = 7 V to 7.75 V, Ireg = 0 mA to 15 mA 11.0 – 13.5 V Charge Pump Frequency F CP CP1, CP2 – 62.5 – kHz VREF Output Voltage V REF IREF ≤ 4 mA, CREF = 0.1 μF 4.5 – 5.5 V Gate Output Drive Turn On Time t rise CLOAD = 3300 pF, 20% to 80% – 60 100 ns Turn Off Time t fall CLOAD = 3300 pF, 80% to 20% – 40 80 ns Pullup On Resistance R DSUP Tj = 25°C – 4 – Ω Tj = 135°C – 6 – Ω Pulldown On Resistance R DSDOWN Tj = 25°C – 2 – Ω Tj = 135°C – 3 – Ω Short Circuit Current – Source – tpw < 10 μs 800 –– mA Short Circuit Current – Sink – tpw < 10 μs 1000 –– mA GH Output Voltage V GH tpw < 10 μs, Bootstrap Capacitor fully charged V REG – 1.5 –– V GL Output Voltage V GL – VREG – 0.2 –– V Timing Dead Time (Delay from Turn Off to Turn On) tDEAD Rdead = 5 kΩ 200 350 500 ns Rdead = 100 kΩ 567 μs Propagation Delay t PD Logic input to unloaded GH, GL. DT = VREF –– 150 ns

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Protection VREG Undervoltage V REGON VREG increasing 8.6 9.1 9.6 V VREG Undervoltage V REGOFF VREG decreasing 7.8 8.3 8.8 V BOOT Undervoltage V BSON VBOOT increasing 8 8.75 9.5 V BOOT Undervoltage V BSOFF VBOOT decreasing 7.25 8.0 8.75 V Thermal Shutdown Temperature T JTSD Temperature increasing – 170 – °C Thermal Shutdown Hysteresis ΔTJ Recovery = TJTSD – ΔTJ – 15 – °C Logic Input Current I IN(1) IN1 VIN / IN2 VIN = 2.0 V – 40 100 μA IIN(0) IN1 VIN / IN2 VIN = 0.8 V – 16 40 μA RESET pin only –– 1 μA Logic Input Voltage V IN(1) IN1 / IN2 logic high 2.0 –– V RESET logic high 2.2 –– V VIN(0) Logic low –– 0.8 V Logic Input Hysteresis – All digital inputs 100 – 300 mV Fault Output Vol I = 1 mA, fault asserted –– 400 mV Voh V = 5 V –– 1 μA ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller VREG. A 13 V output from the on-chip charge pump, used to power the low-side gate drive circuit directly, provides the current to charge the bootstrap capacitors for the high-side gate drive. The VREG capacitor, C REG, must supply the instantaneous current to the gate of the low-side MOSFET. A 10 μF, 25 V capacitor should be adequate. This capacitor can be either electrolytic or ceramic (X7R). Diagnostics and Protection. The fault output pin, ~FAULT, goes low (i.e., FAULT = 1) when the RESET line is high and any of the following conditions are present:

• Undervoltage conditions on VREG (UVREG) or on the internal logic supply VREF (UVREF). These conditions set a latched fault.
• A junction temperature > 170°C (OVERTEMP). This con- dition sets a latched fault.
• An undervoltage on the stored charge of the BOOT capaci- tor (UVBOOT). This condition does NOT set a latched fault. An overtemperature event signals a latched fault, but does not disable any output drivers, regulators, or logic inputs. The user must turn off the A3946 (e.g., force the RESET line low) to prevent damage. The power FETs are protected from inadequate gate drive voltage by undervoltage detectors. Either of the regulator undervoltage faults (UVREG or UVREF) disable both output drivers until both voltages have been restored. The high-side driver is also disabled during a UVBOOT fault condition. Under many operating conditions, both the high-side (GH) and low-side (GL) drivers may be off, allowing the BOOT capacitor to discharge (or never become charged) and create a UVBOOT fault condition, which in turn inhibits the high- side driver and creates a FAULT = 1. This fault is NOT latched. To remove this fault, momentarily turn on GL to charge the BOOT capacitor. Latched faults may be cleared by a low pulse, 1 to 10 μs wide, on the RESET line. Throughout that pulse (despite a possible UVBOOT), FAULT = 0; also the fault latch is cleared immediately, and remains cleared. If the power is restored (no UVREG or UVREF), and if no OVERTEMP fault exists, then the latched fault remains cleared when the RESET line returns to high. However, FAULT = 1 may still occur because a UVBOOT fault condition may still exist. Charge Pump. The A3946 is designed to ac com mo date a wide range of power supply voltages. The charge pump output, VREG, is regulated to 13 V nominal. In all modes, this regulator is current-limited. When V BB < 8 V , the charge pump operates as a voltage doubler. When

8 V < V

BB< 15 V , the charge pump operates as a voltage doubler/PWM, current-controlled, voltage regulator. When V BB>15 V , the charge pump operates as a PWM, current-con- trolled, voltage regulator. Effi ciency shifts, from 80% at VBB= 7 V , to 20% at VBB = 50 V . CAUTION. Although simple paralleling of VREG supplies from several A3946s may appear to work correctly, such a confi guration is NOT recommended. There is no assurance that one of the regulators will not dominate, taking on all of the load and back-biasing the other regulators. (For example, this could occur if a particular regulator has an internal refer- ence voltage that is higher that those of the other regulators, which would force it to regulate at the highest voltage.) Sleep Mode/Power Up. In Sleep Mode, all circuits are disabled in order to draw minimum current from VBB. When powering up and leaving Sleep Mode (the RESET line is high), the gate drive outputs stay disabled and a fault remains asserted until VREF and VREG pass their undervoltage thresholds. When powering up, before starting the fi rst boot- strap charge cycle, wait until t = C REG ⁄ 4 (where CREG is in μF, and t is in ns) to allow the charge pump to stabilize. When powered-up (not in Sleep Mode), if the RESET line is low for > 10 μs, the A3946 may start to enter Sleep Mode (VREF < 4 V). In that case, ~FAULT = 1 as long as the RESET line remains low. If the RESET line is open, the A3946 should go into Sleep Mode. However, to ensure that this occurs, the RESET line must be grounded. Functional Description

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller Dead Time. The analog input pin DT sets the delay to turn on the high- or low-side gate outputs. When in struct ed to turn off, the gate outputs change after an short internal propa- gation delay (90 ns typical). The dead time controls the time between this turn-off and the turn-on of the appropriate gate. The duration, t DEAD, can be adjusted within the range 350 ns to 6000 ns using the following formula: tDEAD = 50 + (RDEAD ⁄ 16.7 ) where tDEAD is in ns, and RDEAD is in Ω, and should be in the range 5 kΩ < RDEAD < 100 kΩ. Do not ground the DT pin. If the DT pin is left open, dead time defaults to 12 μs. Control Logic. Two different methods of control are possible with the A3946. When a resistor is connected from DT to ground, a single-pin PWM scheme is utilized by short- ing IN1 with IN2. If a very slow turn-on is required (greater than 6 μs), the two input pins can be hooked-up individually to allow the dead times to be as long as needed. The dead time circuit can be disabled by tying the DT pin to VREF. This disables the turn-on delay and allows direct control of each MOSFET gate via two control lines. This is shown in the Control Logic table, on page 2. Top-Off Charge Pump. An internal charge pump allows 100% duty cycle operation of the high-side MOSFET. This is a low-current trickle charge pump, and is only operated after a high-side has been signaled to turn on. A small amount of bias current (< 200 μA) is drawn from the BOOT pin to operate the fl oating high-side circuit. The charge pump simply provides enough drive to ensure that the gate voltage does not droop due to this bias supply current. The charge required for initial turn-on of the high-side gate must be sup- plied by bootstrap capacitor charge cycles. This is described in the section Application Information. VREF. VREF is used for the internal logic circuitry and is not intended as an external power supply. However, the VREF pin can source up to 4 mA of current. A 0.1 μF capacitor is needed for decoupling. Fault Response Table Fault Mode RESET ~FAULT VREG VREF GH 1 GL1 No Fault 1 1 ON ON (IL) (IL) BOOT Capacitor Undervoltage2 1 0 ON ON 0 (IL) VREG Undervoltage3 1 0 ON ON 0 0 VREF Undervoltage4 1 0 OFF ON 0 0 Thermal Shutdown3 1 0 ON ON (IL) (IL) Sleep5 0 1 OFF OFF High Z High Z 1(IL) indicates that the state is determined by the input logic. 2This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched. 3These faults are latched. Clear by pulsing RESET = 0. 4Unspecifi ed VREF undervoltage threshold < 4 V. 5During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to be- come high impedance (High Z). Refer to the section Sleep Mode/Power Up.

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller

Application Information

Bootstrap Capacitor Selection. CBOOT must be cor- rectly selected to ensure proper operation of the device. If too large, time is wasted charging the capacitor, with the result being a limit on the maximum duty cycle and PWM frequency. If the capacitor is too small, the voltage drop can be too large at the time the charge is trans ferred from the C BOOT to the MOSFET gate. To keep the voltage drop small: QBOOT >> QGATE where a factor in the range of 10 to 20 is reasonable. Using 20 as the factor: QBOOT = CBOOT × VBOOT = QGATE × 20 and CBOOT = QGATE × 20 / VBOOT The voltage drop on the BOOT pin, as the MOSFET is being turned on, can be approximated by: Delta_v = QGATE / CBOOT For example, given a gate charge, QGATE, of 160 nC, and the typical BOOT pin voltage of 12 V , the value of the Boot capacitor, C BOOT, can be determined by: CBOOT = (160 nC × 20) / 12 V ≈ 0.266 μF Therefore, a 0.22 μF ceramic (X7R) capacitor can be chosen for the Boot capacitor. In that case, the voltage drop on the BOOT pin, when the high-side MOSFET is turned on, is: Delta_v = 160 nC / 0.22 μF = 0.73 V Bootstrap Charging. It is good practice to ensure that the high-side bootstrap capacitor is completely charged before a high-side PWM cycle is re quest ed. The time required to charge the capacitor can be ap prox i- mat ed by: tCHARGE = CBOOT (Delta_v / 100 mA) At power-up and when the drivers have been disabled for a long time, the bootstrap capacitor can be completely discharged. In this case, Delta_v can be considered to be the full high-side drive voltage, 12 V . Otherwise, Delta_v is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the S pin is pulled low, via a GL PWM cycle, and current fl ows from VREG through the internal bootstrap diode circuit to C BOOT. Power Dissipation. For high ambient temperature applications, there may be little margin for on-chip power con sump tion. Careful attention should be paid to ensure that the op er at ing conditions allow the A3946 to remain in a safe range of junction temperature. The power consumed by the A3946 can be es ti mat ed as: P_total = Pd_bias + Pd_cpump + Pd_switching_loss where: Pd_bias = VBB × IVBB , typically 3 mA, and Pd_cpump = (2VBB – VREG) IAV E, for VBB < 15 V , or Pd_cpump = (VBB – VREG) IAV E, for VBB > 15 V , in either case, where IAV E = QGATE × 2 × fPWM and Pd_switching_loss = QGATE × VREG × 2 × fPWM Ratio, where Ratio = 10 Ω / (RGATE + 10 Ω).

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller L PL P VREG CBOOT +VBAT +5 Vref Charge Pump BOOT GH S GL LGND VREG CP1CP2 Charge Pump RESET Protection VREG Undervoltage Overtemperature UVLOBOOT IN2 ~FAULT DT Control Logic Turn-On Delay IN1 RDEAD 15.8 kΩ VREF Bootstrap UVLO kΩ CREG 0.47 μF RGATE RGATE ILIM High Side Driver Low Side Driver 10 μF 0.1 uF VREF 10 μF IRF2807 IRF2807 0.47 μF 33 Ω 200 kΩ 33 Ω External +5 V IN IN Brake Forward M DC Motor PGND L P L L L L P PL P Application Block Diagrams Diagram A. Dependent drivers. Unidirectional motor control with braking and dead time. TDEAD = 1 μs; QTOTAL = 160 nC.

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller VREG CBOOT +VBAT +5 Vref Charge Pump BOOT GH S GL LGND VREG CP1CP2 Charge Pump RESET Protection VREG Undervoltage Overtemperature UVLOBOOT IN2 ~FAULT DT Control Logic Turn-On Delay IN1 VREF Bootstrap UVLO kΩ CREG 0.47 μF RGATE ILIM High Side Driver Low Side Driver 10 μF 0.1 uF VREF 10 μF IRF2807 IRF2807 0.47 μF 33 Ω External +5 V Slow Decay Forward VREF Forward Slow Decay DC Motor #1 DC Motor #2 200 kΩ M DC Motor #2 M DC Motor #1 PGND PL P L P L L L L P P 200 kΩ RGATE 33 Ω PL Diagram B. Independent drivers. One high-side drive and one low-side drive.

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller VREG +VBAT +5 Vref Charge Pump BOOT GH S GL LGND VREG CP1CP2 Charge Pump RESET Protection VREG Undervoltage Overtemperature UVLOBOOT IN2 ~FAULT DT Control Logic Turn-On Delay IN1 VREF Bootstrap UVLO kΩ CREG 0.47 μF RGATE RGATE ILIM High Side Driver Low Side Driver 10 μF 0.1 uF VREF 10 μF IRF2807 IRF2807 33 Ω 33 Ω External +5 V Slow Decay Forward VREF Forward Slow Decay DC Motor #1 DC Motor #2 200 kΩ 200 kΩ PGND DC Motor M DC Motor M PL P L P L L L L P PL P P Diagram C. Independent drivers. Two low-side drives.

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller Pin Name Pin Description SOIC-16 (A3946KLB) TSSOP-16 (A3946KLP) VREG Gate drive supply. 1 1 CP2 Charge pump capacitor, positive side. When not using the charge pump, leave this pin open. 22 CP1 Charge pump capacitor, negative side. When not using the charge pump, leave this pin open. 33 PGND* External ground. Internally connected to the power ground. 4 4 GL Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output. S Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap capacitor and negative supply connection for the fl oating high-side drive. GH High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output. BOOT High-side connection for bootstrap capacitor, positive supply for the high-side gate drive. 88 ~FAULT Diagnostic output, open drain. Low during a fault condition. 9 9 IN1 Logic control. 10 10 IN2 Logic control. 11 11 RESET Logic control input. When RESET = 0, the chip is in a very low power sleep mode. 12 12 LGND* External ground. Internally connected to the logic ground. 13 13 DT Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this input high disables the dead time circuit and changes the logic truth table. 14 14 VREF 5 V internal reference decoupling terminal. 15 15 VBB Supply Input. 16 16 *In the LB package, the PGND pin (4) and LGND pin (13) grounds are internally connected by the leadframe. In the LP package, however, the PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally. In the LP package, the exposed thermal pad is not connected to any pin, but should be externally connected to ground, to reduce noise pickup by the pad.

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller A3946KLB SOIC NOTES: 1. Exact body and lead confi guration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel. .406 .398 10.31 10.11 .299 .291 7.59 7.39 .414 .398 10.52 10.11 .020 .014 0.51 0.36 .026 REF 0.66 .050 BSC 1.27 .012 .004 0.30 0.10 .104 .096 2.64 2.44 .040 .020 1.02 0.51 .011 .009 0.28 0.23 Dimensions in inches Metric dimensions (mm) in brackets, for reference only Webbed lead frame. Leads 4 and 13 are joined together within the device package. A3946KLP TSSOP with Exposed Thermal Pad 0.20 0.09 0.008 0.004 .75 .45 0.030 0.018 1.20 MAX 0.047 .15 .00 0.006 0.000 .30 .19 0.012 0.007 4.5 4.3 0.177 0.169 6.6 6.2 0.260 0.244 REF 0.039 5.1 4.9 0.201 0.193 .65 BSC .026 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface) Gauge Plane Seating Plane BSC 0.118 BSC 0.118 .25 BSC 0.010 A .65 BSC .026 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface) Gauge Plane Seating Plane BSC 0.118 BSC 0.118 .25 BSC 0.010 A

Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller Copyright©2003, 2004 AllegroMicrosystems, Inc. The products described here are manufactured under one or Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical compo- nents in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and re- liable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si - bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.