3936 ALLEGRO
Document overview
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Technical content
Features
±3 A, 50 V Continuous Output Rating Low rDS(on) Outputs (typically 500 mΩ source, 315 mΩ sink) Configurable Mixed, Fast and Slow Current-Decay Modes Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection Tachometer Output for External Speed Control Loop Always order by complete part number Part Number Package A3936SED 44-pin PLCC A3936SED-T 44-pin PLCC, Lead-free ABSOLUTE MAXIMUM RATINGS at TA = +25°C Logic Input Voltage Range, VIN Package Power Dissipation, Operating Temperature Range, Storage Temperature Range, * Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. DMOS THREE-PHASE PWM MOTOR DRIVER
3936 Three Phase PWM Motor Driver
.1uF R S REGULATOR CHARGE PUMP VREG CP1 CP2 BANDGAP .22uf/100V .22uf/50V .22uf/50V GATE DRIVE HA+ HB- PWM TIMER OSC TACH OUTA OUTB OUTC OVERVOLTAGE UNDERVOLTAGE AND FAULT DETECT BUFFER/ DIVIDER VCPVREG HB+ HC- HC+ HALL HALL HALL Comm Logic DIR SLEEP Control Logic VCP VBB1 ENABLE EXTMODE BRAKE SR BLANK HBIAS PFD1 PFD2 VDD VBB2 LSS1 LSS2
ELECTRICAL CHARACTERISTICS at T J = +25°C, VBB = 50 V, VDD =5 . 0V ,fPWM < 50KHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Output Drivers Load Supply Voltage Range VBB Operating 9 – 50 V During Sleep Mode 0 50 V Output Leakage Current I DSS VOUT =V BB –< 1 . 0 2 0 µ A VOUT = 0 V – <–1.0 -20 µA Output On Resistance R DSON Source Driver, IOUT = -3A – .55 Ω Sink Driver, IOUT =3 A – . 3 5 Ω Body Diode Forward Voltage V F Source Diode, IF = -3A – – 1.4 V Sink Diode, IF =3 A – – 1 . 3 V Motor Supply Current I BB fPWM <5 0k H z – 4 7 m A Charge Pump On, Outputs Disabled – 2 5 mA Sleep Mode – – 20 uA IDD fPWM <5 0k H z – 1 0 m A Outputs Off – 8 mA Logic Supply Current Sleep Mode (Inputs below .5V) 100 µA Control Logic Logic Supply Voltage Range V DD Operating 3 5.0 5.5 V Logic Input Voltage V IN(1) VDD *.5 – – V VIN(0) –– V DD *.2 V Logic Input Current I IN(1) VIN =V DD *.5 -20 <1.0 20 µA (except ENABLE) I IN(0) VIN=V DD *.2 -20 <-1.0 20 µA Logic Input Current I IN(1) VIN =V DD *.5 – 100 µA ENABLE Input I IN(0) VIN =V DD *.2 – 30 µA OSC shorted to GND 3 4 5 MHzInternal Oscillator f OSC R OSC = 51K 3.4 4 4.6 MHz
ELECTRICAL CHARACTERISTICS at T J = +25°C, VBB =5 0V ,V DD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Control Logic Buffer Input Offset Volt. V IO ±10 mV VREF Input Voltage Range Operating 0.0 – V DD V Reference Input Current I REF VREF =V DD ,VBB =0 to 50V -.5 0 0.5 µA Comparator Input Offset Volt. V IO VREF =0V ± 5 m V VREF =V DD -4 4 %G M Error V ERR (Note 3) VREF =. 5 V - 1 4 1 4 % Propagation Delay Times tpd 50% TO 90%, SR Enabled PWM CHANGE TO SOURCE ON 600 750 1000 ns PWM CHANGE TO SOURCE OFF 50 150 350 ns PWM CHANGE TO SINK ON 600 750 1000 ns PWM CHANGE TO SINK OFF 50 100 150 ns Crossover Delay t COD SR Enabled 300 600 1000 ns Thermal Shutdown Temp. T J – 165 – °C Thermal Shutdown Hysteresis ΔTJ –1 5– ° C UVLO Enable Threshold Rising V DD 2.45 2.7 2.95 V UVLO Hysteresis 0.05 0.10 – V NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device pin. VERR =((VREF /10) – VSENSE )/(VREF /10)
ELECTRICAL CHARACTERISTICS at T A = +25°C, VBB =5 0V ,V DD =5 . 0Vf PWM < 50KHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Hall Logic Hall Input Current I HALL VIN =1 . 2 V - 1 0 1 µA Common Mode Input Range VCMR .3 2.5 V AC Input Voltage Range V HALL .120 Vp-p Hysteresis V HYS TA= -20 to 85 deg C. 10 30 mV Pulse Reject Filter 35 . 5 8 µs Hall Bias Output Sat Voltage V HB IOUT =40mA, TA= -20 to 85 deg C. .4 .5 V IHB 40 mA Tach Output V OL IOUT = 500uA .5 V NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device pin. Commutation Truth Table 120 spacing Outputs HA HB HC DIR OUTA OUTB OUTC 1+-+F O R H I L O Z 2+- - F O R H I Z L O 3++- F O R Z H I L O 4-+- F O R L O H I Z 5-+ +F O R L O Z H I 6- -+F O R Z L O H I 1+-+ R E V L O H I Z 2 + - - REV LO Z HI 3 + + - REV Z LO HI 4-+- R E V H I L O Z 5-+ +R E V H I Z L O 6 - - + REV Z HI LO --- X Z Z Z +++ X Z Z Z
VREG. The VREG pin should be decoupled with a 0.22 µF capacitor to ground. This supply voltage is used to run the sink side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The Charge Pump is used to generate a supply above VBB to drive the source sideDMOS gates. A 0.22 uF ceramic monolithic capacitor should be connected between CP 1 and CP2 for pumping purposes. A 0.22 uF ceramic monolithic capacitor should be connected between V CP and VBB to act as a reservoir to run the high side DMOS devices. The VCP Voltage is internally monitored and in the case of a fault condition the outputs of the device are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG ,t h e outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low V DD ,t h e UVLO circuit disables the drivers. Current Regulation.Load current is regulated by an internal fixed off time PWM control circuit. When the outputs of the DMOS H-bridge are turned on, current increases in the motor winding until it reaches a value given by: I TRIP =V REF /(10*RSENSE ) At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed off time period. The current path during recirculation is determined by the configuration of slow/mixed decay mode and the synchronous rectification control setting. Enable Logic.The Enable input terminal allows external PWM. ENABLE high turns ON the selected sink- source pair, enable low switches off the appropriate drivers and the load current decays. If the ENABLE pin is held high, the current will rise until it reaches the level set by the internal current control circuit. ENABLE Outputs
0 Source
Extmode Logic.When using external PWM current control, the EXTMODE input determines the current path during the chopped cycle. With EXTMODE set low, fast decay mode, both the source and sink drivers are chopped OFF during the decay time (ENABLE=0). With EXTMODE high, slow decay mode, only the source driver turns off during the current decay time. EXTMODE Decay 0F a s t 1S l o w Sleep Mode.The input pin SLEEP is dedicated to put the device into a minimum current draw mode. When asserted low, all circuits are disabled. Fixed Off-Time.The 3936 is set for a fixed off time of 96 counts of the internal oscillator, typically 24µs with 4Mhz oscillator. Internal Current Control Mode.Input pins PFD1 and PFD2 determine the current decay method after an overcurrent event is detected at sense input. In slow decay mode both sink side drivers are turned on for the fixed off time period. Mixed decay mode starts out in fast decay mode for the selected percentage of the fixed off time, and then is followed by slow decay for the rest of the period. PFD2 PFD1 % t OFF Decay 00 0 S l o w 0 1 15 Mixed 1 0 48 Mixed 1 1 100 Fast
PWM Blank Timer.When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. The blank timer runs after the off time counter to provide the blanking function. The blank timer is reset when ENABLE is chopped or DIR is changed. For external PWM control, a DIR change or ENABLE ON will trigger the blanking function. The duration is adjusted by control input BLANK. BLANK t BLANK 06 / f OSC 1 12/f OSC Synchronous Rectification.Logic high applied to the SR terminal enables synchronous rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off time cycle, load current will recirculate according to the decay mode selected by control logic. The A3936 synchronous rectification feature will turn on the appropriateMOSFET(s)during the current decay and effectively short out the body diodes with the low Rdson driver. This will lower power dissipation significantly and can eliminate the need for external schottky diodes. Reversal of load current is prevented by turning off synchronous rectification when a zero current level is detected. Brake.Logic high to the brake terminal activates the brake function, logic low allows normal operation. Brake will turn all three sink drivers ON and effectively shorts out the motor generated BEMF. It is important to note that the internal PWM current control circuit will not limit the current when braking, since the current does not flow through the sense resistor. The maximum current can be approximated by V BEMF /RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations of high speed and high inertial loads. Oscillator.The PWM timer is based on an internal oscillator set by a resistor connected from the OSC terminal to VDD . Typical value of 4Mhz is set with 51k resistor. FOSC = 204E9/ROSC . Tach. A tachometer signal is available for speed measurement. This open collector output toggles at each Hall transition.
Pin No. Pin Name Pin Description 1G N D 2G N D
3 HA+ Hall input
4 HA- Hall input
5 HB+ Hall input
6 HB- Hall input
7 HC+ Hall input
8 HC- Hall input
9V DD Logic Supply Voltage