DATASHEET SEARCH SITE
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 21
Technical content
Description
The A3930 and A3931 are 3-phase brushless DC (BLDC) motor controllers for use with N-channel external power MOSFETs. They incorporate much of the circuitry required to design a cost effective three-phase motor drive system, and have been specifically designed for automotive applications. A key automotive requirement is functionality over a wide input supply range. A unique charge pump regulator provides adequate (>10 V) gate drive for battery voltages down to 7 V , and allows the device to operate with a reduced gate drive at battery voltages down to 5.5 V . Power dissipation in the charge pump is minimized by switching from a voltage doubling mode at low supply voltage to a dropout mode at the nominal running voltage of 14 V . A bootstrap capacitor is used to provide the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high-side drive allows for DC (100% duty cycle) operation. Internal fixed-frequency PWM current control circuitry can be used to regulate the maximum load current. The peak load current limit is set by the selection of an input reference voltage and external sensing resistor. The PWM frequency is set by a user-selected external RC timing network. For added flexibility, the PWM input can be used to provide speed and 3930-DS Rev. 4 Features and Benefits ▪ High current 3-phase gate drive for N-channel MOSFETs ▪ Synchronous rectification ▪ Cross-conduction protection ▪ Charge pump and top-off charge pump for 100% PWM ▪ Integrated commutation decoder logic ▪ Operation over 5.5 to 50 V supply voltage range ▪ Extensive diagnostics output ▪ Provides +5 V Hall sensor power ▪ Low-current sleep mode Automotive 3-Phase BLDC Controller and MOSFET Driver Typical Application Continued on the next page… Package: 48 Lead LQFP with exposed thermal pad (suffix JP) Approximate Scale 1:1
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 2Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A. torque control, allowing the internal current control circuit to set the maximum current limit. Efficiency is enhanced by using synchronous rectification. The power FETs are protected from shoot-through by integrated crossover control with dead time. The dead time can be set by a single external resistor. The A3930 and A3931 only differ in their response to the all-zero combination on the Hall inputs. In this state, the A3930 indicates a logic fault, but the A3931 pre-positions the motor in an unstable starting position suitable for start-up algorithms in microprocessor- driven “sensor-less” control systems. Both devices are supplied in a 48-pin LQFP with exposed thermal pad. This is a small footprint (81 mm 2) power package, that is lead (Pb) free, with 100% matte tin leadframe plating. Selection Guide Absolute Maximum Ratings Part Number Option Packing Terminals Package A3930KJPTR-T Hall short detection 1500 pieces/reel 48 LQFP surface mount A3931KJPTR-T Pre-positioning 1500 pieces/reel Description (continued) Parameter Symbol Conditions Rating Units Load Supply Voltage V BB VBB pin –0.3 to 50 V Logic Input/Output Voltage VRESET RESET pin input –0.3 to 6 V Remaining logic pins –0.3 to 7 V Output Voltage Range VGHx GHA, GHB, and GHC pins V Sx to VSx+ 15 V VGLx GLA, GLB, and GLC pins –5 to 16 V VCx CA, CB, and CC pins V Sx+ 15 V VSx SA, SB, and SC pins –5 to 55 V CSP, CSN, and LSS pins –4 to 6.5 V CSO, VDSTH pins –0.3 to 6.5 V VDRAIN pin –0.3 to 55 V Operating Temperature Range (K) T A –40 to 150 °C Junction Temperature T J 150 °C Transient Junction Temperature T tJ Overtemperature event not exceed- ing 1 s, lifetime duration not exceed- ing 10 hr; guaranteed by design characterization 175 °C Storage Temperature Range T S –55 to 150 °C ESD Rating, Human Body Model AEC-Q100-002, all pins except CP1 2000 V AEC-Q100-002, pin CP1 1000 V ESD Rating, Charged Device Model AEC-Q100-011, all pins 1050 V
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. P High-Side Drive Low-Side Drive Blanking Charge Pump Regulator Charge Pump Boostrap Monitor +5V Ref OSC R S Q Diagnostics and Protection –UVLO –TSD –Short to Supply –Short to Ground –Shorted Winding –Low Load P RSENSE V5BD CA SA TACHO VBB RC CTRT RDEAD VDRAIN Phase A of three phases VDSTH REF CSOUT Control Logic LSS AGND CSN Pad CSP RESET TEST FF1 PWM FF2 GHA DIR DIRO GLA RGLA RGHA COAST MODE BRAKE CP1CP2 VREG VBAT+ CREG CBOOTA CP VREG ESF CV5 QV5 Functional Block Diagram
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1 Characteristics Symbol Test Conditions Min. Typ. Max. Units Supply and Reference VBB Functional Operating Range6 VBB Function correct, parameters not guaranteed 5.5 – 50 V VBB Quiescent Current IBBQ RESET = High, outputs = Low – 11 14 mA IBBS RESET = Low, sleep mode – – 10 μA V5 Quiescent Current I V5Q RESET = High, outputs = Low – – 5 mA VREG Output Voltage V REG VBB ≥ 7.4 V, IREG = 0 to 15 mA 12.10 13 13.75 V 6 V < VBB < 7.4 V IREG = 0 to 15 mA 2 × VBB –2.7 –– V
5.5 V < VBB < 6 V, IREG < 10 mA 9 10 – V
Bootstrap Diode Forward Voltage V fBOOT ID = 10 mA 0.4 0.7 1.0 V ID = 100 mA 1.5 2.2 2.8 V Bootstrap Diode Resistance r D rD(100 mA) = (VfBOOT(150 mA) – VfBOOT(50 mA)) / 100 mA 61 0 2 0 Ω Bootstrap Diode Current Limit IDBOOT 250 500 750 mA Top-off Charge Pump Current Limit ITOCPM – 200 – μA High-Side Gate Drive Static Load Resistance RGSH 250 – – k Ω V5 Output Voltage V 5 4.75 5 5.25 V VBE of External Transistor QV5 V BEEXT –– 1 V V5BD Base Drive Capability for QV52 I5BD – – –2 mA Gate Output Drive Turn-On Rise Time t r CLOAD = 3300 pF, 20% to 80% points – 60 – ns Turn-Off Fall Time t f CLOAD = 3300 pF, 80% to 20% points – 40 – ns Pull-Up On Resistance R DS(on)UP TJ = 25C, IGHx = –150 mA 3 4 5 Ω TJ = 150C, IGHx = –150 mA 4.6 5.6 6.6 Ω Pull-Down On Resistance R DS(on)DN TJ = 25C, IGLx = 150 mA 1 1.5 2 Ω TJ = 150C, IGLx = 150 mA 1.5 2.3 3 Ω Short-Circuit Current – Source2 ISC(source) TJ = 25C – –500 – mA Short-Circuit Current – Sink I SC(sink) TJ = 25C – 850 – mA GHx Output Voltage V GHx tw < 10 μs Bootstrap capacitor fully charged VCx – 0.2 – – V GLx Output Voltage V GLx VREG – 0.2 –– V Continued on the next page...
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Continued on the next page… Turn-Off Propagation Delay t p(off) From Hall input change to unloaded gate output change 300 500 700 ns From other control input change to unloaded gate output change – 150 200 ns Dead Time (turn-off to turn-on delay) t DEAD RDEAD = 5 kΩ – 180 – ns RDEAD = 50 kΩ 835 960 1090 ns RDEAD = 400 kΩ – 3.3 – μs RDEAD = tied to V5 – 6 – μs Logic Inputs and Outputs FFx Fault Output (Open Drain) V OL IOL = 1 mA, fault asserted – – 0.4 V FFx Fault Output Leakage Current2 IOH VO = 5 V, fault not asserted –1 – 1 μA TACHO and DIRO Output High Voltage V OH IOH = –1 mA V 5 – 1 V – – V TACHO and DIRO Output Low Voltage V OL IOL = 1 mA – – 0.4 V Input Low Voltage V IL – – 0.8 V Input High Voltage (Except RESET) V IH 2– – V RESET Input High Voltage V IHR 2.2 – – V Input Hysteresis V IHys 300 500 – mV Input Current (Except H1, H2, H3, and RESET)2 IIN –1 – 1 μA RESET Input Pull-Down Resistor R PD VIN = 5 V – 50 – k Ω Hx Input Pull-Up Resistor R PU VIN = 0 V – 100 – k Ω Current Sense Differential Amplifier Input Bias Current2 IIBS CSP = CSN = 0 V –250 –200 –150 μA Input Offset Current2 IIOS CSP = CSN = 0 V –10 – 10 μA CSP Input Resistance R CSP Measured with respect to AGND – 80 – k Ω CSN Input Resistance R CSN Measured with respect to AGND – 4 – k Ω Differential Input Voltage V ID VID = CSP – CSN, –1.3 V < CSP < 4 V, –1.3 V < CSN < 4 V 0 – 200 mV Output Offset Voltage V OOS CSP = CSN = 0 V 100 320 550 mV Output Offset Voltage Drift V OOS(∆t) CSP = CSN = 0 V – 100 – μV/°C Input Common Mode Range V CM CSP = CSN –1.5 – 4 V Differential Input Voltage Gain A V 40 mV < VID < 175 mV, VCM in range 18.5 19 19.5 V/V Low Output Voltage Error V err 0 < VID < 40 mV, VCSOUT = (19 × VID) + VOOS + Verr –20 – 20 mV DC Common Mode Gain A CMdc CSP = CSN = 200 mV – –30 – dB Source Resistance r CSOUT VCSOUT = 2 V, –2 mA < ICSOUT < 0.5 mA – 80 – Ω Output Dynamic Range V CSOUT –100 μA < ICSOUT < 100 μA 0.1 – V5 – 0.2 V Output Current – Sink ICSOUT(sink) VCSOUT= 2 V ±5% – 1 – mA Output Current – Source2 ICSOUT(source) VCSOUT= 2 V ±5% – –19 – mA ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1 Characteristics Symbol Test Conditions Min. Typ. Max. Units
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Supply Rejection PSRR CSP = CSN = AGND, 0 to 300 kHz – 45 – dB Small Signal 3 dB Bandwidth Frequency f 3dB VID=10 mVPP – 1.6 – MHz Settling Time t SETTLE To within 10%, VCSOUT = 1 VPP square wave – 400 – ns AC Common Mode Gain A CMac VICR= 250 mVPP, 0 to 1 MHz – –28 – dB Common Mode Recovery Time t CMrec To within 100 mV, VICR= +4.1 to 0 V step –1 – μs Output Slew Rate SR 10% to 90% points, VID= 0 to 175 mV step –2 0 – V / μs Input Overload Recovery Time t IDREC To within 10%, VID=250 mV to 0 V step – 500 – ns Current Limit Reference Comparator Input Offset Voltage V IOC –15 0 15 mV Reference Input Clamp Voltage V REFC External pull-up to 5 V RREF = 200 kΩ 3.75 4 4.2 V Comparator Blank Time tRC RT= 56 kΩ, CT = 470 pF – 650 – ns REF Input Bias Current IIBREF –0 – μA RC Charge Current2 IRC –1.15 –1 –0.85 mA RC HIgh Voltage Threshold V RCH 1.7 1.9 2.1 V RC Low Voltage Threshold V RCL 0.6 0.7 0.8 V Protection VREG Undervoltage Lockout V REGUV VREG rising 7.5 8 8.5 V VREG falling 6.75 7.25 7.75 V Bootstrap Capacitor Undervoltage Lockout V BOOTUV VBOOT falling, VCx – VSx 59 – 69 % Bootstrap Capacitor Undervoltage Lockout Hysteresis VBOOTUVHys VBOOTUVHys = %VREG –1 3 – % V5 Undervoltage Lockout V 5UV V5 falling 3.4 3.65 4.0 V V5 Undervoltage Lockout Hysteresis V 5UVHys 300 400 500 mV VDSTH Input Voltage Range V DSTH 0.3 – 4 V VDSTH Input Current2 IDSTH –1 – 1 μA VDRAIN Input Voltage Range V DRAIN 7V BB 45 V Short-to-Ground Threshold Offset3,5 VSTGO VDSTH > 1 V – ±300 – mV VDSTH ≤ 1 V, 7 V ≤ VDRAIN ≤ 30 V –150 – 150 mV Short-to-Battery Threshold Offset4,5 VSTBO VDSTH > 1 V – ±300 – mV VDSTH ≤ 1 V, 7 V ≤ VDRAIN ≤ 30 V –150 – 150 mV Low Load Current Detection Voltage V CSOL – 500 – mV Overtemperature Flag T JF Temperature increasing – 170 – ºC Overtemperature Flag Hysteresis T JFHys Recovery = TJF – TJFHys –1 5 – º C 1Parameters are tested at 135C. Values at 150C are guaranteed by design or correlation. 2For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 3High side on. As VSX decreases, fault occurs if VBAT – VSX > VSTG . 4Low side on. As VSX increases, fault occurs if VSX – VLSS > VSTB . 5VSTG threshold is VDTSTH + VSTGO. VSTB threshold is VDTSTH + VSTBO . 6Function is correct but parameters not guaranteed above or below general limits (7 to 45 V). ELECTRICAL CHARACTERISTICS (continued) at TJ = –40°C to 150°C, VBB = 7 to 45 V, unless otherwise noted1 Characteristics Symbol Test Conditions Min. Typ. Max. Units
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Thermal Characteristics Power Dissipation versus Ambient Temperature THERMAL CHARACTERISTICS may require derating at maximum conditions, see Applications Information section Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance R θJA 4-layer PCB, based on JEDEC standard 23 ºC/W 2-layer PCB, with 3 in.2 of copper area each side connected by thermal vias 44 ºC/W Die-to-Exposed Pad Thermal Resis- tance RθJP 2 ºC/W *Additional thermal information available on Allegro Web site. 50 75 100 125 15025 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS AMBIENT TEMPERATURE IN °C 6.0 5.0 1.0 2.0 3.0 4.0 R QJA = 23°C/W RQJA = 44°C/W
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Basic Operation The A3930 and A3931 devices provide commutation and current control for 3-phase brushless DC (BLDC) motors with integrated Hall-effect (HE) sensors. The motor current is provided by an external 3-phase N-channel MOSFET bridge which is controlled by the A3930/A3931, using fixed-frequency pulse width modu- lation (PWM). The use of PWM with N-channel MOSFETs provides the most cost-effective solution for a high-efficiency motor drive. The A3930/A3931 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side exter- nal MOSFETs are above 10 V , at supply voltages down to 7 V . For extreme battery voltage drop conditions, functional operation is guaranteed down to 5.5 V but with a reduced gate drive. The A3930/A3931 also decodes the commutation sequence from three HE sensors spaced at 120° in the electrical cycle, and ensure no cross-conduction (shoot through) in the external bridge. Individ- ual pins provide direction, brake and coast control. Motor current can be sensed by a low-value sense resistor, RSENSE, in the ground connection to the bridge, amplified and compared to a reference value. The A3930/A3931 then limits the bridge current on a cycle-by-cycle basis. Bridge current can also be controlled using an external PWM signal with the internal cur- rent control either disabled or used to set the absolute maximum motor current. Specific functions are described more fully in the following sections. Power Supplies Only one power connection is required because all internal circuits are powered by integrated regulators. The main power supply should be connected to VBB through a reverse battery protection circuit. V5 and V5BD A 5 V supply for external pull-up and bias cur- rents is provided by an integrated 5 V regulator controller and an external NPN transistor, QV5. The A3930/A3931 provides the base drive current on the V5BD pin, and the 5 V reference on the V5 pin. This regulator is also used by the internal logic circuits and must always be decoupled by at least a 200 nF capacitor, CV5, between the V5 pin and AGND. For stability, a 100 nF capacitor, C5BD, also should be connected between V5BD and AGND. If an external 5 V supply is not required, the V5BD pin and the V5 pin should be connected together. CP1, CP2, and VREG The gate drive outputs are powered by an internal charge pump, which requires a pump capacitor, typi- cally 470 nF, CP, connected between the CP1 and CP2 pins. The output from the charge pump, 13 V nominal, is used to power each of the three high- and low-side driver pairs and is also available on the VREG pin. A sufficiently large storage capaci- tor, CREG, must be connected to this pin to provide the tran- sient charging current to the low-side drivers. The charge pump also provides the charging current for the bootstrap capacitors, CBOOTx. An additional “top-off” charge pump is provided for each high- side drive which allows the high-side drive to maintain the gate voltage on the external FET indefinitely, ensuring so-called 100% PWM if required. This is a low-current trickle charge pump (< 100 μA typical), and is only operated after a high-side driver has been signaled to turn on. There is a small amount of bias current (< 20 μA) drawn from the Cx pin to operate the floating high-side circuit, and the charge pump simply provides enough drive to ensure that the bootstrap voltage, and hence the gate volt- age, will not droop due to this bias current. The charge required for initial turn-on of the high-side gate is always supplied by bootstrap capacitor charge cycles. Hall Effect Sensor Inputs H1, H2, and H3 Hall-effect sensor inputs are configured for motors with 120° electrically-spaced HE sensors, but may be used for 60° electrical spacing with an external inverter. HE sen- sors usually require an additional pull-up resistor to be connected between the sensor output and 5 V . This 5 V can be provided by the integrated 5 V regulator. HE inputs have a hysteresis of typi- cally 500 mV to reduce the effects of switching noise on the HE connections to the motor. These inputs are also filtered to further reduce the effects of switching noise. The HE inputs are pulled- up to 5 V inside the A3930/A3931 through a high value (100 kΩ typical) resistor in series with a diode. This internal pull-up makes the HE input appear high if the Hall sensor signal is miss- ing, allowing detection of an HE input logic fault. Functional Description
Worcester, Massachusetts 01615-0036 U.S.A. table 2. The inputs can also be driven directly from a microcon- troller or similar external circuit. which should have low-impedance traces to the FET bridge. gate of the high-side FET in the external motor-driving bridge. sponding external FET gate circuit to the respective Sx pin. nections of the high-side FETs, with an independent trace. LSS Low-side return path for discharge of the gate capacitors. FETs through an independent low-impedance trace. hysteresis of 500 mV to improve noise performance. pump stabilizes in approximately 3 ms under nominal conditions. RESET has an internal pull-down resistor, 50 kΩ typical.
10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. FETs and the motor to be protected in case of a short circuit. suitable for motors used in start-stop and positioning applications. table 2. For an unloaded, low-inertia motor, this will also usually breaking torque, when fast decay is used (MODE = 0). BRAKE An active-low input that provides a braking function. circuits the back EMF in the windings, and brakes the motor. ings are shorted with no control over the winding current. PWM control circuit or by external input on the PWM pin. ITRIP = (VREF – VOOS) / (RSENSE × AV) . voltage. RREF should have a value between 20 kΩ and 200 kΩ. OSC ≈ 1 / (RTCT + tBLANK + tDEAD) . where fOSC in the range 20 to 50 kHz.
11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. lator and ensure that the output of the PWM latch is always high. for external PWM: tBLANK (μs) = 2000 × CT (μF) . when using the internal sense amplifier. when the sequence follows table 2 bottom-to-top. the DIRO output will not change. taken follows the states shown in table 1. fault occurs, to prevent damage to components. COAST input and a pull-up resistor to V5.
- Undervoltage VREG supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are sufficiently high before enabling any of the outputs. The undervoltage circuit is active during power-up, and will pull both fault flags low and coast the motor (all gate drives low) until V REG is greater than approximately 8 V . Note that this is sufficient to turn on the external power FETs at a battery voltage as low as 5.5 V , but will not normally provide the rated on-resis- tance of the FET. This could lead to excessive power dissipation in the external FET. Commutation Points TACHO DIRO "Forward" Motor Rotation "Reverse" Motor Rotation
Figure 1. Direction Indication Outputs
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. In addition to a monitor on VREG, the A3930/A3931 also monitors both the bootstrap charge voltage, to ensure sufficient high-side drive, and the 5 V reference voltage at V5, to ensure correct logical operation. If either of these fall below the lock- out voltage level, the fault flags are set.
- Overtemperature This event pulls both fault flags low but does not disable any circuitry. It is left to the user to turn off the device to prevent overtemperature damage to the chip and unpredictable device operation.
- Logic Fault: Hall Invalid The A3930 and the A3931 differ slightly in how they handle error conditions on the Hall inputs, Hx. When all Hx are 1s, both devices evaluate this as an illegal code, and they pull both fault flags, FFx, low and coast the mo- tor. This action can be used, if desired, to disable all FET drives under bridge or motor fault conditions. The Hall logic fault condition is not latched, so if the fault occurs while the motor is running, the external FETs will be reenabled, according to the commutation truth table (table 2), when the Hx inputs become valid. When all Hx are 0s, the A3930 handles this in the same manner as all 1s, described in the preceding paragraph. The A3931, however, evaluates this as a prepositioning code, and does not register it as a fault. The Hx inputs have pull-up resistors to ensure that a fault condi- tion will be indicated in the event of an open connection to a Hall sensor.
- Short to Ground A short from any of the motor phase con- nections to ground is detected by monitoring the voltage across the top FETs in each phase using the appropriate Sx pin and the voltage at VDRAIN. This drain-source voltage is then compared to the voltage on the VDSTH pin. If the drain source voltage exceeds the voltage at the VDSTH pin, FF2 will be pulled low.
- Short to Supply A short from any of the motor phase connec- tions to the battery or VBB connection is detected by monitor- ing the voltage across the bottom FETs in each phase using the appropriate Sx pin and the LSS pin. This drain-source voltage is then compared to the voltage on the VDSTH pin. If the drain source voltage exceeds the voltage at the VDSTH pin, FF2 will be pulled low.
- Shorted Motor Winding A short across the motor phase winding is detected by monitoring the voltage across both the top and bottom FETs in each phase. This fault will pull FF2 low.
- Low Load Current The sense amplifier output is monitored independently to allow detection of a low load current. This can be used to detect if an open load condition is present. If, during a commutation period, the output from the sense amplifier does not go above a minimum value, V CSOL, FF1 will go low. No further action will be taken. Short Fault Operation Because motor capacitance may cause the measured voltages to show a fault as the phase switches, the voltages are not sampled until one t DEAD interval after the exter- nal FET is turned on. If a short circuit fault occurs when ESF = 0, the external FETs are not disabled by the A3930/A3931. Under some conditions, some measure of protection will be provided by the internal cur- rent limit but in many cases, particularly for a short to ground, the current limit will provide no protection for the external FETs. To limit any damage to the external FETs or the motor, the A3930/A3931 can either be fully disabled by the RESET input or all FETs can be switched off by pulling the COAST input low. Alternatively, setting ESF = 1 will allow the A3930/A3931 to dis- able the outputs as soon as the fault is detected. The fault will be latched until any of the following conditions occur: a phase commutation RESET goes low COAST goes low This will allow a running motor to coast to the next phase commutation without the risk of damage to the external power MOSFETs. Low Load Current Fault Operation No action is taken for a low load current condition. If the low load occurs due to an open circuit on a phase connection while the motor is running, the A3930/A3931 will continue to commutate the motor phases according to the commutation truth table, table 2. In some cases, this will allow the motor to continue operating at a much reduced performance. The low load condition is checked during a commutation period and is only flagged at the next com- mutation event. The flag is cleared at the end of any subsequent- commutation period where no low load current fault is detected. If the motor stalls or is stationary, then the remaining phase con- nections will usually be insufficient to start rotating the motor. At start-up or after a reset, the low load condition is flagged until the first time the motor current exceeds the threshold value, V CSOL. This allows detection of a possible open phase from startup, even if the motor is not able to start running. Note that a low load current condition can also exist if the motor being driven has no mechanical load.
13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Table 3. INPUT LOGIC
00111 Fast PWM chop – current decay with opposite of selected drivers ON
01111 Fast Peak current limit – selected drivers ON
10111 Slow PWM chop – current decay with both low-side drivers ON
11111 Slow Peak current limit – selected drivers ON
Table 2. Commutation Truth Table* Table 1. Fault Action Table
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 14Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Power All supply connections to the A3930/A3931 should have capaci- tors mounted between the supply pins and the ground pin. These capacitors will provide the transient currents which occur during switching and decouple any voltage transients on the pin from the main supply. VBB Decouple with at least a 100 nF ceramic capacitor mounted between the VBB pin and the AGND pin. A larger electrolytic capacitor, typically 10 μF, in parallel with the ceramic capacitor is also recommended. VREG Supplies current for the gate-drive circuit. As the gates are driven high, they require current from an external capacitor connected to VREG to support the transients. This capacitor should be placed as close as possible to the VREG pin with the ground connection close to the AGND pin. Its value should be at least 20 times larger than the bootstrap capacitor. The capacitor should have a very low series resistance (ESR) and inductance (ESL) to avoid large voltage drops during the initial transient. The optimum capacitor type is a high quality ceramic such as X7R. However, when the required capacitance is too large, an aluminium electrolytic capacitor may be used, with a smaller ceramic capacitor (≈100 nF) in parallel. V5 When the 5V regulator is used with an external pass transistor to provide power to other circuits, a 10 μF decoupling capacitor should be connected between the V5 pin and AGND as close to the pins as possible. If an electrolytic capacitor is used, then a 100 nF ceramic capacitor should be added in parallel. To improve stability, a 100 nF capacitor also should be connected between the V5BD pin and AGND. If 5V is not required for external circuits, the external pass transistor may be omitted, but in that case, V5 must connected directly to V5BD and decoupled with at least a 220 nF capacitor between V5 and AGND. AGND The A3930/A3931 has a single ground connection at the AGND pin. The design ensures that only the operating current for the controller stage passes through this pin. The charge and discharge current for the external FETs does not pass though this pin. The AGND pin is the ground reference for the current trip threshold, the V DS monitor threshold, and the timing components. It should therefor be kept as quiet as possible. A suggested ground connection scheme is described in the layout section below. Power Dissipation In applications where a high ambient tem- perature is expected the on-chip power dissipation may become a critical factor. Careful attention should be paid to ensure the operating conditions allow the A3930/A3931 to remain in a safe range of junction temperature. The power consumed, P TOT , by the A3930/A3931 can be esti- mated using the following formulas: PTOT = PBIAS + PCPUMP + PSWITCHING , PBIAS = VBB × IBB , where IBB is 3 mA, typical, and PCPUMP = (2 × VBB–VREG) × IAV where VBB < 15 V , or PCPUMP = (VBB–VREG) × IAV where VBB > 15 V , and IAV = QGATE × N × fPWM , PSWITCHING = QGATE × VREG × N × fPWM × Ratio where N = 2 for slow decay, or N = 4 for fast decay, and Ratio = 10 / (RGATE + 10) Bootstrap Capacitors Bootstrap Capacitor Selection The value for CBOOT must be correctly selected to ensure proper operation of the device. If the value is too large, time will be wasted charging the capacitor, resulting in a limit on the maximum duty cycle and PWM frequency. If the value is too small, there can be a large voltage drop at the time when the charge is transferred from C BOOT to the MOSFET gate. To keep the voltage drop small, QBOOT QGATE . A factor of 20 is a reasonable value. To calculate CBOOT, the following formulas can be used: QBOOT = CBOOT × VBOOT , = QGATE × 20, therefore C BOOT = QGATE × 20 / VBOOT The voltage drop on the Cx pin as the MOSFET is being turned on can be approximated by: ΔV = QGATE / CBOOT Bootstrap Charging It is good practice to ensure that the high- side bootstrap capacitor, CBOOT, is completely charged before a Applications Information
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. high-side PWM cycle is requested. The minimum time required to charge the capacitor is approximated by: t CHARGE(min) ≈ CBOOT × ΔV /250 mA At power-on, and when the drivers have been disabled for a long time, the CBOOT may be completely discharged. In these cases, ΔV can be considered to be the full high-side drive voltage, 12 V . Otherwise, ΔV is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the Sx pin is pulled low via a GLx PWM cycle, and current flows from VREG through the internal bootstrap diode circuit to CBOOT. Bootstrap Charge Monitor The A3930 and A3931 provide automatic bootstrap capacitor charge management. The boot- strap capacitor voltage for each phase, V BOOTx , is continuously checked to ensure that it is above the bootstrap undervoltage threshold, V BOOTUV. If VBOOT drops below this threshold, the A3930 and A3931 will turn on the necessary low-side FET until the V BOOT exceeds VBOOTUV plus the hysteresis, VBOOTUVHys . The minimum charge time is typically 7 μs, but may be longer for very large values of the bootstrap capacitor (CBOOT >1000 nF). If VBOOT does not exceed VBOOTUV within approximately 200 μs, an undervoltage fault will be flagged, as shown in table 1. PWM Control The A3930 and A3931 have the flexibility to be used in many different motor control schemes. The internal PWM control can be used to provide fully integrated, closed-loop current control. Alternatively, current-mode or voltage-mode control are possible using external control circuits with either the DIR or the PWM input pins. Internal PWM Control The internal PWM current control function is useful in applications where motor torque control or simple maximum current limitation is required. However, for motor speed control applications, it is usually better to use external PWM control either as a closed- or open-loop system. External PWM Control When external PWM control is used, it is possible to completely disable the internal PWM control circuit by connecting the RC pin to AGND. With the internal control disabled, however, care should be taken to avoid excessive current in the power FETs because the A3930/ A3931 will not limit the current. Short-circuit detection will still be available in case of faults. The output of the sense amplifier is also available, but provision must be made in the external control circuits to ignore (blank) the transients at the switching points. External and Internal Combined PWM Control Where external PWM control is used but current limitation is still required, internal PWM current control can be used at the same time as external PWM control. To do so, usually the internal PWM frequency is set lower than the external PWM frequency. This allows the external PWM signal to dominate and synchronize the internal PWM circuit. It does this by discharging the timing capacitor, CT, when the PWM pin is low. When internal and external PWM control are used together, all control features of the A3930/A3931 are available and active, including: dead time, current comparator, and comparator blanking. PWM Frequency Should be set high enough to avoid any audible noise, but low enough to ensure adequate charging of the boot capacitor, CBOOT. The external resistor RT and capacitor CT, connected in parallel from the RC pin to AGND, set the PWM frequency to approximately: f OSC ≈ 1 / (RTCT + tBLANK + tDEAD) . RT should be in the range of 5 to 400 kΩ. PWM Blank The timing capacitor, CT, also serves as the means to set the blank time duration. tBLANK. At the end of the PWM off-cycle, a high-side gate selected by the commutation logic turns on. At this time, large current transients can occur during the reverse recovery time of the intrinsic source drain body diodes of the external power MOSFETs. To prevent false tripping of the current-sense comparator, the output of the current comparator is ignored during the blank time. The length of t BLANK is different for internal versus external PWM. It is set by the value of the timing capacitor, CT, according to the following formulas: for internal PWM: t BLANK (μs) = 1260 × CT (μF), and for external PWM: tBLANK (μs) = 2000 × CT (μF) . A nominal CT value of 680 pF will give a blanking time of 1.3 μs for external PWM and 860 ns for internal PWM. The user must ensure that C T is large enough to cover the current-spike duration.
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 16Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Note that this blank time is only used to mask the internal cur- rent comparator. If the current sense amplifier output, CSOUT, is being used in an external PWM control circuit, then it will be necessary to externally generate a blank time for that control loop. Dead Time The potential for cross-conduction occurs with synchronous rectification, direction changes, PWM, or after a bootstrap capacitor charging cycle. To prevent cross-conduction in any phase of the power FET bridge, it is necessary to have a dead-time delay, t DEAD, between a high- or low-side turn-off and the next turn-on event. tDEAD is in the range of between 96 ns and 6.3 μs, and is set by the value of a resistor, RDEAD, between the RDEAD pin and the GND pin. The maximum dead time of typi- cally 6μs can be set by leaving the RDEAD pin unconnected, or connected to the V5 pin. At 25°C, the value of t DEAD (μs) can be approximated by: tDEAD(nom) ≈ 0.1 + 33 / (5 + IDEAD), IDEAD = 2000 / RDEAD where IDEAD is in μA, and RDEAD is between 5 and 400 kΩ. The greatest accuracy is obtained with values of RDEAD between 10 and 100 kΩ. The choice of power MOSFET and external series gate resistance determines the selection of RDEAD. The dead time should be made long enough to cover the variation of the MOSFET gate capacitance and the tolerances of the series gate resistance, both external and internal to the A3930/A3931. Synchronous Rectification To reduce power dissipation in the external MOSFETs, the A3930/A3931 control logic turns on the appropriate low-side and high-side driver during the load current recirculation PWM-off cycle. Synchronous rectification allows current to flow through the FET selected by the MODE pin setting during the decay time, rather than through the source- drain body diode. The body diodes of the recirculating power FETs conduct only during the dead time that occurs at each PWM transition. For internal current control using fast decay mode, reversal of load current is prevented by turning off synchronous rectification when a zero current level is detected. For external PWM control using fast decay mode, the load current will not be limited to zero but will rise to the set current limit in the reverse direction before disabling synchronous rectification. Braking. The A3930 and A3931 provide dynamic braking by forcing all low-side MOSFETs on, and all high-side MOSFETs off. This effectively short-circuits the back EMF of the motor, which forces a reverse current in the windings, and creating a breaking torque. During braking, the load current can be approximated by: I BRAKE ≈ VBEMF / RLOAD Because the load current does not flow through the sense resistor, RSENSE, during a dynamic brake, care must be taken to ensure that the power MOSFET maximum ratings are not exceeded. It is possible to apply a PWM signal to the BRAKE input to limit the motor braking current. However, because there is no measurement of this current, the PWM duty cycle must be determined for each set of conditions. Typically the duty cycle of such a brake PWM input would start at a value which limits the current and then drops to 0%, that is, BRAKE goes to low, to hold the motor stationary. Setting RESET = 1 and COAST = 0 overrides BRAKE and turns all motor bridge FETs off, coasting the motor. Driving a Full-Bridge. The A3930 and A3931 may be used to drive a full-bridge (for example, a brush DC motor load) by hard-wiring a single state for the Hall inputs and leaving the corresponding phase driver outputs floating. For example, with a configuration of H1 = H2 = 1, and H3 = 0, the outputs CC, GHC, SC, and GLC would be floated, according to the commutation truth table, table3, which indicates a state of high-impedence (Z) for SC with that Hall input configuration. The DIR input controls the motor rotation, while the PWM and MODE inputs control the motor current behavior, as described in the input logic table, table 3.Figure 2. Internal PWM RC Timing VRCH RC VRCL tRC tBLANK tOSC GHx GLx Current Trip Points tDEAD tDEAD Note: For reasons of clarity, t DEAD is shown exaggerated.
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 17Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Circuit Layout Because this is a switch-mode application, where rapid current changes are present, care must be taken during layout of the application PCB. The following points are provided as guidance for layout (refer to figure 3). Following all guidelines will not always be possible. However, each point should be carefully considered as part of any layout procedure. Ground connection layout recommendations: 1. Sensitive connections such as RDEAD and VDSTH, which have very little ground current, should be referenced to the Quiet ground, which is connected independently closest to the AGND pin. The components associated with these sensi- tive pins should never be connected directly to the Supply common or to the Power ground; they must be referenced directly to the AGND pin. 2. Supply decoupling for the supply pins VBB, VREG, and V5 should be connected to Controller Supply ground, which is connected independently, close to the AGND pin. The decoupling capacitors should also be connected as close as possible to the corresponding supply pin. 3. The oscillator timing components can be connected to Quiet ground or Controller Supply ground. They should not be connected to the Supply common or the Power ground. 4. The exposed thermal pad on the package should be con- nected to the AGND pin and may form part of the Controller Supply ground. 5. If the layout space is limited, then the Quiet ground and the Controller Supply ground may be combined, provided that the ground return of the dead-time resistor, RDEAD, is close to the AGND pin. 6. The AGND pin should be connected by an independent low impedance trace to the Supply common at a single point. 7. Check the peak voltage excursion of the transients on the LSS pin with reference to the AGND pin using a close- grounded (tip and barrel) probe. If the voltage at LSS exceeds the absolute maximum specified in this datasheet, add additional clamping, capacitance or both between the LSS pin and the AGND pin. Other layout recommendations: 1. Gate charge drive paths and gate discharge return paths may carry large transient current pulses. Therefore, the traces from GHx, GLx, Sx, and LSS should be as short as possible to reduce the inductance of the circuit trace. 2. Provide an independent connection from LSS to the common point of the power bridge. It is not recommended to connect LSS directly to the AGND pin, as this may inject noise into sensitive functions such as the dead-timer. The LSS connec- tion should not be used for the CSP connection. 3. The inputs to the sense amplifier, CSP and CSN, should be independent traces and for best results should be matched in length and route. 4. Minimize stray inductance by using short, wide copper runs at the drain and source terminals of all power FETs. This includes motor lead connections, the input power bus, and the common source of the low-side power FETs. This will minimize voltages induced by fast switching of large load currents. 5. Consider the use of small (100 nF) ceramic decoupling capacitors across the source and drain of the power FETs
18Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A.
- Ensure that the TEST pin is connected to AGND. This pin is
used for production test only.
150 A, and each design should be tested at the maximum current,
to ensure any parasitic effects are eliminated. Figure 3. Supply and Ground Connections
19Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A.
6 V 6 V
Figure 4. Input and Output Structures
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 20Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Pin-out Diagrams Bootstrapped High-Side Drives Hall Control Logic Current SenseCharge Pump Low Side Drives RDEAD TEST RC MODE PWM NC AGND CP1 CP2 DIRO VBB COAST NC NC LSS NC ESF VREG FF2 FF1 TACHO BRAKE DIR RESET NC V5BD GHA SA CB GHB SB CC GHC SC GLB GLA GLC CA CSP CSN REF CSOUT VDSTH VDRAIN Number Name Description 1 N.C. No connection
2 RESET Control for sleep mode
3 V5BD 5V regulator base drive
4 V5 5V regulator reference
5 FF2 Fault flag 2
6 FF1 Fault flag 1
7 TACHO Speed output
8 BRAKE Brake input
9 DIR Direction control input
10 H1 Hall sensor input
11 H2 Hall sensor input
12 H3 Hall sensor input
13 N.C. No connection
14 PWM Control input
15 MODE Decay control input
16 RC PWM oscillator control input
17 TEST Test pin; tie to AGND
18 RDEAD Dead time setting
19 CSOUT Current sense output
20 REF Current limit setting
21 CSN Current sense input –
22 CSP Current sense input +
23 VDSTH Fault threshold voltage
24 VDRAIN High-side drain voltage sense
25 SC Motor connection phase C
26 GHC High-side gate drive phase C
27 CC Bootstrap capacitor phase C
28 SB Motor connection phase B
29 GHB High-side gate drive phase B
30 CB Bootstrap capacitor phase B
31 SA Motor connection phase A
32 GHA High-side gate drive phase A
33 CA Bootstrap capacitor phase A
34 GLC Low-side gate drive phase C
35 GLB Low-side gate drive phase B
36 GLA Low-side gate drive phase A
37 N.C. No connection
38 LSS Low-side source
39 ESF Enable stop on fault input
40 VREG Gate drive supply output
41 AGND Analog ground
42 CP1 Pump capacitor
43 CP2 Pump capacitor
44 DIRO Direction output
45 VBB Supply voltage
46 COAST Coast input
47 N.C. No connection 48 N.C. No connection – Pad Thermal dissipation, tie to AGND Terminal List Table
Automotive 3-Phase BLDC Controller and MOSFET Driver A3930 and A3931 21Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Package JP, 48-pin LQFP with Exposed Thermal Pad Copyright ©2006-2010, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com A Exposed thermal pad (bottom surface) Terminal #1 mark area B B A CSEATING PLANEC0.08 48X GAGE PLANE SEATING PLANE
1.60 MAX
0.50 5.00 8.60 0.30 1.70 8.60 5.00 For Reference Only (reference JEDEC MS-026 BBCHD) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown1.40 ±0.05 0.10 ±0.05 0.22 ±0.05 9.00 ±0.20 7.00 ±0.20 0.50 PCB Layout Reference ViewC 0.25 (1.00) 0.60 ±0.15 4° ±4 0.15 +0.05 –0.06 5.00±0.04 5.00±0.04 C Reference land pattern layout (reference IPC7351 QFP50P900X900X160-48M); adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C