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Description

The A3910 is a dual half bridge motor driver, designed for low cost, low voltage battery operated power applications. The outputs are rated for operation up to 500 mA. Direct control of high- and low-side drivers is implemented to allow either high-side or low-side PWM. The motor can be connected to either supply or GND. Using a MOS switch results in improved braking action for the motor, compared to implementation with simple clamp diode. The A3910 is supplied in a 2 mm × 2 mm 8-contact DFN package (EE) with exposed thermal pad. The package is lead (Pb) free, with 100% matte tin leadframe plating. A3910-DS Features and Benefits

  • Low RDS(on) outputs
  • Standby mode with zero current drain
  • Small 2 × 2 DFN package
  • Crossover Current protection
  • Thermal Shutdown protection Dual Half Bridge Motor Driver Package: 8-contact DFN with Exposed Thermal Pad (suffix EE) Typical Application Diagram Not to scale A3910 VSUPPLY A3910System Controller M M VSUPPLY A3910System Controller M M (A) Connection to Supply (B) Connection to Ground

Dual Half Bridge Motor DriverA3910 2Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. Pin-out Diagram Absolute Maximum Ratings* Characteristic Symbol Notes Rating Unit Supply Voltage V BB –0.3 to 5.5 V Logic Input Voltage Range V IN –0.3 to 6 V Output Current I OUT 500 mA Output Voltage V OUT –0.3 to VBB + 1 V Operating Ambient Temperature T A E temperature range –40 to 85 ºC Maximum Junction Temperature T J(max) 150 ºC Storage Temperature T stg –55 to 150 ºC Terminal List Table Number Name Function

1 HIN1 Logic input

2 LIN1 Logic input

3 LIN2 Logic input

4 HIN2 Logic input

5 OUT2 Motor terminal

6 GND Ground

7 VBB Input Supply

8 OUT1 Motor terminal

Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Unit Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 49 ºC/W On 2-layer PCB based with 0.23 in.2 exposed copper each side 92 ºC/W *Additional thermal information available on the Allegro website. Selection Guide Part Number Packing* Package A3910EEETR-T 3000 pieces per 13-in. reel 8-contact DFN with exposed thermal pad *Contact Allegro™ for additional packing options. HIN1 LIN1 LIN2 HIN2 OUT1 VBB GND OUT2 PAD

Dual Half Bridge Motor DriverA3910 3Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. GND (Option: VBB or GND) OUT1 VBB HIN1 LIN1 VIN = 3 V typ TSD TSD OUT2 Gate Drive Disable Disable Sleep Mode VBB Gate Drive Supply HIN2 LIN2 VBB VBB VBB Functional Block Diagram

Dual Half Bridge Motor DriverA3910 4Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Logic Table HINx LINx OUTx Function Motor to Supply Function Motor to GND 0 0 Hi-Z 1 Coast (Sleep2) Coast (Sleep 2) 1 0 High Brake Drive 0 1 Low Drive Brake 1 1 Hi-Z

1 Coast Coast

1Hi-Z is high impedance. 2Sleep mode activated by all four inputs <100 mV. ELECTRICAL CHARACTERISTICS* Valid at TA = 25°C; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit VBB Supply Range V BB 2.5 – 5.5 V VBB Supply Current I BB Both bridges, PWM = 50 kHz – 0.3 1 mA Sleep mode (HIN1 = HIN2 = LIN1 = LIN2 = 0 V) – <1 1 μA Output Driver On-Resistance R DS(on) Source driver, I = 400 mA, VBB = 3 V – 1.1 1.4 Ω Source driver, I = 400 mA, VBB = 5 V – 0.8 1 Ω Sink driver, I = 400 mA, VBB = 3 V – 0.5 0.65 Ω Sink driver, I = 400 mA, VBB = 5 V – 0.4 0.52 Ω Input Logic Low Level V IL – – 0.5 V Input Logic High Level V IH V BB / 2 – – V Input Hysteresis V HYS 50 150 300 mV Logic Input Current I IN VIN = 3.3 V (Pulldown = 100 kΩ) – 33 50 μA Thermal Shutdown Temperature T JTSD Temperature increasing – 165 – °C Thermal Shutdown Hysteresis ΔTJ Recovery = TJTSD – ΔTJ – 15 – °C *Specified limits are tested at a single temperature and assured over operating temperature range by design and characterization.

Dual Half Bridge Motor DriverA3910 5Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Characteristic Performance 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 RDS(on) (Ω) VBB (V) Output On-Resistance versus Load Supply Voltage Source = 500 mA Source = 100 mA Sink = 500 mA Sink = 100 mA 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 100 200 300 400 500 IOUT (mA) Output On-Resistance versus Output Current Source = 3 V Source = 5 V Sink =3 V Sink = 5 V RDS(on) (Ω)

Dual Half Bridge Motor DriverA3910 6Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package EE, 8-Contact DFN with Exposed Thermal Pad 1.60 A A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) For reference only (DWG-2857), not for tooling use (reference JEDEC MO-229UCCD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown C Reference land pattern layout (reference IPC7351 SON50P200X200X100-9M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) B PCB Layout Reference View 0.90 1.60 0.30 8 0.50 0.83 2.13 C 0.90 0.55 +0.05 –0.04 2.00 ±0.15 2.00 ±0.15 0.25 ±0.05 0.325 ±0.050 0.50 C0.08 D D Coplanarity includes exposed thermal pad and terminals CSEATING PLANE

Dual Half Bridge Motor DriverA3910 7Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Copyright ©2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com