A3901 ALLEGRO
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Dual Full Bridge Low Voltage Motor DriverA3901 2Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Parameter Symbol Conditions Min. Typ. Max. Units Load Supply Voltage V BB ––7V Output Current per Channel* IOUT – – 400 mA Logic Input Voltage Range V IN –0.3 – 6 V Junction Temperature T J – – 150 °C Storage Temperature Range T S –40 – 150 °C Operating Temperature Range T A –20 – 85 °C *Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Selection Guide Part Number Packing A3901SEJTR-T Tape and reel, 1500 pieces/reel Absolute Maximum Ratings
Dual Full Bridge Low Voltage Motor DriverA3901 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Control Logic and Gate Drive TSD IN1 IN2 IN3 IN4 VBB GND OUT1 OUT2 BRIDGE1 BRIDGE2 OUT3 OUT4 PAD 10 µF 10 V Functional Block Diagram OUT1 OUT2 VBBPAD OUT3 OUT4 IN1 IN2 GND IN3 IN4 Terminal Diagram Number Name Description
1 IN1 Logic input 1
2 IN2 Logic input 2
3 GND Ground terminal
4 IN3 Logic input 3
5 IN4 Logic input 4
6 OUT4 Bridge2 output to load
7 OUT3 Bridge2 output to load
8 VBB Load supply terminal
9 OUT2 Bridge1 output to load
10 OUT1 Bridge1 output to load
– Pad Exposed pad for thermal dissipation; connect to GND externally
Dual Full Bridge Low Voltage Motor DriverA3901 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com ELECTRICAL CHARACTERISTICS at TA =25°C, and VBB = 2.5 to 5.5 V, unless noted otherwise Characteristics Symbol Test Conditions Min. Typ. Max. Units Output On Resistance R DS(on) Source driver, VBB = 3 V, IOUT = 300 mA – 1.8 2.1 Ω Source driver, VBB = 5 V, IOUT = 300 mA – 1.2 1.4 Ω Sink driver, VBB = 3 V, IOUT = 300 mA – 1.2 1.4 Ω Sink driver, VBB = 5 V, IOUT = 300 mA – 0.8 1.0 Ω Clamp Diode I = 300 mA – – 1.5 V Motor Supply Current I BB All outputs PWMed at 20 kHz – 0.6 – mA Sleep mode, VBB= 3 V – – 100 nA Sleep mode, VBB= 5 V – <50 500 nA Logic Input Voltage VIN(1) VBB/2 – – V VIN(0) – – 0.5 V Logic Input Current IIN(1) VIN = 2.0 V – <100 500 nA IIN(0) VIN = 0.5 V – <–100 –500 nA Input Voltage Hysteresis V hys – 150 – mV Propagation Delay tpd(on) Input Low to Sink On, Input High to Source On – 130 – ns tpd(off) Input High to Sink Off, Input Low to Source Off – 50 – ns Crossover Delay t COD –8 0–n s Thermal Shut Down Temperature T J – 150 – °C Thermal Shut Down Hysteresis T Jhys –1 0–° C THERMAL CHARACTERISTICS Characteristics Symbol Test Conditions Rating Unit Package Thermal Resistance* RθJA Measured on 4-layer board based on JEDEC standard 45 °C/W Measured on 2-layer board with copper limited to solder pads and 0.88 in2. of copper on each side 65 °C/W *Additional thermal information is available on the Allegro Web site.
Dual Full Bridge Low Voltage Motor DriverA3901 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Motor Operation Truth Table INx1 OUT12 OUT2 OUT3 OUT4 Function Stepper Motor IN1 IN2 IN3 IN4 Full Stepping Half-Stepping 0 0 0 0 OFF OFF OFF OFF Sleep Mode Sleep Mode 1 0 1 0 H L H L Step 1 Step 1 0 0 1 0 OFF OFF H L – Step 2 0 1 1 0 L H H L Step 2 Step 3 0 1 0 0 L H OFF OFF – Step 4 0 1 0 1 L H L H Step 3 Step 5 0 0 0 1 OFF OFF L H – Step 6 1 0 0 1 H L L H Step 4 Step 7 1 0 0 0 H L OFF OFF – Step 8 DC Motor (Dual) IN1 or IN3 IN2 or IN4 0 0 OFF OFF OFF OFF Hi-Z (Sleep Mode)/Coast 1 0 H L H L Forward 0 1 L H L H Reverse 1 1 L L L L Brake DC Motor (Single, Paralleled) IN1 and IN3 IN2 and IN4 0 0 OFF OFF OFF OFF Hi-Z (Sleep Mode)/Coast 1 0 H L H L Forward 0 1 L H L H Reverse 1 1 L L L L Brake DC Motor (External PWM) IN1 or IN3 IN2 or IN4 H OFF L OFF H OFF L OFF Forward Fast Decay L OFF H OFF L OFF H OFF Reverse Fast Decay H L L L H L L L Forward Slow Decay L L H L L L H L Reverse Slow Decay 10 = logic low, VINx< VIN(0)(max); 1 = logic high, VINx> VIN(1)(min) 2H = voltage high, source driver on; L = voltage low, sink driver on
Dual Full Bridge Low Voltage Motor DriverA3901 6Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 0.50 1.00 1.50 2.50 2.00 3.00 3.50 4.00 0.50 1.00 1.50 2.50 2.00 3.00 3.50 4.00 100 150 200 250 300 350 400 0.50 1.00 1.50 2.00 2.50 3.50 3.00 0.50 1.00 1.50 2.00 2.50 3.50 3.00 100 150 200 250 300 350 400 Output On Resistance versus Load Supply Voltage IOUT = 100 mA Output On Resistance versus Load Supply Voltage IOUT = 300 mA Output On Resistance versus Output Current VBB = 3 V Output On Resistance versus Output Current VBB = 5 V RDS(on) (Ω) RDS(on) (Ω) VBB (V)VBB (V) VBB (V)VBB (V) RDS(on) (Ω) RDS(on) (Ω) Source Sink Total Source Sink Total Source Sink Total Source Sink Total Characteristic Performance
Dual Full Bridge Low Voltage Motor DriverA3901 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Functional Description Device Operation. The A3901 is a dual full-bridge low voltage motor driver capable of operating one stepper motor or up to two dc motors. MOSFET output stages substantially reduce the voltage drop and the power dissipation of the outputs of the A3901 compared to typical drivers with bipolar transistors. Internal circuit protection includes thermal shutdown with hysteresis, clamp diodes, and crossover current protection. The A3901 is designed for portable applications with a power-off (Sleep mode) current of 50 nA typical, and an operating voltage of 2.5 to 5.5 V . The A3901 logic inputs are 3 to 5 V logic compatible. Output current can be regulated by pulse width modu- lating (PWM) the inputs. The full-bridge outputs can be paralleled for higher-current applications (see figure 6). In conditions where the logic supply voltage drops below 2.5 V , both the sink and the source R DS(on) will increase beyond the specified values. In extreme cases, no power will be delivered to the motor(s). However, the device will not be damaged. In stepping operation, the device can drive in either full- or half-step mode. The stepping mode is set by the signal pattern on the INx terminals, as shown in the stepping timing diagrams. External PWM. Pulse width modulating the inputs allows the output current to be regulated. Slow decay mode is achieved by holding one input high while PWMing the other input. Holding one input low and PWMing the other input results in fast decay. See the External PWM diagram. Sleep Mode. Pulling all inputs to 0.5 V or less, sends the A3901 into Sleep mode, during which it draws 50 nA typical. Thermal Shutdown. The A3901 will disable the outputs if the junction temperature reaches 165°C. When thermal shutdown is entered, after the junction temperature drops 15°C, the outputs will be re-en- abled. Brake Mode. When driving dc motors, the A3901 will go into Brake mode (turn on both sink drivers) when all inputs, INx, are logic 1. There is no protec- tion during braking, so care must be taken to ensure that the peak current during braking does not exceed the absolute maximum current.
Dual Full Bridge Low Voltage Motor DriverA3901 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
Application Information
+VBB/Rmotor –VBB/Rmotor +VBB/Rmotor –VBB/Rmotor IN1 IN2 IN3 IN4 IOUT1-2 IOUT3-4 +VBB/Rmotor –VBB/Rmotor +VBB/Rmotor –VBB/Rmotor Figure 4a. Typical stepper motor control application Figure 4c. Half step mode timing chart IN1 CONT ROL LOGIC/ GATE DRIVE TSD VBB IN2 GND IN3 IN4 OUT1 OUT2 OUT3 VBB OUT4 Stepper Motor 10 µF/10 V Figure 4b. Full step mode timing chart
Figure 5. Typical dual dc motor control application. Either IN1 or IN2 can be used to drive OUT1 and OUT2. Either IN3 or IN4 can be used to drive OUT3 and OUT4. Figure 6. Typical single dc motor control (paralleled outputs)
10Allegro MicroSystems, Inc. Figure 7. Typical dual dc motor control application Figure 8. External PWM current control in fast and slow decay modes
Dual Full Bridge Low Voltage Motor DriverA3901 11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. Copyright©2005, 2006 Allegro MicroSystems, Inc. Package EJ, 10-contact DFN/MLP 1.64 NOM .065 2.38 NOM .094 0.30 0.18 .012 .007 0.50 0.30 .020 .012 1.64 NOM .065 2.90 NOM .114 0.30 NOM .012 0.50 NOM .0200.85 NOM .033 2.38 NOM .094 0.80 0.70 .031 .028 0.05 0.00 .002 .000 3.15 2.85 .124 .112 3.15 2.85 .124 .112 0.20 REF .008 A B CSEATING PLANEC0.08 [.003] 10X 0.50 .020 10X 0.10 [.004] M C A B 0.05 [.002] M C 0.20±0.05 MIN .008±.002 A C A T erminal #1 mark area B Exposed thermal pad (reference dimensions only, terminal #1 identifier appearance at supplier discretion) Preliminary dimensions, for reference only (reference JEDEC MO-229 WEED) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown C Reference pad layout (reference IPC7351 SON50P300X300-11WEED3N); adjust as necessary to meet application process requirements; when mounted on multilayer PCBs, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) B 0.225 x 0.225 REF .009 x .009