A2550

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Large numbers of relay-based applications require the use of a microprocessor which implements complex system control. In these systems, there is the need for microprocessor logic supply voltage, power-on reset circuitry, and watchdog capabilities. The Allegro ® A2550 combines the functions of voltage regulator, watchdog, and reset, as well as three low-side DMOS relay driver outputs. Primarily targeted at automotive applications, this IC is designed to provide robust performance over extended voltage and temperature ranges. Three low-side DMOS drivers can drive inductive loads, such as relay coils. Each driver integrates rugged voltage clamps which survive automotive load dump pulses up to 48 V . The

40 V rating on VBB also ensures adequate survival in harsh

automotive environments. A 5 V linear regulator provides 40 mA of output current, with a tolerance of 2% over the operating temperature range. To enhance the usefulness of the IC in automotive applications, the 5 V regulator output, as well as the three low-side driver outputs are protected against overcurrent conditions. 2550-DS, Rev. 4 Features and Benefits ▪ Three independent low-side DMOS output drivers ▪ Short-circuit protection of drivers ▪ Eliminates need for flyback diodes on relays ▪ Thermal shutdown ▪ Separate precision 5 V regulator (2%) ▪ Current clamp on 5 V regulator ▪ 16-pin TSSOP package with exposed thermal pad ▪ Programmable reset (NPOR) delay time ▪ Programmable watchdog ▪ Automotive voltage and temperature ranges ▪ Active clamps for automotive load dump specifications ▪ Lead (Pb) free Relay Driver with 5 V Regulator for Automotive Applications Continued on the next page… Package: 16 pin TSSOP (suffix LP) with exposed pad Typical Application Approximate Scale A2550 OUT1 OUT2 OUT3 PGND CWD CPOR ENBAT VBB IN1 IN2 IN3 LGND NPOR WDI EN VREG5 A2550System Logic Relays or other inductive loads 0.47 μF X7R

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 2Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A. The A2550 also includes power-on reset circuitry (NPOR) as well as an integrated watchdog circuit. Combined, they service the monitoring and reset requirements of a system microprocessor. The A2550 is supplied in a 16-pin TSSOP package with exposed thermal pad (package LP).The package is lead (Pb) free, with 100% matte tin leadframe plating. Description (continued) Selection Guide Part Number Packing A2550KLPTR-T 13-in. reel, 4000 pieces / reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Supply Voltage V BB –0.3 to 60 V High Voltage Enable V ENBAT –0.3 to 60 V Output Driver V OUT Continuous rating; outputs off –1.4 to 48 V Output Load Clamp V OUT(CL) Transient rating 60 V Maximum Energy at Outputs E OUT Single Pulse, TJ(initial) = 125°C 100 mJ Peak Power Dissipation at Outputs P PK Single pulse, TJ(initial) = 125°C, ∆t = 1 ms; see figure 2 for different durations and TJ(initial) 1.7 W All other pins –0.3 to 7 V ESD Rating – Human Body Model AEC-Q100-002; all pins 2.5 kV ESD Rating – Charged Device Model AEC-Q100-011; all pins 1050 V Operating Ambient Temperature T A Range K –40 to 125 ºC Maximum Junction Temperature T J (max) 150 ºC Storage Temperature T stg –55 to 150 ºC

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 3Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Functional Block Diagram Component Selection Table Name Suitable Characteristics Representative Device CBB 33 μF, 63 V electrolytic United Chemi-Con EGXE630E--330MH12D CREG5 0.47 μF, 25 V, X7R ceramic CWD, CPOR 0.22 μF, 16 V, X7R ceramic NPOR Adjustable Delay Linear Regulator VREG5 Internal Reference Vref VREG5 UVLO Enable OUT1 VBB Micro Controller Hi-V Enable VBAT Vdc Coil 1 LGND WDI ENBAT EN IN2 IN1 200 k7 CBB TSD CPOR Watchdog TSD CWD CREG5 0.47 μF X7R A2550 Coil 2 Coil 3 Relays or Other Inductive Loads Hi-V Protection PGND IN3 200 k7 200 k7 Overcurrent Protection Overcurrent Protection Overcurrent Protection OUT3 OUT2 Fault Logic LGND and PGND must be connected externally. A A

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 4Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS, –40°C ≤ TJ ≤ 150°C, VBB within operating limits, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Units Supply VBB Operating Voltage1 VBB 7 – 40 V VBB Supply Current IBBQ All OUTx Off; EN = 5 V, VBB = ENBAT = 14 V – – 4 mA IBB All OUTx On; EN = 5 V, VBB = ENBAT= 14 V – – 5 mA IBBS Sleep mode, EN = ENBAT = 0 – – 10 μA Logic Inputs ENBAT Input Voltage2 VENBAT HIGH input level 3.5 – V BB V LOW input level 0 – 1.5 V EN, WDI, and INx Input Voltage VIH HIGH input level 3.5 – 5.5 V VIL LOW input level 0 – 1.5 V ENBAT, EN, WDI, INx Input Voltage Hysteresis VIhys 200 – – mV ENBAT Input Current2,3 IENBAT HIGH input level, VBB = VBB(max) – – 400 μA HIGH input level, VBB = 14 V – – 70 μA LOW input level –50 – 10 μA EN Input Current2 IEN HIGH input level – – 50 μA LOW input level –50 – 10 μA WDI Input Current2 IWDI HIGH input level – – 50 μA LOW input level –10 – 10 μA INx Input Current2 IINx HIGH input level – – 50 μA LOW input level –10 – 10 μA Drivers Propagation Delays tp(ON) INx change to unloaded output change – 1 2 μs tp(OFF) INx change to unloaded output change – 0.5 1 μs Driver On-Resistance R DS(on) IOUTx = 250 mA, VBB = 14 V – – 5 Ω IOUTx = 250 mA, VBB = 9 V – – 5.5 Ω IOUTx = 250 mA, VBB = 7 V – – 6 Ω Driver Leakage Current I DSS VOUTx = 40 V – – 10 μA Diode Forward Voltage V F IOUTx = –250 mA – –1.3 –1.4 V Output Clamp Voltage V CL IOUTx = 100 μA 50 – 60 V Low-Side Driver Overcurrent (O.C.) Threshold IOUT(OC) 275 – 500 mA Blanking Time Before Overcurrent Detect t BLANK IOUT = 500 mA 2 – 20 μs Regulator Voltage Regulator Output Voltage V REG5 CREG5 ≥ 0.47 μF (X7R Ceramic, ESR ≤ 0. 5Ω), 1 mA ≤ IREG5 ≤ 40 mA 4.9 5.0 5.1 V Pass Transistor On-Resistance1 RREG5 IREG5 = 40 mA – – 55 Ω Line Regulation Voltage V LNR IREG5 = 1 mA – – 20 mV Load Regulation Voltage V LDR 1 mA ≤ IREG5 ≤ 40 mA, VBB = 7 V – – 100 mV 1 mA ≤ IREG5 ≤ 40 mA, VBB ≥ 9 V – – 40 mV Current Limit Level4 IREG5Lim VREG5 = 4.63 V, VBB = 7 V 40 – 150 mA VREG5 = 4.63 V, VBB ≥ 9 V 65 – 200 mA VREG5 = 0 V 65 – 200 mA Under Voltage Lockout Threshold V UVREG5 VREG5 falling 4.25 4.38 4.63 V VREG5 rising 4.36 4.50 4.75 V Under Voltage Lockout Hysteresis V UVREG5hys – 0.12 – V Continued on the next page...

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 5Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. ELECTRICAL CHARACTERISTICS, continued –40°C ≤ TJ ≤ 150°C, VBB within operating limits, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Units Watchdog and Power-On Reset NPOR Active Voltage V NPOR INPOR = 1 mA; VREG5 = 1.5 V; 1.5 V ≤ VBB ≤ 40 V – – 400 mV NPOR Inactive Leakage Current I NPOR(Off) VNPOR = 5 V – – 10 μA CWD and CPOR Trip Voltage VTRIP(H) VTRIP(H) = VREF – 1.2 – V VTRIP(L) – 0.2 – V CPOR Charge Current I POR 2.5 5 7.5 μA Power-On Reset Cycle Time5 tPOR CPOR = 0.22 μF – 44 – ms CWD Charge Current I CWD Charging 2.5 5 7.5 μA Discharging – 70 – μA Thermal Protection Thermal Shut Down Threshold T TSD 150 175 – °C Thermal Shut Down Hysteresis T TSDhys –1 5–° C 1See Applications Information section for operation with VBB < 7 V. For VBB > 24 V, thermal constraints limit regulator current. 2For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 3When VENBAT exceeds VBB it is clamped with a diode. (VENBAT – VBB) ≤ 1.2 V at 40 mA. 4Defined as the maximum current level allowed during excessive load condition. 5See Applications Information section for calculations. Values guaranteed by design, and depend on capacitor tolerances. Characteristic Symbol Test Conditions* Value Units Thermal Resistance, Junction to Pad R θJP 2 ºC/W Thermal Resistance, Junction to Ambient RθJA 4-layer PCB based on JEDEC standard 34 ºC/W 2-layer PCB with 2 in.2 copper both sides 44 ºC/W Maximum Allowable Power Dissipation P D RθJA = 44 ºC/W (estimated), 2-layer PCB with 2.0 in.2 of 2 oz. copper, TA = 125°C 0.57 W RθJA = 44 ºC/W (estimated), 2-layer PCB with 2.0 in.2 of 2 oz. copper, TA = 85°C 1.48 W *Additional thermal data available on the Allegro Web site. THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Worcester, Massachusetts 01615-0036 U.S.A. Figure 1. Dynamic thermal impedance of an individual output stage during active clamp of an inductive load (mounted on a 4-layer PCB based on JEDEC standard). Figure 2. Peak power dissipation curves for nonrepetitive clamped outputs. Output voltage is clamped during turn-off of inductive loads while current decays.

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 7Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. Pin Descriptions EN Enable pin; logical OR with ENBAT. This logic-level input enables the A2550. If there are no faults, the regulator is live and outputs can be switched. When both the EN and ENBAT pins are held low, the A2550 enters Sleep mode. ENBAT Enable pin; logical OR with EN. Same as EN, except that this pin is high-voltage protected, and specified up to V BB so it can be tied to the battery or power source. Not to exceed VBB because the ESD structure places a diode between the ENBAT and VBB pins. WDI Watchdog Input. Monitors the microcontroller to detect when it stops functioning. This pin is connected to an edge trigger. To avoid a fault, the latter must be triggered before CWD times-out. When not used, WDI is defeated by tying it to NPOR and shorting CWD. CWD Watchdog timer capacitor terminal. Used with WDI. A current source charges the external capacitor tied to this pin. A reverse current source discharges the capacitor when either WDI transitions or the high Trip V oltage, V TRIP(H) , is reached (see specification table for values). The charge-up time defines the maximum period allowed WDI to toggle before a fault is issued; the charge-down time defines the width of NPOR pulses issued to wake-up the microcon- troller. NPOR NOT Power On Reset. This active-low pin indicates a fault. Except for watchdog faults, NPOR is held low during the fault state. Refer to the Fault Logic table to determine which faults are latched. Watchdog faults generate a train of pulses to “wake up” the microcontroller. CPOR Power-On Reset timer capacitor terminal. When- ever VREG5 first charges up (at start-up or when a fault is cleared) a “fault” condition remains in effect until the onboard current source drives CPOR to the high Trip V olt- age, V TRIP(H) . This allows external circuits, such as a micro- controller, to be initialized before activating the outputs. CPOR is defeated by pulling it high to VREG5 with a 50 k resistor. INx Input pin. Active-high CMOS input. Internally tied to 200 k pull-down resistors. OUTx Output pin. Open drain DMOS. Clamps to a voltage greater than V BB when an inductive load is switched off. Includes current mirror for overcurrent protection. VBB Power pin, or “battery.” Specified for automotive volt- ages. VREG5 5 V Regulator output. Clamped at the Current Limit Level (IREG5Lim) for excessive loads. As load resistance decreases, VREG5 is pulled below the UVLO level. In that case, a fault is generated (NPOR low). LGND Logic Ground. The reference pin for the logic circuits. Must be connected to PGND externally. PGND Power Ground. The reference pin for the outputs (OUTx). Must be connected to LGND externally. Functional Description

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 8Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. 1. 5 V signal to wake up microcontroller. 2. OUTx enabled with first watchdog pulse. 3. Power ramp-up sequence with watchdog active. 4. NPOR inactive, but outputs not enabled until watchdog detected. Timing Diagram: Initial Start-up and Exiting Sleep Mode ~INx WDI CWD NPOR EN or ENBAT CPOR VREG5 VBB Internal Vref OUTx ~INx tPORtPOR Internal Vref 1 2 3 4

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 9Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. 1. Missing watchdog detected (WDI low). 2. NPOR pulses generated periodically. 3. NPOR inactive, but outputs not enabled until watchdog detected. 4. Missing watchdog detected (WDI low, steps 2 and 3 repeat). WDI CWD NPOR CPOR VREG5 internal Vref ~INxoutputs enabled tWDR tWD OUTx 1 2 3 4 Timing Diagram: Watchdog Monitoring

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 10Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. 1. VREG5 undervoltage detected. 2. VREG5 recovers, and after it rises above V UVREG5 + VUVREG5(Hys), UVLO flag is deactivated and CPOR recharges. 3. NPOR inactive, but outputs not enabled until watchdog detected. 4. TSD event detected and NPOR is activated. When V REG5 ≤ VUVREG5 , VREG5 shuts down. 5. TSD flag deactivated (VREG5 allowed to rise; steps 2 and 3 repeat) WDI CWD NPOR Internal VREG5 UVLO CPOR VREG5 VBB Internal Vref Internal Vref outputs enabled ~INx Internal TSD ~INxOUTx VUVREG5 1 2 3 4 5 Timing Diagram: VREG5 UVLO and TSD Monitoring

11Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. the rated regulator current, in normal operation. section. The fault logic is described in table 1.

• watchdog alarm
• VREG5 falls below the UVLO level In addition, the following conditions cause a low NPOR signal if the NPOR pin is pulled up by VREG5 (because these conditions disable VREG5):
• overtemperature (Thermal Shut Down)
• no ENABLE signal (EN = ENBAT = 0) Applications Information 0 5 10 15 20 VBB (V) IREG5(max) (mA)

Table 1. Fault Logica 1 0 0 0 0 1 1 1 INx Normal Operation: OUTx active for INx active. aX indicates “don’t care,” Z indicates high impedence. bThis entry is a logical OR of the EN and ENBAT pins. Figure 3. Current Capability of the 5 V Regulator (VREG5)

12Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. See the specification tables for tolerances. nominal capacitances listed. rent will trip each time INx is reapplied. able sleep mode by tying ENBAT to VBB. resistance, RθJA , are given in the specification tables.

• PBIAS from the supply bias current
• PREG from the linear regulator voltage drop
• PLS from low-side driver conduction For example, to determine if TJ is in an acceptable range, given: R θJA = 55°C/W , and T A = 125°C ; and PBIAS = VBB × IBBQ (7) = 14 V × 3 mA = 42 mW , and PREG = (VBB – VREG5(min)) × IREG5 (8) = (14 V – 4.9 V) × 20 mA= 182 mW , and Applications Information

Table 2. Timing Set by Capacitors

13Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. need for external freewheeling diodes across inductive loads. Vdc. This applies a negative voltage drop across the load. age until the current decays to zero, as shown in figure 4. Energy loss in the chip, E, may be calculated as follows. Figure 4. Output Voltage Clamping

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 14Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. A more rigorous derivation, including RCOIL during the exponential current decay results in: COIL COIL COIL CL COIL dc L RtR V R Vti exp1)( ⎡ ⎢⎢ ⎥ ⎥⎛⎞ , (17) and COILR () 1ln – CLdc VVt LCOILΔ = . (18) Energy loss in the driver is: .() ()[] CLdcdcCL COIL COILDCCL VVVVR LVV E −−+= 1ln112 (19) Capacitive Loads When capacitive loads are applied to the outputs, the constraint described below applies. Such is the case, for example, when capacitors are attached to the outputs to protect against ESD. Larger capacitors protect against larger ESD voltages. However, the upper limit on capacitance is determined by the blanking time. The latter allows for spuri- ous current spikes and capacitor discharges to be completed before the overcurrent detection circuit senses the output cur- rent (see t BLANK in the Electrical Characteristics table). The blanking time allows a 47 nF capacitor with 20% tolerance and nominal 12 V automotive voltages. Terminal List Table No. Name Description

1 IN1 Activate driver 1

2 IN2 Activate driver 2

3 IN3 Activate driver 3

4 LGND Logic ground; must be connected to PGND externally

5 NPOR Not Power-On Reset

6 WDI WatchDog Input

7 EN Enable (low voltage)

8 VREG5 5V regulator

9 VBB Supply voltage

10 ENBAT Enable (high voltage)

11 CPOR Capacitor terminal for Power-On Reset cycle time

12 CWD Capacitor terminal for WatchDog timing

13 PGND Power ground; must be connected to LGND externally

14 OUT3 Low side driver 3

15 OUT2 Low side driver 2

16 OUT1 Low side driver 1

– PAD Exposed pad for enhanced thermal performance OUT1 OUT2 OUT3 PGND CWD CPOR ENBAT VBB IN1 IN2 IN3 LGND NPOR WDI EN VREG5 PAD Pin-out Diagram

Relay Driver with 5 V Regulator for Automotive ApplicationsA2550 15Allegro MicroSystems, Inc. Worcester, Massachusetts 01615-0036 U.S.A. 16-Pin TSSOP (Suffix LP) with Exposed Pad Copyright ©2006-2010, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com CSEATING PLANEC0.10 16X 0.65 0.45 1.70 3.00 5.00 ±0.10 3.00 3.00 3.00

1.20 MAX

0.15 MAX

0.65 0.25 (1.00) 4° ±4 0.25 +0.05 –0.06 0.15 +0.05 –0.06 GAUGE PLANE SEATING PLANE B A A Terminal #1 mark area B For Reference Only (reference JEDEC MO-153 ABT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) PCB Layout Reference View Exposed thermal pad (bottom surface) C C