DATASHEET SEARCH SITE
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Description
The Allegro™ A1210-A1214 Hall-effect latches are next generation replacements for the popular Allegro 317x and 318x lines of latching switches. The A121x family, pro- duced with BiCMOS technology, consists of devices that feature fast power-on time and low-noise operation. Device programming is performed after packaging, to ensure increased switchpoint accuracy by eliminating offsets that can be induced by package stress. Unique Hall element geometries and low-offset amplifiers help to minimize noise and to reduce the residual offset voltage normally caused by device overmolding, temperature excursions, and thermal stress. The A1210-A1214 Hall-effect latches include the following on a single silicon chip: voltage regulator, Hall-voltage gen- erator, small-signal amplifier, Schmitt trigger, and NMOS output transistor. The integrated voltage regulator permits operation from 3.8 to 24 V . The extensive on-board protec- tion circuitry makes possible a ±30 V absolute maximum voltage rating for superior protection in automotive and industrial motor commutation applications, without adding external components. All devices in the family are identical except for magnetic switchpoint levels. The small geometries of the BiCMOS process allow these devices to be provided in ultrasmall packages. The package styles available provide magnetically optimized solutions for most applications. Package LH is an SOT23W, a min- iature low-profile surface-mount package, while package UA is a three-lead ultramini SIP for through-hole mounting. Each package is lead (Pb) free, with 100% matte tin plated leadframes. A1210-DS, Rev. 10 Features and Benefits ▪ Continuous-time operation ▫ Fast power-on time ▫ Low noise ▪ Stable operation over full operating temperature range ▪ Reverse battery protection ▪ Solid-state reliability ▪ Factory-programmed at end-of-line for optimum performance ▪ Robust EMC performance ▪ High ESD rating ▪ Regulator stability without a bypass capacitor Continuous-Time Latch Family Functional Block Diagram Not to scale A1210, A1211, A1212, A1213, and A1214 3 pin SIP (suffix UA)
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 2Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A. Selection Guide Part Number Packing* Mounting Ambient, T A BRP (Min) B OP (Max) A1210ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 85ºC –150 150A1210LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 150ºC A1210LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1211LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole –40ºC to 150ºC –180 180 A1212LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 150ºC A1212LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1213LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 150ºC –200 200 A1213LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole A1214LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –40ºC to 150ºC –300 300 A1214LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole *Contact Allegro for additional packing options. Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Supply Voltage V CC 30 V Reverse Supply Voltage V RCC –30 V Output Off Voltage V OUT 30 V Reverse Output Voltage V ROUT –0.5 V Output Current I OUTSINK 25 mA Magnetic Flux Density B 1 G = 0.1 mT (millitesla) Unlimited G Operating Ambient Temperature T A Range E –40 to 85 ºC Range L –40 to 150 ºC Maximum Junction Temperature T J(max) 165 ºC Storage Temperature T stg –65 to 170 ºC
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 3Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Terminal List Name Description Number Package LH Package UA VCC Connects power supply to chip 1 1 VOUT Output from circuit 2 3 GND Ground 3 2 Package UA, 3-pin SIPPackage LH, 3-pin Surface Mount 1 32GND VOUT VCC 1 2
3 GND
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 4Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. DEVICE QUALIFICATION PROGRAM Contact Allegro for information. EMC (Electromagnetic Compatibility) REQUIREMENTS Contact Allegro for information. OPERATING CHARACTERISTICS over full operating voltage and ambient temperature ranges, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Units
Electrical Characteristics
1 VCC Operating, TJ < 165°C 3.8 – 24 V Output Leakage Current I OUTOFF VOUT = 24 V, B < BRP –– 1 0 μA Output On Voltage V OUT(SAT) IOUT = 20 mA, B > BOP – 215 400 mV Power-On Time2 tPO Slew rate (dVCC/dt) < 2.5 V/μs, B > BOP + 5 G or B < BRP – 5 G ––4 μs Output Rise Time3 tr VCC = 12 V, RLOAD = 820 Ω, CS = 12 pF – – 400 ns Output Fall Time3 tf VCC = 12 V, RLOAD = 820 Ω, CS = 12 pF – – 400 ns Supply Current ICCON B > BOP – 4.1 7.5 mA ICCOFF B < BRP – 3.8 7.5 mA Reverse Battery Current I RCC VRCC = –30 V – – –10 mA Supply Zener Clamp Voltage V Z ICC = 10.5 mA; TA = 25°C 32 – – V Supply Zener Current4 IZ VZ = 32 V; TA = 25°C – – 10.5 mA Magnetic Characteristics5 Operate Point B OP A1210 South pole adjacent to branded face of device 25 78 150 G A1211 15 87 180 G A1212 50 107 175 G A1213 80 – 200 G A1214 140 – 300 G Release Point B RP A1210 North pole adjacent to branded face of device –150 –78 –25 G A1211 –180 –95 –15 G A1212 –175 –117 –50 G A1213 –200 – –80 G A1214 –300 – –140 G Hysteresis B HYS A1210 BOP – BRP 50 155 – G A1211 80 180 – G A1212 100 225 350 G A1213 160 – 400 G A1214 280 – 600 G 1 Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section. 2 For VCC slew rates greater than 250 V/μs, and TA = 150°C, the Power-On Time can reach its maximum value. 3 CS =oscilloscope probe capacitance. 4 Maximum current limit is equal to the maximum ICC(max) + 3 mA. 5 Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for sou th-polarity magnetic fields. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the field is indicated by the absolute value of B, and the sign indicates the polarity of the field (for example, a –100 G field and a 100 G field ha ve equivalent strength, but opposite polarity).
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 5Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions Value Units Package Thermal Resistance RθJA Package LH, on single layer, single-sided PCB with copper limited to solder pads 228 ºC/W Package LH, on single layer, double-sided PCB with 0.926 in2 copper area 110 ºC/W Package UA on single layer, single-sided PCB with copper limited to solder pads 165 ºC/W 20 40 60 80 100 120 140 160 180 Maximum Allowable VCC (V) TJ(max) = 165ºC; ICC = ICC(max) Power Derating Curve (RθJA = 228 ºC/W) Minimum-K PCB, Package LH (RθJA = 110 ºC/W) Low-K PCB, Package LH (RθJA = 165 ºC/W) Minimum-K PCB, Package UA VCC(min) VCC(max) 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 Temperature (°C) Power Dissipation, PD (mW) Power Dissipation versus Ambient Temperature θJA = 165 ºC/W) Minimum-K PCB, Pac kage UA θJA = 228 ºC/W) Minimum- K PCB, Package LH θJA = 11 0 ºC/W) Low-K PCB , Package LH 110
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 6Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Characteristic Data TA (°C) Supply Current (On) versus Ambient Temperature VCC (V) ICCON (mA) 24 3.8 TA (°C) Supply Current (Off) versus Ambient Temperature VCC (V) ICCOFF (mA) 24 3.8 TA (°C) Output Voltage (On) versus Ambient Temperature VCC (V) VOUT(SAT) (mV) 3.8 Supply Current (On) versus Supply Voltage TA (°C) ICCON (mA) VCC (V) –40 150 Supply Current (Off) versus Supply Voltage TA (°C) ICCOFF (mA) VCC (V) –40 150 Output Voltage (On) versus Supply Voltage TA (°C) VOUT(SAT) (mV) VCC (V) –40 150 1.0 2.0 3.0 4.0 5.0 7.0 6.0 8.0 1.0 2.0 3.0 4.0 5.0 7.0 6.0 8.0 1.0 2.0 3.0 4.0 5.0 7.0 6.0 8.0 1.0 2.0 3.0 4.0 5.0 7.0 6.0 8.0 –50 0 50 100 150 0 5 10 15 20 25 –50 0 50 100 150 0 5 10 15 20 25 –50 0 50 100 150 0 5 10 15 20 25 100 150 200 250 300 350 400 100 150 200 250 300 350 400
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 7Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. VCC (V) 3.8 TA (°C) VCC (V) 3.8 VCC (V) 3.8 TA (°C) –40 150 TA (°C) –40 150 TA (°C) –40 150 (A1210) Operate Point versus Ambient Temperature BOP (G) (A1210) TA (°C) Release Point versus Ambient Temperature BRP (G) (A1210) (A1210) (A1210) (A1210) TA (°C) Hysteresis versus Ambient Temperature BHYS (G) BOP (G)BRP (G)BHYS (G) Operate Point versus Supply Voltage Release Point versus Supply Voltage VCC (V) VCC (V) TA (°C) VCC (V) Hysteresis versus Supply Voltage 125 100 150 -150 -125 -100 -50 -75 -25 –50 0 50 100 150 0 5 10 15 20 25 –50 0 50 100 150 0 5 10 15 20 25 –50 0 50 100 150 0 5 10 15 20 25 100 125 150 175 200 225 125 100 150 -150 -125 -100 -50 -75 -25 100 125 150 175 200 225
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 8Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. VCC (V) 3.8 TA (°C) VCC (V) 3.8 VCC (V) 3.8 (A1211) Operate Point versus Ambient Temperature BOP (G) (A1211) TA (°C) Release Point versus Ambient Temperature BRP (G) (A1211) TA (°C) Hysteresis versus Ambient Temperature BHYS (G) TA (°C) VCC (V) 3.8 TA (°C) VCC (V) 3.8 VCC (V) 3.8 (A1212) Operate Point versus Ambient Temperature BOP (G) (A1212) TA (°C) Release Point versus Ambient Temperature BRP (G) (A1212) TA (°C) Hysteresis versus Ambient Temperature BHYS (G) TA (°C) –50 0 50 100 150 –50 0 50 100 150 –50 0 50 100 150 140 115 165 -180 -130 -155 -105 -55 -80 -30 100 120 140 160 180 200 220 240 –50 0 50 100 150 –50 0 50 100 150 –50 0 50 100 150 -50 -25 125 150 100 175 -150 -125 -100 -50 -75 -175 100 150 200 250 300 350
Worcester, Massachusetts 01615-0036 U.S.A. fastest available power-on settling time and frequency response. chopper-stabilization offset cancellation algorithm. are the clear choice for such applications. Track-and-Hold Signal Demodulator. Figure 1. Switching Behavior of Latches. On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the using a circuit such as that shown in Panel B.
Worcester, Massachusetts 01615-0036 U.S.A. Figure 2. Continuous-Time Application, B < BRP.. This figure illustrates the use of a quick cycle for chopping VCC in order to conserve battery power. Position 1, power is applied to the device. Position 2, the output assumes the correct state at a time prior to the maximum Power-On Time, tPO(max). valid, a control unit reads the output. Position 5, power is removed from the device.
- Hall-Effect IC Applications Guide, Application Note 27701
- Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead Welding and Lead Forming, Application Note 27703.1
- Soldering Methods for Allegro’ s Products – SMT and Through- Hole, Application Note 26009 All are provided in Allegro Electronic Data Book, AMS-702, and the Allegro Web site, www.allegromicro.com.
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 11Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Power Derating Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating sup- plied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating T J. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RJA, is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, R JC, is relatively small component of RJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate T J, at PD. PD = VIN × IIN (1) T J = TA + ΔT (3) For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 4 mA, and RJA = 140 °C/W, then: P D = VCC × ICC = 12 V × 4 mA = 48 mW T = PD × RJA = 48 mW × 140 °C/W = 7°C A worst-case estimate, PD(max), represents the maximum allow- able power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RJA and TA. Example: Reliability for VCC at TA = 150°C, package UA, using minimum-K PCB. Observe the worst-case ratings for the device, specifically: RJA = 165°C/W, TJ(max) = 165°C, VCC(max) = 24 V , and ICC(max) = 7.5 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = Tmax ÷ RJA = 15°C ÷ 165 °C/W = 91 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 7.5 mA = 12.1 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli- able operation between VCC(est) and VCC(max) requires enhanced RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions.
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 12Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package LH, 3-Pin (SOT-23W)
0.55 REF
0.25 BSC
0.95 BSC
0.95 1.00 0.70 2.40 A Active Area Depth, 0.28 mm REF B C C B Reference land pattern layout All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Branding scale and appearance at supplier discretion A PCB Layout Reference View Standard Branding Reference View Branded Face N = Last two digits of device part number T = Temperature code NNT 2.90 +0.10 –0.20 4°±4° 8X 10° REF 0.180+0.020 –0.053 0.05 +0.10 –0.05
0.25 MIN
1.91 +0.19 –0.06 2.98 +0.12 –0.08 1.00 ±0.13 0.40 ±0.10 For Reference Only; not for tooling use (reference dwg. 802840) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown D Hall element, not to scale D D D1.49 0.96
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 13Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package UA, 3-Pin SIP 231
1.27 NOM
1.02 MAX 45° 45° C 1.52 ±0.05 B Gate and tie bar burr area A B C Dambar removal protrusion (6X) A D E E E 1.44 2.04 E Active Area Depth, 0.50 mm REF Branding scale and appearance at supplier discretion Hall element (not to scale) For Reference Only; not for tooling use (reference DWG-9065) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Mold Ejector Pin Indent D Standard Branding Reference View = Supplier emblem N = Last two digits of device part number T = Temperature code NNT 0.41 +0.03 –0.06 0.43 +0.05 –0.07 14.99 ±0.25 4.09 +0.08 –0.05 3.02 +0.08 –0.05
0.79 REF
10° Branded Face
Continuous-Time Latch Family A1210, A1211, A1212, A1213, and A1214 14Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Copyright ©2005-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Revision History
Revision Revision Date Description of Revision Rev. 10 May 29, 2012 Update UA package drawing