A1128 ALLEGRO
Document overview
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Technical content
Description
The A1128 is a field-programmable, unipolar Hall-effect switch designed for use in high-temperature applications. This device uses a chopper-stabilization technique to eliminate offset inherent in single-element devices. The devices are externally programmable. A wide range of programmability is available on the magnetic operate point, B OP , while the hysteresis remains fixed. This advanced feature allows optimization of the sensor IC switchpoint and can drastically reduce the effects of mechanical placement tolerances found in end-use production environments. A proprietary dynamic offset cancellation technique, with an internal high-frequency clock, reduces the residual offset voltage, which is normally caused by device overmolding, temperature dependencies, and thermal stress. Having the Hall element and amplifier in a single chip minimizes many problems normally associated with low-level analog signals. Two package styles provide a magnetically optimized package for most applications. Type LT is a miniature SOT89/TO-243AA surface mount package that is thermally enhanced with an exposed ground tab, and type UA is a three-lead ultramini SIP for through-hole mounting. The packages are lead (Pb) free, with 100% matte tin plated leadframes. A1128-DS, Rev. 1 Features and Benefits
- Chopper stabilization for stable switchpoints throughout operating temperature range
- Externally programmable: ▫ Operate point (through the VCC pin) ▫ Output polarity ▫ Output fall time for reduced EMI in automotive applications
- On-board voltage regulator for 3 to 24 V operation
- On-chip protection against: ▫ Supply transients ▫ Output short-circuits ▫ Reverse battery condition Highly Programmable Hall-Effect Switch Packages: 3-pin SIP (suffix UA) and 3-pin SOT89 (suffix LT) Functional Block Diagram Not to scale A1128 Trim Control Program Control TC Trim Switchpoint Output Fall Time Output Polarity Signal Recovery Regulator GND VC C CBYPASS VOUT Dynamic Offset Cancellation To All Subcircuits Amp
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A. Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Forward Supply Voltage VCC 28 V Reverse Supply Voltage VRCC –18 V Forward Output Voltage VOUT 26.5 V Reverse Output Voltage VROUT –0.7 V Output Sink Current IOUT(SINK) VCC to VOUT 20 mA Operating Ambient Temperature TA L temperature range –40 to 150 ºC Maximum Junction Temperature TJ(max) 165 ºC Storage Temperature Tstg –65 to 170 ºC Pin-out Diagrams Terminal List Table Number Name Function
1 VCC Input power supply
2 GND Ground
3 VOUT Output signal
Part Number Packing* Package A1128LLTTR-T 7-in. reel, 1000 pieces/reel 3-pin SOT89/TO-243 surface mount A1128LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole *Contact Allegro™ for additional packaging options. 1 32GND VOUT VCC 1 32GND VOUT VCC
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A.
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC 3 12 24 V Supply Current ICC No load on VOUT – – 5.5 mA Supply Zener Clamp Voltage VZSUPPLY TA = 25°C, ICC = ICC(max) + 3 mA 28 – – V Output Zener Clamp Voltage VZOUTPUT IOUT = 3 mA 28 – – V Reverse Battery Zener VRCC – – -18 V Reverse Battery Current IRCC VCC = –18 V –5 – – mA Chopping Frequency fC – 400 – kHz POWER-ON CHARACTERISTICS Power-On Time tPO TA = 25°C; CLOAD (PROBE) = 10 pF – – 30 µs Power-On State2 POS POL = 0; B < BRP , t > ton – High – – POL = 1; B < BRP , t > ton – Low – – OUTPUT STAGE CHARACTERISTICS Output Saturation Voltage V OUT(sat) IOUT = 20 mA – 175 400 mV Output Leakage Current IOFF VOUT = 24 V; Switch state = Off – – 10 µA Output Current Limit IOUT(lim) Short-Circuit Protection, Output = On 30 – 90 mA Output Rise Time3,4 tr VCC = 12 V, RLOAD = 820 Ω, CLOAD = 10 pF – – 2 µs VCC = 12 V, RLOAD = 2 kΩ, CLOAD = 4.7 nF – 21 – µs Output Fall Time4 tf FALL = 0, VCC = 12 V, RLOAD = 820 Ω, CLOAD = 10 pF – – 2 µs FALL = 1, VCC = 12 V, RLOAD = 2 kΩ, CLOAD = 4.7 nF – 6.5 – µs FALL = 2, VCC = 12 V, RLOAD = 2 kΩ, CLOAD = 4.7 nF – 10 – µs FALL = 3, VCC = 12 V, RLOAD = 2 kΩ, CLOAD = 4.7 nF – 12.5 – µs Output Polarity2 POL POL = 0 B > BOP – Low – – B < BRP – High – – POL = 1 B > BOP – High – – B < BRP – Low – – OPERATING CHARACTERISTICS Valid with TA = –40°C to 150°C, CBYPASS = 0.1 µF, VCC = 12 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Unit1 Continued on the next page… tftr V+ % 100 VOUT(High) VOUT(Low) Rise Time and Fall Time Definitions
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. OPERATING CHARACTERISTICS (continued) Valid with TA = –40°C to 150°C, CBYPASS = 0.1 µF, VCC = 12 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Unit1 MAGNETIC CHARACTERISTICS valid VCC = 3 to 24 V, TJ ≤ TJ(max), unless otherwise noted Pre-Programming BOP Target BOPinit TA = 25°C, BOPPOL = 0 – –35 – G TA = 25°C, BOPPOL = 1 – 35 – G Switchpoint Thermal Drift5 ΔBOP LT package, BOP = ±650 G –0.14 –0.03 0.08 %/°C UA package, BOP = ±650 G –0.08 0.00 0.08 %/°C Hysteresis Bhys BOP - BRP 5 15 30 G PROGRAMMING CHARACTERISTICS Switchpoint Magnitude Selection Bits BitBOPSEL – 8 – Bit Switchpoint Polarity Bits BitBOPPOL – 1 – Bit Output Polarity Bits BitPOL – 1 – Bit Fall Time Bits BitFALL – 2 – Bit Device Lock Bits BitLOCK – 1 – Bit Programmable BOP Range BOP TA = 25°C, BOPPOL = 1 (minimum at BOPSEL = 255, maximum at BOPSEL = 0) –650 – 20 G TA = 25°C, BOPPOL = 0 (minimum at BOPSEL = 0, maximum at BOPSEL = 255) –20 – 650 G BOP Step Size ResBOP Bit = LSB of BOPSEL – 4 8 G 11 G (gauss) = 0.1 mT (millitesla). 2Output state when device configured as shown in figure 1. 3Output Rise Time is governed by external circuit tied to VOUT. 4Measured from 10% to 90% steady state output. 5Internal trimming utilized to minimize switchpoint drift across the operating temperature range.
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance RθJA Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W Package LT, 1-layer PCB with copper limited to solder pads 180 ºC/W Package LT, 2-layer PCB with 0.94 in2 copper each side 78 ºC/W *Additional thermal information available on Allegro website. 20 40 60 80 100 120 140 160 180 TA (ºC) Maximum Allowable VCC (V) Power Derating Curve (RθJA = 165 ºC/W) 1-layer PCB, Package UA (RθJA = 180 ºC/W) 1-layer PCB, Package LT (RθJA = 78 ºC/W) 2-layer PCB, Package LT VCC(min) VCC(max) 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 Temperature (°C) Power Dissipation, PD (mW) Power Dissipation (RθJA = 165 ºC/W) 1-layer PCB, Package UA(RθJA = 180 ºC/W) 1-layer PCB, Package LT θJA = 78 ºC/W) 2-layer PCB, Package LT
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Characteristic Performance 500 400 300 200 100 Ambient Temperature, TA (°C) Saturation Voltage, VOUT(sat) (V) -50 -25 0 25 50 75 100 150125 175 VCC (V) 3.3 ICC = 20 mA Saturation Voltage versus Ambient Temperature Ambient Temperature, TA (°C) Supply Current, ICC (mA) -50 -25 0 25 50 75 100 150125 175 VCC (V) 3.3 Supply Current (Off) versus Ambient Temperature -50 -25 0 25 50 75 100 150125 175 Ambient Temperature, TA (°C) Supply Current, ICC (mA) VCC (V) 3.3 Supply Current (On) versus Ambient Temperature
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A.
Application Information
Figure 1. Typical Application Circuit Figure 2. Concept of Chopper Stabilization Technique the offset that can be produced at the output of the Hall sensor IC. induced signal in the frequency domain, through modulation. density logic integration and sample-and-hold circuits.
Worcester, Massachusetts 01615-0036 U.S.A. threshold, BRP , the device output switches on. OPinit is actually positive.
0 BOPinitB–
Figure 3. Hysteresis Diagrams. These plots demonstrate the behavior of the A1128 with the applied magnetic field increasing north or decreasing south magnetic flux density.
Worcester, Massachusetts 01615-0036 U.S.A. age pulses serially through the VCC (supply) pin of the device.
- In Try mode, programmable parameter values are set and mea- sured simultaneously. A parameter value is stored temporarily, and reset after cycling the supply voltage.
- In Blow mode, the value of a programmable parameter may be permanently set by blowing solid-state fuses internal to the device. Device locking is also accomplished in this mode.
- In Read mode, each bit may be verified as blown or not blown. The programming sequence is designed to help prevent the device from being programmed accidentally; for example, as a result of noise on the supply line. Note that, for all programming modes, no parameter programming registers are accessible after the device- level LOCK bit is set. The only function that remains accessible is the overall Fuse Checking feature. Although any programmable variable power supply can be used to generate the pulse waveforms, for design evaluations, Allegro highly recommends using the Allegro Sensor IC Evaluation Kit, available on the Allegro website On-line Store. The manual for that kit is available for download free of charge, and provides additional information on programming these devices. (Note: This kit is not recommended for production purposes.) Definition of Terms Register The section of the programming logic that controls the choice of programmable modes and parameters. Bit Field The internal fuses unique to each register, represented as a binary number. Changing the bit field settings of a particular Programming Guidelines
Table 1. Programming Pulse Requirements, Protocol at TA = 25°C Figure 4. Programming pulse definitions (see table 1)
Worcester, Massachusetts 01615-0036 U.S.A. the internal programming logic. Key A series of voltage pulses used to select a register or mode. binary value. The LSB of a bit field is denoted as code 1, or bit 0. ming code (and parameter value) becomes permanent. blowing. Figure 8 provides an overview state diagram. register. An example register selection key is shown in figure 5. after transiting the register. The same physical registers are used for all programming modes. bined register and mode keys are shown in table 3. wraps back to the beginning of the register, and selects code 0. Figure 5. Example of Try mode register selection pulses, for the BOP Negative Trim, Up-Counting register. Figure 6. Try mode bit field addressing pulses.
Worcester, Massachusetts 01615-0036 U.S.A. code 7 (111) sets FALL to 3 (x11) and sets POL (1xx). power must be cycled after each individual fuse is blown. The fuse for each bit in the bit field must be blown individually. example is shown in figure 11. blow bit 0. The end result would be binary 11 (decimal code 3).
- Select the Output/Lock Bit register key.
- Select Blow mode selection key.
- Address bit 4 (10000) by sending four V
- Send one Blow pulse, at IPP and SRBLOW, and sustain it for
- Delay for a tLOW interval, then power-down.
- Optionally check all fuses.
Figure 7. Example of code 5 broken into its binary components. Table 2. Blow Mode Bit Field Addressing
Worcester, Massachusetts 01615-0036 U.S.A. Table 3. Programming Logic Table entered, wraps back to code 0. 1111 1111 255 BOP selection is at maximum value. entered, wraps back to code 0. 1111 1111 255 BOP selection is at maximum value. 0000 0000 255 BOP selection is at minimum value. 0000 0000 255 BOP selection is at minimum value. x01 1 Output Fall Time (FALL). Code 1 automatically selected. Minimum value. x11 3 Output Fall Time (FALL) selection is at maximum value. 0xx 0 Output Polarity Bit (POL). Default, no fuse blowing required. POL = 0, see figures 3A and 3C. 1xx 4 Output Polarity Bit (POL). Code 1 automatically selected. POL = 1, see figures 3B and 3D. Code references a single bit only. entered. Checks un-blown fuses. Code references a single bit only. 1001 9 Fuse Threshold High Register. Checks blown fuses. 0000 0000 0 BOP magnitude selection. Default, no fuse blowing required. Minimum value, corresponding to BOP(min). 1111 1111 255 BOP magnitude selection. Maximum value, corresponding to BOP(max). 0 0 South field polarity. Default, no fuse blowing required. 1 1 North field polarity. Code 1 (bit 0) automatically selected. 00 0 Output Fall Time (FALL). Default, no fuse blowing required. 000 0 Output Polarity Bit (POL). Default, no fuse blowing required. POL = 0, see figures 3A and 3C. bit 2 only. POL = 1, see figures 3B and 3D. automatically selected. Monitor VOUT after each pulse.
Worcester, Massachusetts 01615-0036 U.S.A. Figure 8. Programming State Diagram
Worcester, Massachusetts 01615-0036 U.S.A. CC , increases by 250 μA if a marginal fuse is detected. POL bit by selecting the Output / Lock bit register, and code 4. Try mode registers. See table 3 for parameter details.
- The power supply used for programming must be capable of delivering at least V PH and 175 mA.
- Be careful to observe the tLOW delay time before powering down the device after blowing each bit.
- Set the LOCK bit (only after all other parameters have been programmed and validated) to prevent any further programming of the device. Read Mode The A1128 features a Read mode that allows the status of each programmable fuse to be read back individually. The status, blown or not blown, of the addressed fuse is determined by moni- toring the state of the VOUT pin. A complete example is shown in figure 9. Read mode uses the same register selection keys as Blow mode (see table 3), allowing direct addressing of the individual fuses in the BOPPOL and BOPSEL registers (do not inadvertently send a Blow pulse while in Read mode). After sending the register and mode selection keys, that is, after the falling edge of the final V PH pulse in the key, the first bit (the LSB) is selected. Each addi- tional VPM pulse addresses the next bit in the selected register, up
Figure 9. Read mode example. Pulse sequence for accessing the BOP Selection register on the VOUT pin will be at GND for blown fuses and at VCC (at VPL or VPM) for un-blown fuses.
Worcester, Massachusetts 01615-0036 U.S.A. LOAD in the Typical Application Circuit diagram). Figure 11. Example of Blow mode programming pulses applied to the VCC pin. In this example, the BOP Magnitude Selection register (BOPSEL) is addressed to code 8 (bit 3, or 3 VPM pulses) and its value is permanently blown. Figure 10. Example of Try mode programming pulses applied to the VCC pin. In this example, BOP Positive Trim, Down- of the register-mode selection key).
Worcester, Massachusetts 01615-0036 U.S.A. polarity, and switchpoints at or near the zero crossing point for B. ble BOP Range, specified in the Operating Characteristics table. nently set using the Blow mode features. value and decreasing to the minimum value. Figure 12. BOP profiles for each of the four BOP Selection virtual registers available in Try mode.
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. The device must be operated below the maximum junction temperature of the device, TJ(max) . Under certain combina- tions of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating T J. (Thermal data is also available on the Allegro MicroSystems website.) The Package Thermal Resistance, RθJA, is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, R θJC, is relatively small component of RθJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN (1) ΔT = PD × RθJA (2) TJ = TA + ΔT (3) For example, given common conditions such as: TA= 25°C, VIN = 12 V, IIN = 4 mA, and RθJA = 140 °C/W, then: PD = VIN × IIN = 12 V × 4 mA = 48 mW Δ T = PD × RθJA = 48 mW × 140 °C/W = 7°C TJ = TA + ΔT = 25°C + 7°C = 32°C A worst-case estimate, PD(max) , represents the maximum allow- able power level, without exceeding TJ(max) , at a selected RθJA and TA. Example: Reliability for VCC at TA = 150°C, package UA, using a single-layer PCB. Observe the worst-case ratings for the device, specifically: RθJA = 165 °C/W, TJ(max) = 165°C, VCC(max) = 24 V , and ICC(max) = 5.5 mA. Calculate the maximum allowable power level, PD(max) . First, invert equation 3: ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165 °C/W = 91 mW Finally, invert equation 1 with respect to voltage: V CC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 5.5 mA = 16.5 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est) . Compare VCC(est) to VCC(max) . If VCC(est) ≤ VCC(max) , then reliable operation between VCC(est) and VCC(max) requires enhanced RθJA. If VCC(est) ≥ VCC(max) , then operation between VCC(est) and VCC(max) is reliable under these condi- tions. Power Derating
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. D Active Area Depth, 0.77 mm Hall element; not to scale D E E EE 1.14 2.24 B Parting Line 321 A C A 10° REF 10° REF 6° REF Gate and tie bar burr areaB 1.04 ±0.15
2.16 REF
0.38 MIN
1.73 ±0.10 2X 1.50 NOM Reference land pattern layout; All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances 4.47 +0.13 –0.08 2.57 +0.03 –0.284.14 +0.10 –0.20 0.41 +0.03 –0.06 0.51 +0.05 –0.07 0.43 +0.05 –0.07 1.45 +0.15 –0.05 Branding scale and appearance at supplier discretion Standard Branding Reference View NNN = Supplier emblem N = Last three digits of device part number Branded Face For Reference Only; not for tooling use (reference DWG-9064) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Updated package drawing only. Allegro package assembly tooling has not changed. 1.50 1.20 0.80 2.60 2.00 2.50 0.70 4.60 C PCB Layout Reference View Basic pads for low-stress, not self-aligning Additional pad for low-stress, self-aligning Additional area for IPC reference layout Package Outline Drawings Package LT 3-Pin SOT-89
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Package UA 3-Pin SIP 2 31
0.79 REF
1.27 NOM
2.16 MAX 0.51 REF 45° C 45° B E E E 2.04 1.44 Gate burr area A B C Dambar removal protrusion (6X) A D E D Branding scale and appearance at supplier discretion Hall element, not to scale Active Area Depth, 0.50 mm REF For Reference Only; not for tooling use (reference DWG-9049) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Standard Branding Reference View = Supplier emblem N = Last three digits of device part number NNN Mold Ejector Pin Indent Branded Face 4.09 +0.08 –0.05 0.41 +0.03 –0.06 3.02 +0.08 –0.05 0.43 +0.05 –0.07 15.75 ±0.51 1.52 ±0.05
Highly Programmable Hall-Effect SwitchA1128 Allegro MicroSystems, LLC Worcester, Massachusetts 01615-0036 U.S.A. Copyright ©2010-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com